HCF40193BE [STMICROELECTRONICS]
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ST 
HCF40193B
PRESETTABLE UP/DOWN COUNTERS
(DUAL CLOCK WITH RESET) BINARY TYPE
■
■
INDIVIDUAL CLOCK LINES FOR COUNTING
UP OR COUNTING DOWN
SYNCHRONOUS HIGH-SPEED CARRY AND
BORROW PROPAGATION DELAYS FOR
CASCADING
■
■
■
ASYNCHRONOUS RESET AND PRESET
CAPABILITY
DIP
SOP
MEDIUM-SPEED OPERATION - f = 8MHz
CL
(typ.) AT 10 V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
ORDER CODES
PACKAGE
TUBE
T & R
■
■
■
DIP
HCF40193BEY
HCF40193BM1
SOP
HCF40193M013TR
I = 100nA (MAX) AT V = 18V T = 25°C
I
DD
A
and BORROW outputs for multiple-stage counting
schemes are provided. The counter is cleared so
that all outputs are in a low state by a high on the
■
■
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
RESET line.
A
RESET is accomplished
asynchronously with the clock. Each output is
individually programmable asynchronously with
the clock to the level on the corresponding jam
input when the PRESET ENABLE control is low.
The counter counts up one count on the positive
clock edge of the CLOCK UP signal provided the
CLOCK DOWN line is high. The counter counts
down one count on the positive clock edge of the
CLOCK DOWN signal provided the CLOCK UP
line is high. The CARRY and BORROW signals
are high when the counter counts up or down. The
CARRY signal goes low one-half clock cycle after
the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low
DESCRIPTION
HCF40193B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40193B Presettable Binary Up/Down Counter
consists of 4 synchronously clocked, GATED "D"
type flip-flops connected as a counter. The inputs
consist of four individual jam lines, a PRESET
ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET.
Four buffered Q signal outputs as well as CARRY
PIN CONNECTION
September 2002
1/12
HCF40193B
one-half clock cycle after the counter reaches its
minimum count in the count-down mode. The
cascading of multiple packages is easily
accomplished without the need for additional
external circuitry by tying the BORROW and
CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the following
package.
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
3, 2, 6, 7
Q1 to Q4
Flip-Flop Outputs
CLOCK
DOWN
4
5
Clock Down Input
CLOCK UP Clock Up Input
PRESET
ENABLE
CARRY
11
Preset Enable Input
12
Count Up (Carry)
13
BORROW Count Down (Borrow)
14
15, 1, 10, 9
8
RESET
J1 to J4
Reset Input
Data Input
V
Negative Supply Voltage
SS
V
16
Positive Supply Voltage
DD
FUNCTIONAL DIAGRAM
2/12
HCF40193B
LOGIC DIAGRAM
TRUTH TABLE
CLOCK UP
CLOCK DOWN
PRESET ENABLE
RESET
ACTION
COUNT UP
NO COUNT
COUNT DOWN
NO COUNT
H
H
H
H
H
H
L
L
L
L
H
H
X
X
X
X
L
L
PRESET
RESET
X
H
(X) : Don’t Care
3/12
HCF40193B
TIMING DIAGRAM
INTERNAL LOGIG OF FLIP-FLOP
4/12
HCF40193B
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
DC Input Voltage
DC Input Current
-0.5 to +22
V
V
DD
V
-0.5 to V + 0.5
I
DD
I
± 10
200
mA
mW
mW
°C
I
P
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
D
100
T
-55 to +125
op
T
Storage Temperature
-65 to +150
°C
stg
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V pin voltage.
SS
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
3 to 20
0 to V
V
V
DD
V
Input Voltage
I
DD
T
Operating Temperature
-55 to 125
°C
op
5/12
HCF40193B
DC SPECIFICATIONS
Test Condition
|I | V
DD
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
V
I
O
O
(V)
(V)
(µA) (V)
Min. Typ. Max. Min. Max. Min. Max.
I
Quiescent Current
0/5
0/10
0/15
0/20
0/5
5
0.04
0.04
0.04
5
150
300
150
300
L
10
15
20
10
20
µA
600
600
0.08 100
3000
3000
V
High Level Output
Voltage
<1
<1
<1
<1
<1
<1
<1
<1
5
4.95
9.95
4.95
9.95
4.95
9.95
OH
0/10
0/15
5/0
10
V
V
V
V
15 14.95
14.95
14.95
V
Low Level Output
Voltage
5
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
OL
10/0
15/0
10
15
V
High Level Input
Voltage
0.5/4.5
1/9
5
3.5
7
3.5
7
3.5
7
IH
10
15
5
1.5/13.5 <1
11
11
11
V
Low Level Input
Voltage
4.5/0.5
9/1
<1
<1
1.5
3
1.5
3
1.5
3
IL
10
15
5
13.5/1.5 <1
4
4
4
I
Output Drive
Current
0/5
0/5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
<1
<1
<1
<1
<1
<1
<1
-1.36 -3.2
-1.1
-0.36
-0.9
-2.4
0.36
0.9
-1.1
-0.36
-0.9
-2.4
0.36
0.9
OH
5
-0.44
-1.1
-3.0
0.44
1.1
-1
-2.6
-6.8
1
mA
mA
0/10
0/15
0/5
10
15
5
I
Output Sink
Current
OL
0/10
0/15
10
15
2.6
6.8
3.0
2.4
2.4
I
Input Leakage
Current
I
-5
0/18
Any Input
Any Input
18
±0.1
±1
±1
µA
±10
C
Input Capacitance
5
7.5
pF
I
The Noise Margin for both "1" and "0" level is: 1V min. with V =5V, 2V min. with V =10V, 2.5V min. with V =15V
DD
DD
DD
6/12
HCF40193B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, C = 50pF, R = 200KΩ, t = t = 20 ns)
amb
L
L
r
f
Test Condition
Value (*)
Unit
Symbol
Parameter
V
(V)
Min. Typ. Max.
DD
t
t
Propagation Delay Time
Clock Up or Clock Down to
Q Reset to Q
5
250
120
90
500
240
180
400
200
140
320
160
120
600
300
220
200
100
80
PLH PHL
10
15
5
ns
ns
PE to Q
200
100
70
10
15
5
Clock Up to Carry
160
80
10
15
5
ns
Clock Down to Borrow
60
Reset or PR to Borrow or
Carry
300
150
110
100
50
10
15
5
ns
t
t
Transition Time
THL TLH
10
15
5
ns
40
t
Removal Time
Reset or PE
80
40
40
rem*
10
15
5
20
ns
30
15
t
Clock Input Pulse Width
Reset
480
300
260
240
150
130
120
85
W
10
15
5
ns
PE
240
170
140
180
90
10
15
5
ns
70
Clock
90
10
15
5
45
ns
30
60
t t
Clock Input Rise or Fall
Time
15
r
f
10
15
5
15
µs
5
f
Maximum Clock Input
Frequency
2
5
4
8
CL
10
15
MHz
5.5
11
(*) The time required for Reset or Preset Enable control to be removed before clocking (see timing diagram).
7/12
HCF40193B
TEST CIRCUIT
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)
L
L
T
= 200KΩ
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
8/12
HCF40193B
WAVEFORM 2 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)
TYPICAL APPLICATION: CASCADED COUNTER PACKAGES
9/12
HCF40193B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
0.51
0.77
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
10/12
HCF40193B
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45˚ (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
˚ (max.)
8
PO13H
11/12
HCF40193B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
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12/12
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