HCF4031B [STMICROELECTRONICS]
64-STAGE STATIC SHIFT REGISTER; 64级静态移位寄存器
| 型号： | HCF4031B |
| 厂家： | 
ST |
| 描述： | 64-STAGE STATIC SHIFT REGISTER |
| 文件： | 总12页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCC/HCF4031B
64-STAGE STATIC SHIFT REGISTER
.
.
FULLY STATIC OPERATION : DC to 16MHz
(TYP.) @ VDD – VSS = 15V
STANDARD TTL DRIVE CAPABILITY ON Q
OUTPUT
RECIRCULATION CAPABILITY
THREE CASCADING MODES :
DIRECT CLOCKING FOR HIGH-SPEED
OPERATION
.
.
EY
F
(Plastic Package)
(Ceramic Package)
DELAYEDCLOCKING FORREDUCED CLOCK
DRIVE REQUIREMENTS
ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA at 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALLREQUIREMENTS OF JEDECTEN-
TATIVE STANDARD NO. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
.
.
C1
(Chip Carrier)
.
.
ORDER CODES :
HCC4031BF
HCF4031BEY
HCF4031BC1
.
.
PIN CONNECTIONS
DESCRIPTION
The HCC4031B (extended temperature range) and
HCF4031B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The HCC/HCF4031B is a static shift register that
contains 64 D-type, master-slave flip-flop stages
and one stage which is a D-type master flip-flop only
(referred to as a 1/2 stage). The logic level present
at the DATA input is transferred into the first stage
and shifted one stage at each positive-going clock
transition. Maximum clock frequencies up to 16
Megahertz (typical) can be obtained. Because fully
static operation is allowed, information can be per-
manently stored with the clock line in either the low
or high state. The HCC/HCF4031B has a MODE
CONTROL input that, when in thehigh state, allows
operation in the recirculating mode. The MODE
CONTROLinputcan also beused toselectbetween
two separate data sources. Register packages can
be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock
output(CLD) isprovided that enables cascading reg-
June 1989
1/12
HCC/HCF4031B
ister packages while allowing reduced clock drive
fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from
the 1/2 stage, which is available on the next nega-
tive-going transition of the clock after the Q output
occurs. This delayed output, like the delayed clock
CLD, is used with clocks having slow rise and fall
times.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply Voltage : HCC Types
HCF Types
Value
Unit
VDD
*
– 0.5 to + 20
– 0.5 to + 18
V
V
VI
II
Input Voltage
– 0.5 to VDD + 0.5
V
DC Input Current (any one input)
± 10
mA
mW
Pt ot
Total Power Dissipation (per package)
Dissipation per Output Transistor
200
for Top = Full Package-temperature Range
100
mW
To p
Tstg
Operating Temperature : HCC Types
HCF Types
– 55 to + 125
– 40 to + 85
°C
°C
Storage Temperature
– 65 to + 150
°C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation ofthe device attheseor anyother conditions abovethose indicated in the operational sections of this specification is not implied.
Exposureto absolute maximum rating conditions for external periods may affect device reliability.
* Allvoltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage : HCC Types
HCF Types
Value
Unit
VDD
3 to + 18
3 to + 15
V
V
VI
Input Voltage
0 to VDD
V
Top
Operating Temperature : HCC Types
HCF Types
– 55 to + 125
– 40 to + 85
°C
°C
2/12
HCC/HCF4031B
LOGIC DIAGRAM AND TRUTH TABLES
INPUT CONTROL CIRCUIT
Bit Into
Stage 1
Data
Recirc.
Mode
1
0
X
X
1
0
0
0
1
1
1
0
1
0
X
X
TYPICAL STAGE
OUTPUT FROM Q’ (pin 5)
Data
CL
Data + 1
Data + 6 4
CL
Data + 64.5
–
–
0
0
1
/
/
0
\
0
–
–
–
–
1
X
1
\
1
–
–
–
–
\
NC
X
NC
/
–
–
1 = HIGHLEVEL
0 = LOW LEVEL
NC = NO CHANGE
X = DON’T CARE
3/12
HCC/HCF4031B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Test Conditions
Value
Symbol
Parameter
Quiescent
Unit
VI
(V)
VO
(V)
|IO
(µA) (V)
|
VD D
T Lo w
*
25°C
T High*
Min. Max. Min. Typ. Max. Min. Max.
IL
0/ 5
0/10
0/15
0/20
0/ 5
0/10
0/15
5
5
10
20
100
20
40
80
0.04
0.04
0.04
5
10
20
150
300
600
3000
150
300
600
Current
10
15
20
5
10
15
HCC
Types
µA
0.08 100
0.04
0.04
0.04
20
40
80
HCF
Types
VOH
VOL
VIH
VIL
Output High
Voltage
0/ 5
0/10
0/15
5/0
10/0
15/0
< 1
< 1
< 1
< 1
< 1
< 1
5
4.95
4.95
9.95
14.95
4.95
9.95
14.95
10 9.95
15 14.95
5
10
15
5
10
15
5
10
15
V
V
V
V
Output Low
Voltage
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
Input High
Voltage
0.5/4.5 < 1
1/9 < 1
1.5/13.5 < 1
3.5
7
11
3.5
7
11
3.5
7
11
Input Low
Voltage
4.5/0.5 < 1
1.5
3
4
1.5
3
4
1.5
3
4
9/1
< 1
13.5/1.5 < 1
IOH
Output
Source
Current
(Source)
Q, Q, Q
CLD
0/ 5
0/ 5
0/10
0/15
0/ 5
0/ 5
0/10
0/15
0/ 5
0/10
0/15
0/ 5
0/10
0/15
0/ 5
0/10
0/15
0/ 5
0/10
0/15
2.5
4.6
9.5
13.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
0.4
0.5
1.5
0.4
0.5
1.5
0.4
5
5
– 2
– 0.64
– 1.6 – 3.2
– 0.51 – 1
– 1.3 – 2.6
– 3.4 – 6.8
– 1.36 – 3.2
– 0.44 – 1
– 1.1 – 2.6
– 3.0 – 6.8
– 1.15
– 0.36
– 0.9
– 2.4
– 1.1
– 0.36
– 0.9
– 2.4
1.44
3.6
HCC
Types
10 – 1.6
15 – 4.2
5
5
10 – 1.3
15 – 3.6
5
mA
– 1.53
– 0.52
HCF
Types
IOL
Output
Sink
Current Q
2.56
6.4
2.04
5.2
4
10.4
HCC
Types
10
15 16.8
2.08
13.6 27.2
1.74
9.6
mA
mA
5
4
1.43
3.74
9.52
0.36
0.9
2.4
0.36
0.9
HCF
Types
10 5.01
15 13.6
5
10
15
5
10
15
4.42 10.4
11.56 27.2
IOL
Output
Sink
Current
Q, Q’
CLD
0.64
1.6
4.2
0.52
1.3
3.6
0.51
1.3
3.4
0.44
1.1
3.0
1
HCC
Types
2.6
6.8
1
2.6
6.8
HCF
Types
0.5
1.5
2.4
IIH, IIL Input
Leakage
Current
HCC
Types
0/18
18
15
± 0.1
± 0.3
±10–5 ± 0.1
± 1
± 1
Any Input
µA
HCF
Types
±10–5 ± 0.3
0/15
CI
Input Capacitance
Any Input
5
7.5
pF
* TLow = – 55°C for HCC device : – 40°C for HCF device.
* THigh = + 125°C for HCC device : + 85°C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. withVDD = 5V, 2V min. withVDD = 10V, 2.5 V min. with VDD = 15V.
4/12
HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall times = 20ns)
Test Conditions
Value
Symbol
tPHL
tPL H, tPLH Clock to Q,
Clock to Q
Parameter
Unit
V D D (V) Min. Typ. Max.
,
Propagation Delay Time :
5
250
110
90
190
80
65
100
50
40
100
50
40
50
25
20
30
15
10
30
15
10
120
50
40
4
500
220
180
380
160
130
200
100
80
ns
10
15
5
tPHL
,
Propagation Delay Time :
tPL H, tPHL Clock to Q’
Clock to Q
ns
ns
10
15
5
Clock to CLD
10
15
5
t
THL’, tTLH Transition Time :
(any output, except QtTHL
200
100
80
)
ns
10
15
5
tTHL
tset up
tho ld
tW
Q,
100
50
ns
10
15
5
40
Data Setup Time
Data Hold Time
Clock Pulse Width
60
ns
10
15
5
30
20
60
ns
10
15
5
30
20
240
100
80
ns
10
15
5
fmax
Maximum Clock Input
Frequency**
2
5
6
MHz
µs
10
15
5
10
12
tr, tf
Clock Input Rise or Fall Time*
1000
1000
200
10
15
*
If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmition time of the output driving stage.
*
* Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
1
fmax =
where n = nimber of packages
(n-1) CLD prop. delay + Q prop. delay + set-up time
b) Not Usng Delaye Clock :
1
fmax =
propagation delay + set-up time
5/12
HCC/HCF4031B
Typical Output Low (sink) Current Characteristics.
Minimum Output Low (sink) Current Charac-
teristics.
Typical Output High (source) Current Charac-
teristics.
Minimum Output High (source) Current Charac-
teristics.
6/12
HCC/HCF4031B
TYPICAL APPLICATIONS
CASCADING USINGDIRECT CLOCKING FORHIGH SPEEDOPERATION (SEE CLOCKRISE ANDFALL
TIME REQUIREMENT).
CASCADING USING DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS.
7/12
HCC/HCF4031B
TYPICAL APPLICATIONS (continued)
CASCADING USING HALF- CLOCK-PULSE DELAYED DATA OUTPUT (Q’) TO PERMIT USE OF SLOW
RISE AND FALL TIME CLOCK INPUTS.
TEST CIRCUITS
Quiescent Device Current.
Noise Immunity.
Input Leakage Current.
8/12
HCC/HCF4031B
Plastic DIP16 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
0.77
TYP.
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
9/12
HCC/HCF4031B
Ceramic DIP16/1 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
20
MIN.
MAX.
0.787
0.276
A
B
7
D
E
3.3
0.130
0.700
0.38
0.015
e3
F
17.78
2.29
0.4
2.79
0.55
1.52
0.31
1.27
10.3
8.05
5.08
0.090
0.016
0.046
0.009
0.020
0.110
0.022
0.060
0.012
0.050
0.406
0.317
0.200
G
H
L
1.17
0.22
0.51
M
N
P
7.8
0.307
Q
P053D
10/12
HCC/HCF4031B
PLCC20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
9.78
8.89
4.2
TYP.
MAX.
10.03
9.04
MIN.
0.385
0.350
0.165
MAX.
0.395
0.356
0.180
A
B
D
4.57
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38
0.290
0.330
0.004
e
1.27
5.08
0.38
0.050
0.200
0.015
e3
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
P027A
11/12
HCC/HCF4031B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12
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