HD1750JL_07 [STMICROELECTRONICS]

Very high voltage NPN power transistor for high definition and slim CRT display; 高清和超薄CRT显示器非常高电压NPN功率晶体管
HD1750JL_07
型号: HD1750JL_07
厂家: ST    ST
描述:

Very high voltage NPN power transistor for high definition and slim CRT display
高清和超薄CRT显示器非常高电压NPN功率晶体管

晶体 显示器 晶体管
文件: 总10页 (文件大小:227K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HD1750JL  
Very high voltage NPN power transistor for high definition and slim  
CRT display  
PRELIMINARY DATA  
Features  
State-of-the-art technology: diffused collector  
“enhanced generation“ EHVS1  
Wider range of optimum drive conditions  
Less sensitive to operating temperature  
variation  
In compliance with the 2002/93/EC European  
3
2
directive  
1
TO-264  
Description  
The HD1750JL is manufactured using Diffused  
Collector in Planar technology adopting new and  
Enhanced High Voltage Stricture 1 (E.H.V.S.1)  
developed to fit High-Definition CRT display. The  
new HD product series show improved silicon  
efficiency bringing updated performance to the  
Horizontal Deflection stage.  
Internal schematic diagram  
Applications  
High-definition and slim CRT TV and monitors  
Order code  
Part number  
Marking  
Package  
Packaging  
HD1750JL  
HD1750JL  
TO-264  
Tube  
February 2007  
Rev 3  
1/10  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
10  
Electrical ratings  
HD1750JL  
1
Electrical ratings  
Table 1.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
VCES  
VCEO  
VEBO  
IC  
Collector-emitter voltage (VBE = 0)  
Collector-emitter voltage (IB = 0)  
Emitte-base voltage (IC = 0)  
Collector current  
1700  
800  
V
V
10  
V
24  
A
ICM  
Collector peak current (tP < 5ms)  
Base current  
36  
A
IB  
12  
A
IBM  
Base peak current (tP < 5ms)  
Total dissipation at Tc = 25°C  
Storage temperature  
18  
A
PTOT  
TSTG  
TJ  
200  
W
°C  
°C  
-65 to 150  
150  
Max. operating junction temperature  
Table 2.  
Symbol  
Thermal data  
Parameter  
Value  
Unit  
RthJ-C  
Thermal resistance junction-case max  
0.625  
°C/W  
2/10  
HD1750JL  
Electrical characteristics  
2
Electrical characteristics  
(T  
=25°C unless otherwise specified)  
CASE  
Table 3.  
Symbol  
Electrical characteristics  
Parameter  
Test conditions  
VCE = 1700V  
Min. Typ. Max. Unit  
Collector cut-off current  
(VBE = 0)  
0.2  
2
mA  
mA  
ICES  
VCE = 1700V; TC = 125°C  
Emitter cut-off current  
(IC = 0)  
IEBO  
VEB = 5V  
10  
µA  
Collector-emitter  
sustaining voltage (IB = 0)  
(1)  
IC = 10mA  
800  
10  
V
VCEO(sus)  
Emitter-base saturation  
voltage (IC = 0)  
(1)  
IE = 10mA  
V
V
V
VEBO  
Collector-emittersaturation  
voltage  
(1)  
(1)  
IC = 12A; IB = 3A  
IC = 12A; IB = 3A  
3
VCE(sat)  
Base-emitter saturation  
voltage  
0.95  
30  
1.5  
VBE(sat)  
IC = 1A;  
VCE = 5V  
hFE  
DC current gain  
IC = 12A;  
VCE = 5V 5.5  
IB(on)= 1.8A  
8.5  
IC = 12A;  
IB(off)= -7.25A;  
VCE(fly)= 1320V;  
Inductive load  
Storage time  
Fall time  
ts  
tf  
3
3.6  
µs  
ns  
VBE(off)= -2.7V;  
300  
450  
LBB(on)= 0.8µH;  
fh= 31520Hz  
IC = 6.5A;  
IB(on)= 1.1A  
IB(off)= -5.25A;  
VCE(fly)= 1220V;  
VBE(off)= -2.7V;  
Inductive load  
Storage time  
Fall time  
ts  
tf  
1.6  
2
µs  
ns  
110  
220  
LBB(on)= 0.25µH;  
fh= 100kHz  
1. Pulsed: pulse duration = 300µs, duty cycle < 2%  
3/10  
Electrical characteristics  
HD1750JL  
2.1  
Electrical characteristics (curve)  
Figure 1.  
Figure 3.  
Figure 5.  
Safe operating area  
Output characteristics  
DC current gain  
Figure 2.  
Figure 4.  
Figure 6.  
Derating curve  
Reverse biased SOA  
DC current gain  
4/10  
HD1750JL  
Electrical characteristics  
Figure 7.  
Collector-emitter saturation Figure 8.  
voltage  
Base-emitter saturation  
voltage  
Figure 9.  
Power losses  
Figure 10. Power losses  
Figure 11. Inductive load switching time Figure 12. Inductive load switching time  
5/10  
Test circuit  
HD1750JL  
3
Test circuit  
Figure 13. Power losses and inductive load switching test circuit  
Figure 14. Reverse biased safe operating area test circuit  
6/10  
HD1750JL  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a Lead-free second level interconnect . The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark.  
ECOPACK specifications are available at: www.st.com  
7/10  
Package mechanical data  
HD1750JL  
Table 4.  
TO-264 Mechanical Data  
Figure 15. TO-264 Drawing  
8/10  
HD1750JL  
Revision history  
5
Revision history  
Table 5.  
Date  
Revision history  
Revision  
Changes  
12-Oct-2006  
17-Oct-2005  
23-Feb-2007  
1
2
3
Initial release.  
Final document  
The document has been reformatted  
9/10  
Revision history  
HD1750JL  
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10/10  

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