HVLED815PFTR [STMICROELECTRONICS]
Offline LED driver with primary-sensing, high power factor up to 15 W; 离线式LED驱动器，具有初级传感，高功率因数高达15 W的
| 型号： | HVLED815PFTR |
| 厂家： | 
ST |
| 描述： | Offline LED driver with primary-sensing, high power factor up to 15 W |
| 文件： | 总36页 (文件大小：1790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HVLED815PF
Offline LED driver with primary-sensing and
high power factor up to 15 W
Datasheet − production data
Features
■ High power factor capability (> 0.9)
■ 800 V, avalanche rugged internal 6 ΩPower
MOSFET
■ Internal high-voltage startup
■ Primary sensing regulation (PSR)
■ +/- 5% accuracy on constant LED output
current
■ Quasi-resonant (QR) operation
■ Optocoupler not needed
SO16N
■ Open or short LED string management
■ Automatic self supply
Table 1.
Device summary
Applications
Order code
Package
Packaging
■ AC-DC LED driver bulb replacement lamps up
HVLED815PF
Tube
to 15 W, with high power factor
SO16N
HVLED815PFTR
Tape & Reel
■ AC-DC LED drivers up to 15 W
Description
The HVLED815PF is a high-voltage primary
switcher intended for operating directly from the
rectified mains with minimum external parts and
enabling high power factor (> 0.90) to provide an
efficient, compact and cost effective solution for
LED driving. It combines a high-performance low-
voltage PWM controller chip and an 800 V,
avalanche-rugged Power MOSFET, in the same
package. There is no need for the optocoupler
thanks to the patented primary sensing regulation
(PSR) technique. The device assures protection
against LED string fault (open or short).
January 2013
Doc ID 023409 Rev 4
1/36
This is information on a product in full production.
www.st.com
36
Contents
HVLED815PF
Contents
1
2
3
4
Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Secondary side demagnetization detection and triggering block . . . . . . . 18
Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage feed-forward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 25
Soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.10 Hiccup mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.11 High Power Factor implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.12 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/36
Doc ID 023409 Rev 4
HVLED815PF
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Application circuit for high power factor LED driver - single range input. . . . . . . . . . . . . . . . 4
Application circuit for standard LED driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OFF-state drain and source current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COSS output capacitance variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Startup current test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quiescent current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating supply current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Quiescent current during fault test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Multi-mode operation of HVLED815PF (constant voltage operation). . . . . . . . . . . . . . . . . 16
Figure 12. High-voltage start-up generator: internal schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18
Figure 14. DMG block, triggering block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Drain ringing cycle skipping as the load is progressively reduced . . . . . . . . . . . . . . . . . . . 19
Figure 16. Current control principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Constant current operation: switching cycle waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. Voltage control principle: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. Feed-forward compensation: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. High power factor implementation connection - single range input . . . . . . . . . . . . . . . . . . 28
Figure 23. Suggested routing for the led driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. SO16N mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 25. SO16N drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 26. SO16N recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 023409 Rev 4
3/36
1
Principle application circuit and block diagram
1.1
Principle application circuit
Figure 1.
Application circuit for high power factor LED driver - single range input
Vout
Lin
T1
O utpout Diode
1
2
10
9
VIN
J1
CON1
EMI FILTER
Bridge Diode
R12
3
4
8
Rf
C12
Cout Bulk
C13
Cout SMD
J2
F1 1A_DIP
Minimum Load
2
1
7
6
Lf
CON1
5
J3
CON1
Cf
Cf
TRANSFORMER
J4
Lf
CON1
Rf
C10
U1
VIN
D5
Rsense
Rsense
HVLED8xxPF
Y1 - SAFETY
1
2
SOURCE
16
15
14
13
RA
RB
DRAIN
CS
R1 (500 - 1.5k)
CS
DRAIN
DRAIN
DRAIN
220pF-1nF
3
4
5
6
7
8
VCC
C_Vcc (10uF MIN)
VCC
GND
ILED
DMG
COMP
N.A.
COS Filter (1uF)
CS
ROS
CS
C_ILED (10uF)
Rfb
RPF
D4
DMG
Cf (330nF-680nF)
DMG
Rdmg
Rf (8k-15k)
VCC
D2
1N4148
NA
R-VCC (10-100ohm)
Cp (1n-10nF)
C_VCC (470nF)
AM13207v1
Figure 2.
Application circuit for standard LED driver
Vout
T2
O utpout Diode1
1
2
10
9
VIN
J5
CON1
EMI FILTER
Bridge Diode
R18
3
4
8
Rf
C16
Cout Bulk
C27
Cout SMD
J7
F2 1A_DIP
Minimum Load
2
1
7
6
Lf
CON1
5
J6
CON1
Cf
Cf
TRANSFORMER
J8
Lf
CON1
Rf
C23
U2
Rsense
Rsense
HVLED8xxPF
Y1 - SAFETY
1
2
SOURCE
16
15
14
13
DRAIN
CS
DRAIN
DRAIN
DRAIN
3
4
5
VCC
DMG
C_Vcc (10uF)
VCC
GND
ILED
DMG
COMP
N.A.
C_ILED (10uF)
Rfb
6
7
8
DMG
VCC
Rdmg
Cf (330nF/680nF)
Rf (8.2k-15k)
D8
1N4148
NA
R-VCC (10ohm)
Cp (1nF/10nF)
C_VCC (470nF)
AM13208v1
1.2
Block diagram
Figure 3.
Block diagram
+ VIN
VCC
HV start-up &
Supply Logic
DRAIN
LED
Vref
PROTECTION &
FEEDFORWARD
LOGIC
DEMAG
LOGIC
DRIVING
LOGIC
RDMG
DMG
CONSTANT
CURRENT
REGULATION
3.3 V
RFB
VILED
VCS
Vref
1 V
OCP
Constant Voltage
Regulation
RA
CS
GND
COMP
ILED
CLED
SOURCE
R1
RCOMP
CCOMP
RSENSE
RPF
ROS
AM13209v1
HVLED815PF
Pin description and connection diagrams
2
Pin description and connection diagrams
Figure 4.
Pin connection (top view)
SOURCE 1
16
CS
VCC
15
DRAIN
N.C.
2
3
14
GND
ILED
DMG
COMP
N.A.
13
12
4
5
N.A.
11
6
10
N.A.
N.A.
7
9
8
AM13210v1
2.1
Pin description
Table 2.
N.
Pin description
Name
Function
1
SOURCE Source connection of the internal power section.
Current sense input.
Connect this pin to the SOURCE pin (through an R1 resistor) to sense the
current flowing in the MOSFET through an RSENSE resistor connected to GND.
The CS pin is also connected through dedicated ROS, RPF resistors to the input
and auxiliary voltage, in order to modulate the input current flowing in the
MOSFET according to the input voltage and therefore achieving a high power
factor. See dedicated section for more details.
2
CS
The resulting voltage is compared with the voltage on the ILED pin to determine
MOSFET turn-off. The pin is equipped with 250 ns blanking time after the gate-
drive output goes high for improved noise immunity. If a second comparison level
located at 1 V is exceeded, the IC is stopped and restarted after VCC has
dropped below 5 V.
Doc ID 023409 Rev 4
7/36
Pin description and connection diagrams
HVLED815PF
Table 2.
N.
Pin description (continued)
Name
Function
Supply voltage of the device.
A capacitor, connected between this pin and ground, is initially charged by the
internal high-voltage startup generator; when the device is running, the same
generator keeps it charged in case the voltage supplied by the auxiliary winding
is not sufficient. This feature is disabled in case a protection is tripped. A small
bypass capacitor (100 nF typ.) to GND may be useful to get a clean bias voltage
for the signal part of the IC.
3
VCC
Ground.
Current return for both the signal part of the IC and the gate drive. All of the
ground connections of the bias components should be tied to a trace going to this
pin and kept separate from any pulsed current return.
4
5
GND
ILED
Constant current (CC) regulation loop reference voltage.
An external capacitor CLED is connected between this pin and GND. An internal
circuit develops a voltage on this capacitor that is used as the reference for the
MOSFET’s peak drain current during CC regulation. The voltage is automatically
adjusted to keep the average output current constant.
Transformer demagnetization sensing for quasi-resonant operation and output
voltage monitor.
A negative-going edge triggers the MOSFET turn-on, to achieve quasi-resonant
operation (zero voltage switching).
The pin voltage is also sampled-and-held right at the end of transformer
demagnetization to get an accurate image of the output voltage to be fed to the
inverting input of the internal, transconductance-type, error amplifier, whose non-
inverting input is referenced to 2.5 V. The maximum IDMG sunk/sourced current
must not exceed 2 mA (AMR) in all the Vin range conditions.
6
7
DMG
No capacitor is allowed between the pin and the auxiliary transformer.
Output of the internal transconductance error amplifier. The compensation
network is placed between this pin and GND to achieve stability and good
dynamic performance of the voltage control loop.
COMP
8
N.a.
N.a.
Not available. These pins must be connected to GND.
Not available. These pins must be left not connected.
9-11
Not internally connected. Provision for clearance on the PCB to meet safety
requirements.
12
N.c.
Drain connection of the internal power section.
13 to
16
DRAIN
The internal high-voltage startup generator sinks current from this pin as well.
Pins connected to the internal metal frame to facilitate heat dissipation.
2.2
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Max. value
Unit
RthJP
RthJA
Thermal resistance, junction-to-pin
10
°C/W
°C/W
Thermal resistance, junction-to-ambient
110
8/36
Doc ID 023409 Rev 4
HVLED815PF
Table 3.
Pin description and connection diagrams
Thermal data (continued)
Parameter
Symbol
Max. value
Unit
PTOT
TSTG
TJ
Maximum power dissipation at TA = 50 °C
Storage temperature range
0.9
W
°C
°C
-55 to 150
-40 to 150
Junction temperature range
Doc ID 023409 Rev 4
9/36
Electrical specifications
HVLED815PF
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4.
Symbol
Absolute maximum ratings
Pin
Parameter
Value
Unit
VDS
ID
1, 13-16
1, 13-16
Drain-to-source (ground) voltage
Drain current (1)
-1 to 800
1
V
A
Single pulse avalanche energy
(Tj = 25 °C, ID = 0.7 A)
Eav
1, 13-16
50
mJ
VCC
IDMG
3
6
2
7
Supply voltage (Icc < 25 mA)
Zero current detector current
Current sense analog input
Analog input
Self limiting
2
V
mA
V
VCS
-0.3 to 3.6
-0.3 to 3.6
Vcomp
V
1. Limited by maximum temperature allowed.
3.2
Electrical characteristics
Table 5.
Symbol
Electrical characteristics(1) (2)
Parameter
Test condition
Min. Typ. Max. Unit
Power section
V(BR)DSS
Drain-source breakdown
OFF-state drain current
ID < 100 µA; Tj = 25 °C
800
V
VDS = 750 V; Tj = 125 °C
(3)See Figure 5
IDSS
RDS(on)
COSS
80
7.4
µA
Id = 250 mA; Tj = 25 °C
6
Drain-source ON-state
resistance
Ω
Id = 250 mA; Tj = 125 °C
14.8
(3)
Effective (energy-related)
output capacitance
(3) See Figure 6
High-voltage startup generator
VSTART
Min. drain start voltage
Icharge < 100 µA
40
4
50
60
7
V
mA
V
VDRAIN > VStart
VCC<VCCOn
;
;
5.5
VCC startup charge
current
Tj = 25 °C
ICHARGE
VDRAIN > VStart
+/- 10%
VCC<VCCOn
(4)
9.5
10.5
5
11.5
VCC restart voltage
(VCC falling)
VCC_RESTART
After protection tripping
10/36
Doc ID 023409 Rev 4
HVLED815PF
Electrical specifications
Min. Typ. Max. Unit
Table 5.
Symbol
Electrical characteristics(1) (2) (continued)
Parameter
Test condition
Supply voltage
VCC
Operating range
After turn-on
11.5
12
9
23
14
11
27
(4)
VCC_ON
Turn-on threshold
Turn-off threshold
Internal Zener voltage
13
10
25
V
V
V
(4)
VCC_OFF
VZ
Icc = 20 mA
23
Supply current
ICC_START-UP Startup current
See Figure 7
See Figure 8
200
1
300
1.4
µA
Iq
Quiescent current
mA
Operating supply current
at 50 kHz
ICC
See Figure 9
See Figure 10
1.4
1.7
mA
µA
Iq(fault)
Startup timer
TSTART
Fault quiescent current
250
350
Start timer period
105
420
140
500
175
700
µs
µs
Restart timer period
during burst mode
TRESTART
Demagnetization detector
IDmgb
VDMGH
VDMGL
VDMGA
VDMGT
Input bias current
VDMG = 0.1 to 3 V
IDMG = 1 mA
0.1
3.3
-60
110
60
1
µA
V
Upper clamp voltage
Lower clamp voltage
Arming voltage
3.0
-90
100
50
3.6
-30
120
70
IDMG = - 1 mA
mV
mV
mV
Positive-going edge
Negative-going edge
VCOMP ≥ 1.3 V
Triggering voltage
6
Trigger blanking time after
MOSFET turn-off
TBLANK
µs
VCOMP = 0.9 V
30
Line feedforward
Equivalent feedforward
RFF
IDMG = 1 mA
Tj = 25 °C
(3) Tj = -25 to 125 °C and
VCC = 12 V to 23 V
45
Ω
resistor
Transconductance error amplifier
2.45
2.4
2.51
2.57
2.6
VREF
Voltage reference
Transconductance
V
ΔICOMP
=
10 µA
gm
1.3
2.2
3.2
ms
VCOMP = 1.65 V
Gv
Voltage gain
(5) Open loop
73
dB
(5)
GB
Gain-bandwidth product
500
KHz
Doc ID 023409 Rev 4
11/36
Electrical specifications
HVLED815PF
Table 5.
Symbol
Electrical characteristics(1) (2) (continued)
Parameter Test condition
VDMG = 2.3 V,
Min. Typ. Max. Unit
Source current
70
100
750
µA
µA
VCOMP = 1.65 V
ICOMP
VDMG = 2.7 V,
VCOMP = 1.65 V
Sink current
400
VCOMPH
VCOMPL
VCOMPBM
Hys
Upper COMP voltage
Lower COMP voltage
Burst-mode threshold
Burst-mode hysteresis
VDMG = 2.3 V
VDMG = 2.7 V
2.7
0.7
1
V
V
V
65
mV
Current reference
VILEDx Maximum value
VCLED
VCOMP = VCOMPL
1.5
1.6
0.2
1.7
V
V
Current reference voltage
0.192
0.208
Current sense
tLEB
(5)
Leading-edge blanking
Delay-to-output (H-L)
Max. clamp value
330
90
ns
ns
V
TD
200
0.8
VCSx
(4) dVcs/dt = 200 mV/µs
0.7
0.75
1
(4)
VCSdis
Hiccup-mode OCP level
0.92
1.08
V
1.
V
=14 V (unless otherwise specified).
CC
2. Limits are production tested at Tj=Ta=25 °C, and are guaranteed by statistical characterization in the range
Tj -25 to +125 °C.
3. Not production tested, guaranteed statistical characterization only.
4. Parameters tracking each other (in the same section).
5. Guaranteed by design.
Figure 5.
OFF-state drain and source current test circuit
14V
Idss
A
VDD
DRAIN
2.5V
+
-
CURRENT
CONTROL
Vin
750V
DMG
ILED
COMP
GND
CS
SOURCE
AM13211v1
Note:
12/36
The measured IDSS is the sum between the current across the startup resistor and the
effective MOSFET’s OFF-state drain current.
Doc ID 023409 Rev 4
HVLED815PF
Figure 6.
Electrical specifications
COSS output capacitance variation
600
500
400
300
200
100
0
0
25
50
75
100
125
150
Vds [ V]
AM13212v1
Figure 7.
Startup current test circuit
Iccstart-up
11.8 V
A
VDD
DRAIN
2.5V
+
-
CURRENT
CONTROL
DMG
ILED
COMP
GND
CS
SOURCE
AM13213v1
Figure 8.
Quiescent current test circuit
Iq_meas
A
14V
VDD
DRAIN
2.5V
+
-
CURRENT
CONTROL
DMG
ILED
COMP
GND
CS
SOURCE
33k
3V
0.8V
10k
0.2V
AM13214v1
Doc ID 023409 Rev 4
13/36
Electrical specifications
Figure 9.
HVLED815PF
Operating supply current test circuit
Icc
1.5K 2W
A
15V
27k
VDD
DRAIN
220k
2.5V
+
CURRENT
CONTROL
150V
-
DMG
ILED
COMP
GND
CS
SOURCE
10k
10k
10
2.8V
5.6
-5V
50 kHz
AM13215v1
Note:
The circuit across the DMG pin is used for switch-on synchronization.
Figure 10. Quiescent current during fault test circuit
Iq(fault)
14V
A
VDD
DRAIN
2.5V
+
-
CURRENT
CONTROL
DMG
ILED
COMP
GND
CS
SOURCE
AM13216v1
14/36
Doc ID 023409 Rev 4
HVLED815PF
Device description
4
Device description
The HVLED815PF is a high-voltage primary switcher intended for operating directly from the
rectified mains with minimum external parts to provide high power factor (> 0.90) and an
efficient, compact and cost effective solution for LED driving. It combines a high-
performance low-voltage PWM controller chip and an 800 V, avalanche-rugged Power
MOSFET, in the same package.
The PWM is a current-mode controller IC specifically designed for ZVS (Zero Voltage
Switching) flyback LED drivers, with constant output current (CC) regulation using primary
sensing feedback (PSR). This eliminates the need for the optocoupler, the secondary
voltage reference, as well as the current sense on the secondary side, while still maintaining
a good LED current accuracy. Moreover, it guarantees a safe operation when short-circuit of
one or more LEDs occurs.
The device can also provide a constant output voltage regulation (CV): it allows the
application to be able to work safely when the LED string opens due to a failure.
In addition, the device offers the shorted secondary rectifier (i.e. LED string shorted due to a
failure) or transformer saturation detection.
Quasi-resonant operation is achieved by means of a transformer demagnetization sensing
input that triggers MOSFET turn-on. This input serves also as both output voltage monitor,
to perform CV regulation, and input voltage monitor, to achieve mains-independent CC
regulation (line voltage feedforward).
The maximum switching frequency is top-limited below 166 kHz, so that at medium-light
load a special function automatically lowers the operating frequency while still maintaining
the operation as close to ZVS as possible. At very light load, the device enters a controlled
burst-mode operation that, along with the built-in high-voltage startup circuit and the low
operating current of the device, helps minimize the residual input consumption.
Although an auxiliary winding is required in the transformer to correctly perform CV/CC
regulation, the chip is able to power itself directly from the rectified mains. This is useful
especially during CC regulation, where the flyback voltage generated by the winding drops.
4.1
Application information
The device is an off-line led driver with all-primary sensing, based on quasi-resonant flyback
topology, with high power factor capability. In particular, using different application schematic
the device is able to provide a compact, efficient and cost-effective led driver solution with
high power factor (PF>0.9 - see application schematic on Figure 1) or with standard power
factor (PF>0.5/0.6 - see application schematic on Figure 2), based on the specific
application requirements.
Referring to the application schematic on Figure 1, the IC modulates the input current in
according to the input voltage providing the high power factor capability (PF>0.9) keeping a
good line regulation. This application schematic is intended for a single range input voltage.
For wide range application a different reference schematic can be used; refer to the
dedicated application note for further details.
Moreover, the device is able to work in different modes depending on the LED's driver load
condition (see Figure 11):
Doc ID 023409 Rev 4
15/36
Device description
HVLED815PF
1. QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET's
turn-on to the transformer's demagnetization by detecting the resulting negative-going
edge of the voltage across any winding of the transformer. Then the system works
close to the boundary between discontinuous (DCM) and continuous conduction
(CCM) of the transformer. As a result, the switching frequency is different for different
line/load conditions (see the hyperbolic-like portion of the curves in Figure 11).
Minimum turn-on losses, low EMI emission and safe behavior in short circuit are the
main benefits of this kind of operation.
2. Valley-skipping mode at medium/ light load. Depending on voltage on COMP pin, the
device defines the maximum operating frequency of the converter. As the load is
reduced MOSFET's turn-on does not occur any more on the first valley but on the
second one, the third one and so on. In this way the switching frequency is no longer
increased (piecewise linear portion in Figure 11).
3. Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter enters a controlled on/off operation with constant peak current.
Decreasing the load result in frequency reduction, which can go down even to few
hundred hertz, thus minimizing all frequency-related losses and making it easier to
comply with energy saving regulations or recommendations. Being the peak current
very low, no issue of audible noise arises.
Figure 11. Multi-mode operation of HVLED815PF (constant voltage operation)
fosc
Input voltage
f
sw
Valley-skipping
mode
Burst-mode
Quasi-resonant mode
0
Pinmax
P
in
AM13561v1
4.2
Power section and gate driver
The power section guarantees safe avalanche operation within the specified energy rating
as well as high dv/dt capability. The Power MOSFET has a VDSS of 800 V min. and a typical
R
DS(on) of 6 Ω.
The internal gate driver of the power MOSFET is designed to supply a controlled gate
current during both turn-on and turn-off in order to minimize common mode EMI. Under
UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the
power MOSFET cannot be turned on accidentally.
16/36
Doc ID 023409 Rev 4
HVLED815PF
Device description
4.3
High voltage startup generator
Figure 12 shows the internal schematic of the high-voltage start-up generator (HV
generator). It includes an 800 V-rated N-channel MOSFET, whose gate is biased through
the series of a 12 MΩ resistor and a 14 V Zener diode, with a controlled, temperature
compensated current generator connected to its source.
The HV generator input is in common with the DRAIN pins, while its output is the supply pin
of the device (VCC pin). A mains "UVLO" circuit (separated from the UVLO of the device
that sense VCC) keeps the HV generator off if the drain voltage is below VSTART (50 V
typical value).
Figure 12. High-voltage start-up generator: internal schematic
DRAIN
14V
12M
Mains UVLO
Vcc_OK
HV_EN
IHV
VCC
CONTROL
Icharge
GND
AM13562v1
With reference to the timing diagram of Figure 13, when power is applied to the circuit and
the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently
biased to start operating, thus it will draw about 5.5 mA (typical) to the VCC capacitor.
Most of this current will charge the bypass capacitor connected between the VCC pin and
ground and make its voltage rise linearly. As soon as the VCC pin voltage reaches the
V
CC_ON turn on threshold (13 V typ) the chip starts operating, the internal power MOSFET is
enabled to switch and the HV generator is cut off by the Vcc_OK signal asserted high. The
IC is powered by the energy stored in the VCC capacitor.
The chip is able to power itself directly from the rectified mains: when the voltage on the
VCC pin falls below VCC_RESTART (10.5 V typ.), during each MOSFET's off-time the HV
current generator is turned on and charges the supply capacitor until it reaches the VCC_ON
threshold.
In this way, the self-supply circuit develops a voltage high enough to sustain the operation of
the device. This feature is useful especially during constant current (CC) regulation, when
the flyback voltage generated by the auxiliary winding alone may not be able to keep VCC
pin above VCC_RESTART
.
Doc ID 023409 Rev 4
17/36
Device description
HVLED815PF
Figure 13. Timing diagram: normal power-up and power-down sequences
VIN
V
Start
t
VCC
VccON
Vccrestart
t
t
DRAIN
ICHARGE
5.5mA
t
Normal operation
CV mode
Normal operation
CC mode
Power-off
Power-on
AM13563v1
4.4
Secondary side demagnetization detection and triggering
block
The demagnetization detection (DMG) and Triggering blocks switch on the power MOSFET
if a negative-going edge falling below 50 mV is applied to the DMG pin. To do so, the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is used to detect transformer demagnetization for QR operation, where the
signal for the DMG input is obtained from the transformer's auxiliary winding used also to
supply the IC.
Figure 14. DMG block, triggering block
Rdmg
DMG
DMG
CLAMP
BLANKING
TIME
STARTER
Rfb
Aux
-
TURN-ON
LOGIC
S
R
+
To Driv er
110mV
60mV
Q
From CC/CV Block
LEB
From OCP
AM13564v1
18/36
Doc ID 023409 Rev 4
HVLED815PF
Device description
The triggering block is blanked after MOSFET's turn-off to prevent any negative-going edge
that follows leakage inductance demagnetization from triggering the DMG circuit
erroneously. This TBLANK blanking time is dependent on the voltage on COMP pin: it is
T
V
BLANK=30 µs for VCOMP=0.9 V, and decreases almost linearly down to TBLANK=6 µs for
COMP=1.3 V.
The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the DMG block of Figure 14. The upper clamp is typically located at 3.3
V, while the lower clamp is located at -60 mV. The interface between the pin and the
auxiliary winding will be a resistor divider. Its resistance ratio as well as the individual
resistance values will be properly chosen (see Section 4.6, 4.7 and 4.11).
Please note that the maximum IDMG sunk/sourced current has to not exceed 2 mA (AMR)
in all the Vin range conditions. No capacitor is allowed between DMG pin and the auxiliary
transformer.
The switching frequency is top-limited below 166 kHz, as the converter's operating
frequency tends to increase excessively at light load and high input voltage.
A Starter block is also used to start-up the system, that is, to turn on the MOSFET during
converter power-up, when no or a too small signal is available on the DMG pin. The starter
frequency is 2 kHz if COMP pin is below burst mode threshold, i.e. 1 V, while it becomes 8
kHz if this voltage exceed this value.
After the first few cycles initiated by the starter, as the voltage developed across the auxiliary
winding becomes large enough to arm the DMG circuit, MOSFET's turn-on will start to be
locked to transformer demagnetization, hence setting up QR operation. The starter is
activated also when the IC is in Constant Current regulation and the output voltage is not
high enough to allow the DMG triggering.
If the demagnetization completes - hence a negative-going edge appears on the DMG pin -
after a time exceeding time TBLANK from the previous turn-on, the MOSFET will be turned
on again, with some delay to ensure minimum voltage at turn-on. If, instead, the negative-
going edge appears before TBLANK has elapsed, it will be ignored and only the first negative-
going edge after TBLANK will turn-on the MOSFET. In this way one or more drain ringing
cycles will be skipped ("valley-skipping mode", Figure 15) and the switching frequency will
be prevented from exceeding 1/TBLANK
.
Figure 15. Drain ringing cycle skipping as the load is progressively reduced
V
DS
V
DS
VDS
t
t
t
T
W
T
ON
TFW
T
OSC
T
OSC
TOSC
P
in = Pin'
Pin = Pin'' < Pin'
Pin = Pin''' < Pin''
(limit condition)
AM13565v1
Note:
That when the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching
cycles will be compensated by one or more shorter cycles and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
Doc ID 023409 Rev 4
19/36
Device description
HVLED815PF
4.5
Constant current operation
Figure 16 presents the principle used for controlling the average output current of the
flyback converter.
The voltage of the auxiliary winding is used by the demagnetization block to generate the
control signal for the internal MOSFET switch Q. A resistor R in series with it absorbs a
current equal to VILED/R, where VILED is the voltage developed across the capacitor CLED
capacitor.
The flip-flop's output is high as long as the transformer delivers current on secondary side.
This is shown in Figure 17.
Figure 16. Current control principle
.
Iref
-
To PWM Logic
VILED
CC
+
R
Q
From CS pin
S
R
Q
Rdmg
DMG
DEMAG
LOGIC
Icled
Rfb
Aux
ILED
CLED
AM13566v1
Figure 17. Constant current operation: switching cycle waveforms
IPRIM
t
ISEC
t
TONSEC
Q
t
ICLED
IREF
t
VILED/R
T
AM13567v1
20/36
Doc ID 023409 Rev 4
HVLED815PF
Device description
The capacitor CLED has to be chosen so that its voltage VILED can be considered as a
constant. Since it is charged and discharged by currents in the range of some ten µA
(IREF=20 µA typ.) at the switching frequency rate, a capacitance value in the range 4.7-10
nF is suited for switching frequencies in the ten kHz. When high power factor schematic is
implemented, a higher capacitor value should be used (i.e. 1 µF-10 µF).
The average output current IOUT can be expressed as:
Equation 1
Where ISEC is the secondary peak current, TONSEC is the conduction time of the secondary
side and T is the switching period.
Taking into account the transformer ratio N between primary and secondary side, ISEC can
also be expressed as a function of the primary peak current IPRIM
:
Equation 2
As in steady state the average current ICLED
:
Equation 3
Which can be solved for VILED
:
Equation 4
where VCLED=R* IREF and it is internally defined (0.2 V typical - see Table 5: Electrical
characteristics).
The VILED pin voltage is internally compared with the CS pin voltage (constant current
comparator):
Equation 5
Combining (1), (2) (4) and (5) the average output current results:
Doc ID 023409 Rev 4
21/36
Device description
Equation 6
HVLED815PF
This formula shows that the average output current IOUT does not depend anymore on the
input voltage VIN or the output voltage VOUT, neither on transformer inductance values. The
external parameters defining the output current are the transformer ratio n and the sense
resistor RSENSE
.
The previous formula (Equation 6) is valid for both standard and high power factor
implementation.
4.6
Constant voltage operation
The IC is specifically designed to work in primary regulation and the output voltage is
sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier
diode.
Figure 18 shows the internal schematic of the constant voltage mode and the external
connections.
Due to the parasitic wires resistance, the auxiliary voltage is representative of the output just
when the secondary current becomes zero. For this purpose, the signal on DMG pin is
sampled-and-held at the end of transformer's demagnetization to get an accurate image of
the output voltage and it is compared with the error amplifier internal reference voltage VREF
(2.51 V typ - see Table 5: Electrical characteristics).
During the MOSFET's OFF-time the leakage inductance resonates with the drain
capacitance and a damped oscillation is superimposed on the reflected voltage. The S/H
logic is able to discriminate such oscillations from the real transformer's demagnetization.
When the DMG logic detects the transformer's demagnetization, the sampling process
stops, the information is frozen and compared with the error amplifier internal reference.
The internal error amplifier is a transconductance type and delivers an output current
proportional to the voltage unbalance of the two outputs: the output generates the control
voltage that is compared with the voltage across the sense resistor, thus modulating the
cycle-by-cycle peak drain current.
The COMP pin is used for the frequency compensation: usually, an RC network, which
stabilizes the overall voltage control loop, is connected between this pin and ground.
As a result, the output voltage VOUT at zero-load (i.e. no led on the led driver output) can be
selected trough the RFB resistor in according to the following formula:
Equation 7
Where NAUX and NSEC are the auxiliary and secondary turn's number respectively.
The RDMG resistor value can be defined depending on the application parameters (see
"Section 4.7: Voltage feed-forward block).
22/36
Doc ID 023409 Rev 4
HVLED815PF
Figure 18. Voltage control principle: internal schematic
Device description
Rdmg
DMG
-
S/H
-
To PWM Logic
+
CV
+
2.5V
Rfb
Aux
DEMAG
LOGIC
From CS pin
COMP
R
C
AM13568v1
4.7
Voltage feed-forward block
The current control structure uses the VCLED voltage to define the output current, according
to equation 6 on Section 4.5. Actually, the constant current comparator will be affected by an
internal propagation delay TD, which will switch off the MOSFET with a peak current than
higher the foreseen value.
This current overshoot will be equal to:
Equation 8
The previous terms introduce a small error on the calculated average output current set-
point, depending on the input voltage.
The HVLED815PF implements a line feed-forward function, which solves the issue by
introducing an input voltage dependent offset on the current sense signal, in order to adjust
the cycle-by-cycle current limitation.
The internal schematic is shown in Figure 19.
Doc ID 023409 Rev 4
23/36
Device description
Figure 19. Feed-forward compensation: internal schematic
HVLED815PF
DRAIN
Rdmg
DMG
Feedforward
Logic
.
Rfb
-
CC
Block
Aux
PWM
LOGIC
IFF
CC
+
Rff
CS
SOURCE
Rsense
AM13569v1
During MOSFET's ON-time the current sourced from DMG pin is mirrored inside the "Feed-
forward Logic" block in order to provide a feed-forward current, IFF.
Such "feed-forward current" is proportional to the input voltage according to the formula:
Equation 9
Where m is the primary-to-auxiliary turns ratio.
According to the schematic, the voltage on the non-inverting comparator will be:
Equation 10
The offset introduced by feed-forward compensation will be:
Equation 11
As RFF>>RSENSE, the previous one can be simplified as:
Equation 12
This offset is proportional to VIN and it is used to compensate the current overshoot,
according to the following formula:
24/36
Doc ID 023409 Rev 4
HVLED815PF
Equation 13
Device description
Finally, the Rdmg resistor can be calculated as follows:
Equation 14
In this case the peak drain current does not depend on input voltage anymore, and as a
consequence the average output current IOUT do not depend from the VIN input voltage.
When high power factor is implemented (see Section 4.11), the feed-forward current has to
be minimized because the line regulation is assured by the external offset circuitry (see
Figure 1: Application circuit for high power factor LED driver - single range input).
The maximum value is limited by the minimum Idmg internal current needed to guarantee
the correct functionality of the internal circuitry:
Equation 15
4.8
Burst-mode operation at no load or very light load
When the voltage at the COMP pin falls 65 mV is below the internally fixed threshold
V
COMPBM, the IC is disabled with the MOSFET kept in OFF state and its consumption
reduced at a lower value to minimize VCC capacitor discharge.
In this condition the converter operates in burst-mode (one pulse train every TSTART=500
µs), with minimum energy transfer.
As a result of the energy delivery stop, the output voltage decreases: after 500 µs the
controller switches-on the MOSFET again and the sampled voltage on the DMG pin is
compared with the internal reference VREF. If the voltage on the EA output, as a result of the
comparison, exceeds the VCOMPL threshold, the device restarts switching, otherwise it
stays OFF for another 500 µs period.
In this way the converter will work in burst-mode with a nearly constant peak current defined
by the internal disable level. A load decrease will then cause a frequency reduction, which
can go down even to few hundred hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. This kind of operation, shown in
the timing diagrams of Figure 20 along with the others previously described, is noise-free
since the peak current is low.
Doc ID 023409 Rev 4
25/36
Device description
Figure 20. Load-dependent operating modes: timing diagrams
COMP
HVLED815PF
50 mV hysteresis (Hys)
V
COMPL
IDS
t
t
Normal-mode
Normal-mode
Burst-mode
AM13570v1
4.9
Soft-start and starter block
The soft start feature is automatically implemented by the constant current block, as the
primary peak current will be limited from the voltage on the CLED capacitor.
During start-up, as the output voltage is zero, the IC will start in constant current (CC) mode
with no high peak current operations. In this way the voltage on the output capacitor will
increase slowly and the soft-start feature will be ensured.
Actually the CLED value is not important to define the soft-start time, as its duration depends
on others circuit parameters, like transformer ratio, sense resistor, output capacitors and
load. The user will define the best appropriate value by experiments.
4.10
Hiccup mode OCP
The device is also protected against short-circuit of the secondary rectifier, short-circuit on
the secondary winding or a hard-saturated flyback transformer. An internal comparator
monitors continuously the voltage on CS pin and activates a protection circuitry if this
voltage exceeds an internally fixed threshold VCSdis (1 V typ. - see Table 5: Electrical
characteristics).
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped the protection circuit enters a "warning state". If in the
subsequent switching cycle the comparator is not tripped, a temporary disturbance is
assumed and the protection logic will be reset in its idle state; if the comparator will be
tripped again a real malfunction is assumed and the device will be stopped.
This condition is latched as long as the device is supplied. While it is disabled, however, no
energy is coming from the self-supply circuit; hence the voltage on the VCC capacitor will
decay and cross the UVLO threshold after some time, which clears the latch. The internal
start-up generator is still off, then the VCC voltage still needs to go below its restart voltage
before the VCC capacitor is charged again and the device restarted.
26/36
Doc ID 023409 Rev 4
HVLED815PF
Device description
Ultimately, this will result in a low-frequency intermittent operation (hiccup-mode operation),
with very low stress on the power circuit. This special condition is illustrated in the timing
diagram of Figure 21.
Figure 21. Hiccup-mode OCP: timing diagram
VCC
Secondary diode is shorted here
VccON
VccOFF
Vccrest
t
t
V
CS
1 V
Vcsdis
V
DS
Two switching cycles
t
AM13571v1
4.11
High Power Factor implementation
Referring to the principle application schematic on Figure 1, two contributions are added on
the CS pin in order to implement the high power factor capability (trough RPF resistor) and
keeping a good line-regulation (trough ROS resistor). The application schematic on Figure 1
is intended for a single range input voltage. For wide range application a different reference
schematic can be used; refer to the dedicated application note for further details.
Through the RPF resistor a contribution proportional to the input voltage is added on the CS
pin: as a consequence the input current is proportional to the input voltage during the line
period, implementing a high power factor correction. The contribution proportional to the
input voltage is generated using the auxiliary winding, as a consequence a diode in series to
the RPF resistor is needed.
Through the ROS resistor a positive contribution proportional to the average value of the
input voltage is added on the CS pin in order to keep a good line-regulation.
The voltage contribution proportional to the average value of the input voltage is generated
trough the low pass filter RA/RB resistor and COS capacitor. A diode in series to the RA/RB
resistor is suggested to avoid the discharge of COS capacitor in any condition.
The R1 resistor between CS and SOURCE pin is needed to add on the CS pin also the
contribution proportional the output current trough the RSENSE resistor.
Doc ID 023409 Rev 4
27/36
Device description
HVLED815PF
Figure 22. High power factor implementation connection - single range input
DRAIN
Rdmg
DMG
Feedforward
Logic1
.
Rfb
-
CC
Block1
Aux
PWM
LOGIC2
IFF
CC
+
Rff
CS
SOURCE
RPF
R1
ROS
Rsense
RA
RB
VIN (after bridge diode)
COS
AM13572v1
The components selection flow starts from Rdmg resistor: this resistor has to be selected in
order to minimize the internal feed-forward effect.
The maximum selectable value is limited is by the minimum internal current circuitry IDMG
needed to guarantee the correct functionality of the internal circuitry:
Equation 16
where NAUX and NPRIM are the auxiliary and primary turn's number respectively and
V
IN_MIN is the minimum rms input voltage of the application (i.e. 88 V for 110 Vac or 175 V
for 230 Vac range).
The RFB resistor defines the VOUT output voltage value in the open circuit condition (no-
load condition, i.e. no led on the output of led driver) and it can be selected using the
following relationship:
Equation 17
where NAUX and NSEC are the auxiliary and secondary turn's number respectively and VREF
is the internal reference voltage (VREF =2.51 V typ - see Table 5: Electrical characteristics).
The R1 resistor is typically selected in the range of 500 Ω -1.5 kΩ in order to minimize the
internal feed-forward effect and to minimize the power dissipation on the RA/RB resistor
offset circuitry.
The RA, RB, ROS resistors are selected to add a positive offset on CS pin in order to keep a
good line regulation over the input voltage range and cab be selected using the following
relationship:
28/36
Doc ID 023409 Rev 4
HVLED815PF
Equation 18
Device description
Where VOS_TYP is the desired voltage across COS capacitor applying the VIN_TYP typical
input voltage (i.e. VIN_TYP=220 V for 176/264 Vac input range); Fsw is the switching
frequency and can be estimated using the following formula, where fT and fR are the
transition and resonant frequency respectively:
Equation 19
Equation 20
Equation 21
π
where CD is the total equivalent capacitor afferent at the drain node.
Based on the desired voltage across COS capacitor and calculated ROS resistor, then the
sum of RA and RB can then calculated as a results of partitioning divider:
Equation 22
Using the previous ROS resistor value the RPF resistor can be estimated using the following
formula:
Equation 23
Finally the current sense resistor RSENSE can be estimated in order to select the
desiderated average output current value:
Doc ID 023409 Rev 4
29/36
Device description
Equation 24
HVLED815PF
where VCLED is internally defined (0.2 V typical - see Table 5: Electrical characteristics).
System design tips
Starting from the estimated value using the previous formulas, further fine-tuning on the real
led driver board could be necessary and it can be easily done considering that:
–
–
–
Decreasing/increasing the RPF resistor value, the power factor effect
increase/decrease
Decreasing/increasing the ROS resistor value, the line-regulation effect
increase/decrease
Decreasing/increasing the ROS resistor value, the RA+RB resistors value should
be increase/decrease to keep the desiderated voltage across the COS capacitor
(Equation 22).
–
Decreasing/increasing the RSENSE resistor value the average output current
increase/decrease (Equation 24).
4.12
Layout recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the HVLED815PF as well. Careful component placing, correct
traces routing, appropriate traces widths and compliance with isolation distances are the
major issues.
In particular:
●
●
●
●
●
Current sense resistor (RSENSE) should be connected as close as possible to the
SOURCE pin, maintaining the trace for the GND as short as possible.
Resistor connected on CS pin (ROS, RPF, R1) should be connected as close as possible
to the pin.
Compensation network (RCOMP, CCOMP) should be connected as close as possible to
the COMP pin, maintaining the trace for the GND as short as possible.
Signal ground should be routed separately from power ground, as well from the sense
resistor trace.
DMG partition resistors (RDMG, RFB) should be connected as close as possible to the
DMG pin, minimizing the equivalent parasitic capacitor on DMG pin.
30/36
Doc ID 023409 Rev 4
HVLED815PF
Figure 23. Suggested routing for the led driver
Device description
AC
AC
VCC
DRAIN
RDMG
DMG
ILED
GND
SOURCE
COMP
CS
RFB
RPF
ROS
R1
RCOMP
CCOMP
CLED
RSENSE
AM13573v1
Doc ID 023409 Rev 4
31/36
Package information
HVLED815PF
5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 24. SO16N mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.25
0.10
1.25
0.31
0.17
9.80
5.80
3.80
0.51
0.25
10.00
6.20
4.00
c
D
9.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0
0.50
1.27
8°
L
k
ccc
0.10
32/36
Doc ID 023409 Rev 4
HVLED815PF
Figure 25. SO16N drawing
Package information
0016020_F
Doc ID 023409 Rev 4
33/36
Package information
Figure 26. SO16N recommended footprint (dimensions are in mm)
HVLED815PF
34/36
Doc ID 023409 Rev 4
HVLED815PF
Revision history
6
Revision history
22-Oct
Table 6.
Document revision history
Revision
Date
Changes
26-Jul-2012
29-Aug-2012
1
2
Initial release.
Added Table 2: Pin description on page 7.
Modified TJ value on Table 3: Thermal data.
23-Oct-2012
31-Jan-2013
3
4
Updated TJ value in note 2 (below Table 5: Electrical characteristics).
Minor text changes.
Added sections from 4.1 to 4.12.
Modified Figure 1: Application circuit for high power factor LED driver
- single range input and Figure 2: Application circuit for standard LED
driver.
Doc ID 023409 Rev 4
35/36
HVLED815PF
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
36/36
Doc ID 023409 Rev 4
相关型号：
HVM10
HIGH VOLTAGE ASSEMBLIED RECTIFIER (VOLTAGE RANGE 5000 to 16000 Volts CURRENT 0.35 Amperes)
RECTRON
©2020 ICPDF网 联系我们和版权申明