IMG-524-P01 [STMICROELECTRONICS]
VGA Mobile Camera Module; VGA手机相机模块
| 型号： | IMG-524-P01 |
| 厂家： | 
ST |
| 描述： | VGA Mobile Camera Module |
| 文件： | 总3页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VS6524
VGA Mobile Camera Module
DATA BRIEF
FEATURES
■ 640H x 480V active pixels
■ 3.6 µm pixel size, 1/6 inch optical format
■ RGB Bayer color filter array
■ Integrated 10-bit ADC
■ Integrated digital image processing functions,
including defect correction, lens shading
correction, demosaicing, sharpening, gamma
correction and color space conversion
■ Embedded camera controller for automatic
exposure control, automatic white balance
control, black level compensation, 50/60 Hz
flicker detection and cancelling, flashgun
support
DESCRIPTION
The VS6524 is a VGA resolution CMOS color dig-
ital camera featuring low size and low power con-
sumption and targeting mobile applications. The
VS6524 is manufactured in 0.18 µm ST CMOS im-
aging process. It integrates a high-sensitivity pixel
array, a digital image processor and camera con-
trol functions.
■ Up to 30 fps progressive scan, subsampling and
cropping to QVGA, QQVGA and subQCIF
■ ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with
embedded syncs, RGB 565, RGB 444 or Bayer
10-bit output formats
■ 8-bit parallel video interface, horizontal and
The VS6524 is capable of streaming VGA video
up to 30 fps, with ITU-R BT.656-4 YUV 4:2:2 frame
format. It supports both 1.8 V and 2.8 V interface
and requires a 2.4 to 3.0 V analog power supply.
Typically, the VS6524 can operate as a 2.8 V sin-
gle supply camera or as a 1.8 V / 2.5 V supply
camera. The integrated PLL allows for low fre-
quency system clock, and flexibility for successful
EMC integration. This complete camera module is
ready to connect to camera enabled baseband
processors, back-end IC devices or PDA engines.
The VS6524 package uses the second generation
of SmOP2 packaging technology where the sen-
sor, passives and lens are assembled in a fully au-
tomated test and focus process, allowing high
volume and low cost production.
vertical syncs, 24 MHz clock
■ Two-wire serial control interface
■ On-chip PLL, 6.5 to 27 MHz clock input
■ Analog power supply, from 2.4 to 3.0 V
■ Separate I/O power supply, 1.8 or 2.8 V levels
■ Integrated power management with power
switch, automatic power-on reset and power-
safe pins
■ Low power consumption, ultra low standby
current
■ Dual-element plastic lens, F# 2.8, 50°
Horizontal field of view
■ 7 x 7 x 4.5 mm fixed focus camera module with
APPLICATIONS
■ Mobile phone
embedded passives
■ 20-wire FPC attachment with board-to-board
■ PDA
connector, 22 mm total length
■ Videophone
Rev. 2
1/3
February 2005
VS6524
Figure 1. Application Diagram
Table 1. Technical Specifications
8-bit parallel video, hsync,
vsync
ITU-R BT.656-4 compliant,
24 MHz max
CLK
CE
Video Interface
VS6524
VGA Mobile
Camera Module
Baseband
or
Application
Processor
SCL, SDA
6.5 to 27 MHz square
13 MHz typ. (on-chip PLL)
Clock input
D[7:0]
HSYNC
VSYNC
PCLK
FSO
Supply voltage
I/O voltage
2.4 to 3.0 V analog
1.8 or 2.8 V +/- 0.1 V
CMOS levels
Streaming 30 fps: 30 mA
max
Power down: 10 µA max.
Power consumption
Lens
Figure 2. Block diagram
2-element, 50° HFOV, F#
2.8
VS6524
PLL and Clock Management
CLK
CE
Depth of field
TV distortion
20 cm to infinite
< 1%
VDD
DGND
Power Mgmt
Power-On Reset
Camera
Controller
640 x 480
Pixel array
AVDD
AGND
Relative illumination
Package type
Package size
45% typ.
SCL
SDA
SmOP2
Video
7.0 x 7.0 x 4.5 mm (wlh)
D[7:0]
HSYNC, VSYNC
PCLK
Processor
Column ADC
X Decoder
FPC with 20-pin B2B
connector, Molex 55560-
FSO
Line SRAM
System attach
a
0201 or equivalent
a.
Contact us for custom FPC designs and/or ZIF connector
variants
Table 1. Technical Specifications
PART NUMBERING
Active pixels
640H x 480V
3.6 x 3.6µm
2.38 x 1.77 mm
RGB Bayer
Pixel size
Table 2. Order Codes
Part Number
Array size
Description
Color filter array
Exposure control
Analog gain
SmOP2 7.0 x 7.0 x 4.5 mm
FPC attach, tray packing
VS6524P02S
+120 dB
+24 dB (max)
61 dB (typical)
Dynamic range
Signal-to-noise Ratio
Frame rate
35 dB at 100 lux (typical)
1 to 30 Hz
VGA, QVGA, QQVGA,
subQCIF
Arbitrary cropping
Horizontal/vertical flipping
Image format
Pixel format
YUV 4:2:2
RGB 565, RGB 444
Raw Bayer 10-bit
2/3
VS6524
Figure 3. Outline Drawing
REVISION HISTORY
Table 3. Revision History
Date
Revision
Description of Changes
February 2005
February 2005
1
2
First Issue
Same content, format/layout reviewed.
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2004 STMicroelectronics - All rights reserved
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