L4981 [STMICROELECTRONICS]
POWER FACTOR CORRECTOR; 功率因数校正
| 型号： | L4981 |
| 厂家： | 
ST |
| 描述： | POWER FACTOR CORRECTOR |
| 文件： | 总17页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L4981A
L4981B
POWER FACTOR CORRECTOR
CONTROL BOOST PWM UP TO 0.99P.F.
LIMITLINE CURRENT DISTORTION TO < 5%
UNIVERSAL INPUT MAINS
MULTIPOWER BCD TECHNOLOGY
FEED FORWARD LINE AND LOAD REGULA-
TION
AVERAGE CURRENT MODE PWM FOR
MINIMUM NOISE SENSITIVITY
HIGH CURRENT BIPOLAR AND DMOS TO-
TEM POLE OUTPUT
LOW START-UP CURRENT (0.3mA TYP.)
UNDER VOLTAGE LOCKOUT WITH HYS-
TERESIS AND PROGRAMMABLE TURN ON
THRESHOLD
OVERVOLTAGE, OVERCURRENT PROTEC-
TION
DIP20
SO20
ORDERING NUMBERS: L4981X (DIP20)
L4981XD (SO20)
PRECISE 2% ON CHIP REFERENCE EX-
TERNALLY AVAILABLE
SOFT START
trol functions for designing a high efficiency-mode
power supply with sinusoidal line current con-
sumption.
The L4981 can be easily used in systems with
mains voltages between 85V to 265V without any
line switch. This new PFC offers the possibility to
work at fixed frequency (L4981A) or modulated
frequency (L4981B) optimizing the size of the in-
DESCRIPTION
The L4981 I.C. provides the necessary features
to achieve a very high power factor up to 0.99.
Realized in BCD 60II technology this power factor
corrector (PFC) pre-regulator contains all the con-
BLOCK DIAGRAM
1/17
September 1998
L4981A - L4981B
put filter; both the operating frequency modes
working with an average current mode PWM con-
troller, maintaining sinusoidal line current without
slope compensation.
Besides power MOSFET gate driver, precise volt-
age reference (externally available), error ampli-
fier, undervoltage lockout, current sense and the
soft start are included. To limit the number of the
external components, the device integrates pro-
tections as overvoltage and overcurrent. The
overcurrent level can be programmed using a
simple resistor for L4981A. For a better precision
and for L4981B an external divider must be used.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Pin
19
Parameter
Value
selflimit
2
Unit
V
Supply Voltage (ICC ≤50mA) (*)
IGDRV
20
Gate driv. output peak current (t = 1 s)
SINK
µ
Α
.
SOURCE
1.5
A
VGDRV
Gate driv. output voltage t = 0.1µs
Voltages at pins 3, 14, 7, 6, 12, 15
Error Amplifier Voltage
-1
V
-0.3 to 9
-0.3 to 8.5
5
V
VVA-OUT
IAC
13
4
V
AC Input Current
mA
V
Voltages at pin 8, 9
-0.5 to 7
-0.3 to 8.5
-0.3 to 3
-0.3 to 7
15
VCA-OUT
VROSC
5
Current Amplifier Volt. (Isource = -20mA; Isink = 20mA)
Voltage at pin 17
V
17
V
11, 18 Voltage at pin 11, 18
V
ICOSC
IFREQ-MOD
VSYNC
18
16
16
2
Input Sink Current
mA
mA
V
Frequency Modulation Sink Current (L4981B)
Sync. Voltage (L4981A)
5
-0.3 to 7
VIPK
Voltage at pin 2
Voltage at Pin 2 t = 1µs
-0.3 to 5.5
-2
V
V
Ptot
Power Dissipation at Tamb = 70°C
(DIP20)
(SO20)
1
W
W
Power Dissipation at Tamb = 70 C
0.6
°
Top
Operating Ambient Temperature
StorageTemperature
-40 to 125
-55 to 150
°C
°C
Tstg
(*) Maximum package power dissipation limits must be observed.
PIN CONNECTIONS (Top views)
L4981A
L4981B
2/17
L4981A - L4981B
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-ambient
DIP 20
SO 20
Unit
C/W
Rth j-amb
80
120
°
PIN FUNCTIONS
N.
1
Name
P-GND
IPK
Description
Power ground.
2
L4981A peak current limiting. A current limitation is obtained using a single resistor connected
between Pin 2 and the sense resistor. To have a better precision another resistor between Pin
2 and a reference voltage (Pin 11) must be added.
L4981B
peak current limiting. A precise current limitation is obtained using two external
resistor only. These resistors must be connected between the sense resistor, Pin 2 and the
reference voltage.
3
4
OVP
IAC
Overvoltage protection. At this input are compared an internal precise 5.1V (typ) voltage
reference with a sample of the boost output voltage obtained via a resistive voltage divider in
order to limit the maximum output peak voltage.
Input for the AC current. An input current proportional to the rectified mains voltage generates,
via a multiplier, the current reference for the current amplifier.
5
6
CA-OUT
LFF
Current amplifier output. An external RC network determinates the loop gain.
Load feedforward; this voltage input pin allows to modify the multiplier output current
proportionally to the load, in order to give a faster response versus load transient. The best
control is obtained working between 1.5V and 5.3V. If this function is not used, connect this pin
to the voltage reference (pin = 11).
7
VRMS
Input for proportional RMS line voltage. the VRMS input compesates the line voltage changes.
Connecting a low pass filter between the rectified line and the pin 7, a DC voltage proportional
to the input line RMS voltage is obtained. The best control is reached using input voltage
between 1.5V and 5.5V. If this function is not used connect this pin to the voltage reference
(pin = 11).
8
MULT-OUT Multiplier output. This pin common to the multiplier output and the current amplifier N.I. input is
an high impedence input like ISENSE. The MULT-OUT pin must be taken not below -0.5V.
9
ISENSE
S-GND
VREF
Current amplifier inverting input. Care must be taken to avoid this pin goes down -0.5V.
Signal ground.
10
11
Output reference voltage (typ = 5.1V).Voltage refence at ± 2% of accuracy externally available,
it’s internally current limited and can deliver an output current up to 10mA.
12
SS
A capacitor connected to ground defines the soft start time. An internal current generator
delivering 100µA (typ) charges the external capacitor defining the soft start time constant. An
internal MOS discharge, the external soft start capacitor both in overvoltage and UVLO
conditions.
13
14
VA-OUT
VFEED
Error amplifier output, an RC network fixes the voltage loop gain characteristics.
Voltage error amplifier inverting input. This feedback input is connected via a voltage divider to
the boost output voltage.
15
16
P-UVLO
Programmable under voltage lock out threshold input. A voltage divider between supply
voltage and GND can be connected in order to program the turn on threshold.
SYNC
(L4981A)
This synchronization input/output pin is CMOS logic compatible. Operating as SYNC in, a
rectangular wave must be applied at this pin. Opearting as SYNC out, a rectangular clock
pulse train is available to synchronize other devices.
FREQ-MOD Frequency modulation current input. An external resistor must be connected between pin 16
(L4981B)
and the rectified line voltage in order to modulate the oscillator frequency. Connecting pin 16 to
ground a fixed frequency imposed by ROSC and COSC is obtained.
17
18
19
20
ROSC
COSC
VCC
An external resistor connected to ground fixes the constant charging current of COSC
An external capacitor connected to GND fixes the switching frequency.
Supply input voltage.
.
GDRV
Output gate driver. Bipolar and DMOS transistors totem pole output stage can deliver peak
current in excess 1A useful to drive MOSFET or IGBT power stages.
3/17
L4981A - L4981B
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified VCC = 18V, COSC = 1nF,
R
OSC = 24KΩ, CSS = 1µF, VCA-OUT = 3.5V, VISENSE = 0V, VLFF = VREF, IAC = 100µA, VRMS = 1V,
V
FEED = GND, VIPK = 1V, VOVP = 1V, TJ = 25°C
Symbol
Prameter
Test Condition
Min.
Typ.
Max.
Unit
ERROR AMPLIFIER SECTION
VIO
IIB
Input Offset Voltage
Input Bias Current
Open Loop Gain
–25°C < TJ < 85°C
±8
mV
nA
dB
V
VFEED = 0V
-500
70
-50
100
6.5
500
V13H
V13L
Output High voltage
VFEED = 4.7V
5.5
7.5
1
I
VA-OUT = -0.5mA
VFEED = 5.5V
VA-OUT = 0.5mA
Output Low Voltage
0.4
V
I
-I13
I13
Output Source Current
Output Sink Current
VFEED = 4.7V; VVA-OUT = 3.5V
VFEED = 5.5V; VVA-OUT = 3.5V
2
4
10
20
mA
mA
REFERENCE SECTION
Vref
Reference Output Voltage
–25 C < T < 85 C
4.97
5.01
5.1
5.1
3
5.23
5.19
15
V
V
°
°
J
Tj = 25°C Iref = 0
∆Vref
∆Vref
Iref sc
Load Regulation
Line Regulation
1mA ≤ Iref ≤ 10mA
–25°C < TJ < 85°C
mV
12V ≤ VCC ≤ 19V
3
10
50
mV
mA
–25 C < T < 85 C
°
°
J
Short Circuit Current
Vref = 0V
20
30
OSCILLATOR SECTION
fosc
Initial Accuracy
Tj = 25°C
85
80
100
100
115
120
KHz
KHz
Frequency Stability
12V ≤ VCC ≤ 19V
–25°C < TJ < 85°C
Vsvp
I18C
I18D
V18
Ramp Valley to Peak
Charge Current
4.7
5
5.3
V
mA
mA
V
VCOSC = 3.5V
VCOSC = 3.5V
0.45
0.55
11.5
1.15
0.65
Discharge Current
Ramp Valley Voltage
0.9
1.4
SYNC SECTION (Only for L4981A)
tW
Output Pulse Width
50% Amplitude
VSYNC = 0.4V
0.3
0.4
0.8
0.8
µs
I16
Sink Current with Low Output
Voltage
mA
V
COSC = 0V
-I16
Source Current with High Output
Voltage
VSYNC = 4.5V
1
6
mA
V
COSC = 6.7V
V16L
V16H
td
Low Input Voltage
0.9
V
V
High Input Voltage
3.5
Pulse for Synchronization
800
ns
FREQUENCY MODULATION FUNCTION
L4981B
)
(Only for
f18max
f18min
Maximum Oscillation Frequency
Minimum Oscillator Frequency
VFREQ-MOD = 0V (Pin 16) Ifreq = 0
85
100
74
115
KHz
KHz
IFREQ-MOD = 360µA (Pin 16)
V
VRMS = 4V (Pin 7)
IFREQ-MOD = 180µA (Pin 16)
VRMS = 2V (Pin 7)
76
KHz
V
SOFT START SECTION
ISS
Soft Start Source Current
Output Saturation Voltage
VSS = 3V
60
100
0.1
140
µA
V12sat
V3 = 6V, ISS = 2mA
0.25
V
4/17
L4981A - L4981B
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE
VCC
Operating Supply Voltage
19.5
V
OVER VOLTAGE PROTECTION COMPARATOR
Vthr
Rising Threshold Voltage
Vref
5.1
Vref
V
-20mV
+20mV
V3Hys
I3
Hysteresis
180
250
0.05
1
320
1
mV
Input Bias Current
Propagation delay to output
A
µ
td
VOVP = Vthr +100mV
2
s
µ
OVER CURRENT PROTECTION COMPARATOR
Vth
td
Threshold Voltage
±30
0.9
105
5
mV
µs
Propagation delay to Output
Current Source Generator
Leakage Current
VOCP = Vthr -0.2V
0.4
85
only for L4981A
only for L4981B
Iipk
IL
VIPK = -0.1V
VIPK = -0.1V
65
µA
µA
CURRENT AMPLIFIER SECTION
Voffset
I9bias
Input Offset Voltage
Input Bias Current
Open Loop Gain
VMULT OUT = VSENSE = 3.5V
VSENSE = 0V
±2
mV
nA
dB
dB
-500
70
50
100
90
500
1.1V VCA OUT 6V
≤
≤
SVR
V5H
V5L
Supply Voltage Rejection
12V ≤ VCC ≤ 19V
MULT OUT = 3.5V VSENSE = 3.5V
68
V
Output High Voltage
Output Low Voltage
VMULT OUT = 200mV
CA OUT = -0.5mA, VIAC = 0V
6.2
V
V
I
VMULT OUT = -200mV
CA OUT = 0.5mA, VIAC = 0V
VMULT OUT = 200mV,
IAC = 0V, VCA-OUT = 3.5V
0.9
0.8
I
-I5
I5
Output Source Current
Output Sink Current
2
2
10
10
mA
mA
V
OUTPUT SECTION
V20L
V20H
Output Voltage Low
ISINK = 250mA
0.5
V
V
Output Voltage High
ISOURCE = 250mA
11.5
13
12.5
V
CC = 15V
tr
tf
Output Voltage Rise Time
Output Voltage Fall Time
Voltage Clamp
COUT = 1nF
COUT = 1nF
ISOURCE = 0mA
50
30
16
150
100
19
ns
ns
V
VGDRV
TOTAL STANDBY CURRENT SECTION
I19start
I19on
Supply Current before start up
Supply Current after turn on
VCC = 14V
0.3
8
0.5
12
mA
mA
VIAC = 0V, VCOSC = 0,
Pin17 = Open
I19
Operating Supply Current
Zener Voltage
Pin20 = 1nF
(*)
12
25
16
30
mA
V
VCC
20
UNDER VOLTAGE LOCKOUT SECTION
Vth ON
Turn on Threshold
Turn off Threshold
14.5
9
15.5
10
16.5
11
V
V
V
Vth OFF
Programmable Turn-on Threshold Pin 15 to VCC = 220K
Pin15 to GND = 33K
10.6
12
13.4
LOAD FEED FORWARD
ILFF
Bias Current
V6 = 1.6V
V6 = 5.3V
70
140
300
5.3
A
µ
200
µA
VI
Input Voltage Range
1.6
V
(*) Maximum package power dissipation limits must be observed.
5/17
L4981A - L4981B
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Prameter
Test Condition
Min.
Typ.
Max.
Unit
MULTIPLIER SECTION
Multipler Output Current
VVA-OUT = 4V, VRMS = 2V,
VMULTOUT = 0, VLFF = 5.1V
20
35
52
A
µ
IAC = 50µA, COSC = 0V
VVA-OUT = 4V, VRMS = 2V,
VMULTOUT = 0, VLFF = 5.1V
IAC = 200µA, COSC = 0V
100
10
2
135
20
170
30
11
34
54
54
2
µA
µA
VVA-OUT = 2V, VRMS = 2V,
VMULTOUT = 0, VLFF = 5.1V
IAC = 100 A, COSC = 0V
µ
VVA-OUT = 2V, VRMS = 4V,
VMULTOUT = 0, VLFF = 5.1V
5.5
22
A
µ
IAC = 100µA, COSC = 0V
VVA-OUT = 4V, VRMS = 4V,
VMULTOUT = 0, VLFF = 5.1V
IAC = 100µA, COSC = 0V
10
20
20
-2
µA
µA
VVA-OUT = 4V, VRMS = 2V,
VMULTOUT = 0, VLFF = 2.5V
37
COSC = 0V, I = 200 A
µ
AC
VVA-OUT = 4V, VRMS = 4V
VMULTOUT = 0, VLFF = 5.1V
39
A
µ
IAC = 200µA, COSC = 0V
VVA-OUT = 2V, VRMS = 4V,
VMULTOUT = 0, VLFF = 5.1V
IAC = 0, COSC = 0V
0
µA
K
Multiplier Gain
0.37
(
−
) (
−
)
VVA−OUT 1.28 0.8 VLFF 1.28
I
MULT−OUT = K IAC
2
(VVRMS
)
(V
VA
− 1.28)
−OUT
if VLFF = VREF;
I
= I
K1
MULT−OUT
AC
2
(V
)
VRMS
where: K1 = 1V
Figure 2: MULTI-OUT vs. IAC (VRMS = 2.2V;
Figure 1:
MULTI-OUTvs. IAC (VRMS = 1.7V;
VLFFD = 5.1V)
VLFFD = 5.1V)
6/17
L4981A - L4981B
Figure 3:
MULTI-OUTvs. IAC (VRMS = 4.4V;
VLFFD = 5.1V)
Figure 4: MULTI-OUT vs. IAC (VRMS = 5.3V;
VLFFD = 5.1V)
Figure 5: MULTI-OUTvs. IAC (VRMS = 1.7V;
Figure 6:
MULTI-OUT vs. IAC (VRMS = 2.2V;
VLFFD = 2.5V)
VLFFD = 2.5V)
Figure 7: MULTI-OUTvs. IAC (VRMS = 4.4V;
Figure 8:
MULTI-OUT vs. IAC (VRMS = 5.3V;
VLFFD = 2.5V)
VLFFD = 2.5V)
7/17
L4981A - L4981B
Figure 9A:
L4981A Power Factor Corrector (200W)
T
+
Vo=400V
D1
R6
C7
C12
D4
R14
R15
R1
R9
R7
C8
R8
D3
C5
C9
FUSE
Vi
BRIDGE
R12
7
4
1
19
13
14
85V -265V
AC
AC
3
C2
C11
D2
15
16
C1
L4981A
R13
20
MOS
6
2
8
5
9
18
10
17
12
11
D5
R17
R2
R10
R21
C3
R5
R11
R3
R4
C4
R16
C6
C10
R
S
-
D93IN029B
PART LIST
RS
R1
0.07(3 x .22)
820kΩ
10kΩ
1/2W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/2W
1/4W
4W
5%
1%
1%
5%
5%
5%
5%
5%
5%
1%
1%
1%
5%
5%
1%
5%
5%
1%
1%
C1
470nF
100µF
2.2nF
1nF
400V
C2
C3
450V
R2
R3
1.8kΩ
C4
R4
1.8kΩ
C5
100µF
1µF
25V
16V
63V
63V
R5
18kΩ
C6
R6
1.2MΩ
C7
220nF
220nF
330nF
R7
360k
Ω
C8
R8
33k
Ω
C9
R9
1.8M
21k
Ω
C10
C11
C12
D1
1 F
µ
16V
400V
100V
R10
R11
R12
R13
R14
R15
R16
R17
R21
Ω
270pF
8.2nF
402Ω
120kΩ
27Ω
STTA506D
1N4148
18V
D2, D3
D4
1MΩ
1/2W
120kΩ
30kΩ
D5
BYT11-600
MOS
STH/STW15NA50
FUSE = 4A/250V
1.8k
5.1k
Ω
Ω
1/4W
BRIDGE = 4 x P600M
T= primary: 88 turns of 12 x 32 AWG (0.2mm)
secondary:9 turns of # 27AWG (0.15mm)
core:B1ET3411A THOMSON - CSF
fSW = 80kHz PO = 200W
OUT = 400V Irms max = 2.53A
VOVP = 442V IPK max = 6.2A
V
gap: 1,6mm for a total primary inductance of
0.9mH
8/17
L4981A - L4981B
Figure 9B:
L4981B Power Factor Corrector (200W)
T
+
Vo=400V
D1
R22
R6
R7
C7
C8
C12
R15
D4
C5
R14
R1
R9
D3
C9
FUSE
Vi
BRIDGE
R8
R12
7
4
1
19
13
14
85V -265V
AC
AC
3
C2
C11
D2
15
16
C1
L4981B
R13
20
MOS
6
2
8
5
9
18
10
17
12
11
D5
R17
R2
R10
R21
C3
R5
R11
R3
R4
C4
R16
C6
C10
R
S
-
D95IN220
PART LIST
RS
R1
0.07(3 x .22)
820kΩ
1/2W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/2W
1/4W
4W
5%
1%
1%
5%
5%
5%
5%
5%
5%
1%
1%
1%
5%
5%
1%
5%
5%
1%
1%
1%
C1
470nF
100µF
2.2nF
1.1nF
100µF
1µF
400V
450V
C2
C3
R2
10kΩ
R3
1.8kΩ
C4
R4
1.8kΩ
C5
25V
16V
63V
63V
R5
18k
Ω
C6
R6
1.2M
Ω
C7
220nF
220nF
330nF
R7
360kΩ
33kΩ
C8
R8
C9
R9
1.8MΩ
C10
C11
C12
D1
1 F
µ
16V
400V
100V
R10
R11
R12
R13
R14
R15
R16
R17
R21
R22
21k
402
Ω
Ω
270pF
8.2nF
120kΩ
27Ω
STTA506D
1N4148
18V
D2, D3
D4
1MΩ
1/2W
120kΩ
D5
BYT11-600
24k
Ω
MOS
STH/STW15NA50
FUSE = 4A/250V
1.8k
Ω
5.1kΩ
1/4W
1/4W
1.1MΩ
BRIDGE = 4 x P600M
T= primary: 88 turns of 12 x 32 AWG (0.2mm)
secondary:9 turns of # 27AWG (0.15mm)
core:B1ET3411A THOMSON - CSF
fSW = 80 to 92kHz PO = 200W
OUT = 400V Irms max = 2.53A
VOVP = 442V IPK max = 6.2A
V
gap: 1,6mm for a total primary inductance of
0.9mH
9/17
L4981A - L4981B
Figure 10: Reference Voltage vs. Source Refer-
Figure 11: ReferenceVoltage vs. Supply Voltage
ence Current
Figure 12: ReferenceVoltage vs. Junction Tem-
Figure 13: Switching Frequency vs. Junction
perature
Temperature
Figure 15: OperatingSupply Current vs. Supply
Figure 14: Gate Driver Rise and Fall Time
Voltage
10/17
L4981A - L4981B
Figure 16:
Programmable Under Voltage Lock-
out Thresholds
Figure 17:
ModulationFrequency Normalized in
an Half Cycle of the Mains Voltage
fsw
1
Vl
1
0.8
0.4
0.8
0.4
R22 = R23 6.8
0.2
0
0.2
0
0
45
90
135
180
R23 (Kohm)
Electrical degrees
Table 1: Programmable Under Voltage Lockout Thresholds.
VCC ON
11V
VCC OFF
10V
R22
R23
82kΩ
12kΩ
12V
10.1V
10.5V
10.8V
10.9V
11V
220k
33k
Ω
Ω
13V
430kΩ
909k
62kΩ
133k
14V
Ω
Ω
14.5V
15V
1.36MΩ
2.7M
200kΩ
390k
Ω
Ω
Figure 18: Oscillator Diagram
11/17
L4981A - L4981B
Figure 19:
200W Evaluation Board Circuit.
T= primary: 75 turns of litz wire 20 x 32 AWG (0.2mm)
secondary: 8 turns of # 27AWG (0.15mm)
core: B1ET3411A THOMSON - CSF
gap: 1.4mm for a total primary inductance of 0.7mH
f
sw = 100kHz; VO = 400V; PO = 200W
NOTE:
Start Up Circuit
voltage available at pin 6 by R20 and Q3, ensures Q2 to be turned
off.
Usually the VCC capacitor (C11 in fig. 19)can becharged bya resistor
drawing current from the rectified mains. In the evaluation board
instead the start up circuit composed by (Q2+R19+R15+Dz) has
been designed to perform a fast and effective supply in all the
conditions. Once that the L4981A/B has started, the reference
Programmable Under voltage Lockout
The PCB allows to insert a couple of resistor (R22, R23) to modify
the threshold input voltage. Please refer to fig. 16 and table1.
12/17
L4981A - L4981B
Figure 20:
P.C. Board and Component Layout of EvaluationBoard Circuit (1:1 scale).
13/17
L4981A - L4981B
a NTC resistor can be used.
The PFC demoboard performances has been
evaluated testing the following parameters:
The evaluation board has been designed using: a
faster not dissipative start-up circuit, a diode (D2)
to speed-up the MOS start-off time and (even if a
single resistor can be used) an external divider to
improve the precision of the overcurrent thresh-
old.
Further there is a possibility to change the input
threshold voltage using an external divider (R23
and R22) and if an inrush current problem arises
PF (power factor), A-THD (percentage of current
total harmonic distortion), H3..H9 (percentage of
current’s nth harmonic amplitude), Vo (output
∆
η
voltage ripple), Vo (output voltage), (efficiency).
The test configuration, equipments and results
are:
AC POWER
SOURCE
LARCET /3KW
PM1200
AC POWER
ANALYSER
PFC
L4981
DEMO
EMI
FILTER
LOAD
D94IN057
Vi
(Vrms
88
f
(Hz)
60
60
60
50
50
50
Pi
PF
A-THD
(%)
H3
H5
H7
H9
VO
∆VO
(V)
8
PO
(W)
200
201
202
203
204
205
η
)
(W)
222
220
218
217
217
216
(%)
(%)
(%)
(%)
(V)
390
392
394
396
398
400
(%)
0.999
0.999
0.999
0.999
0.997
0.995
2.94
1.79
1.71
1.88
2.25
3.30
1.98
1.40
1.16
1.52
1.68
1.84
0.61
0.40
0.40
0.65
0.83
1.30
0.55
0.31
0.35
0.40
0.57
0.39
0.70
0.28
0.31
0.34
0.48
0.73
90.2
91.6
92.8
93.8
94.2
95.2
110
132
180
220
260
8
8
8
8
8
EMI/RFI FILTER
The harmonic content measurement has been
done using an EMI/RFI filter interposed between
the AC source and the demoboard under test,
while the efficiency has been calculated without
the filter contribution.
T1
T2
LINE
C1
PFC
C
EARTH
D94IN052
where:
T1 = 1mH
T2 = 27mH
C1 = 0.33µF, 630V
C2 = 2.2nF, 630V
14/17
L4981A - L4981B
SO20 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
2.35
0.1
TYP.
MAX.
2.65
0.3
MIN.
0.093
0.004
0.013
0.009
0.496
0.291
MAX.
0.104
0.012
0.020
0.013
0.512
0.299
A
A1
B
C
D
E
e
0.33
0.23
12.6
7.4
0.51
0.32
13
7.6
1.27
0.050
H
h
10
0.25
0.4
10.65
0.75
1.27
0.394
0.010
0.016
0.419
0.030
0.050
L
K
0 (min.)8 (max.)
L
h x 45°
A
A1
H
B
C
e
K
D
20
1
11
10
E
SO20MEC
15/17
L4981A - L4981B
DIP20 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.254
1.39
TYP.
MAX.
MIN.
0.010
0.055
MAX.
a1
B
b
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
0.335
0.100
0.900
2.54
22.86
e3
F
7.1
0.280
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
16/17
L4981A - L4981B
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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17/17
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