L5996 [STMICROELECTRONICS]
5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU; 5位动态DAC控制器的移动CPU
| 型号： | L5996 |
| 厂家： | 
ST |
| 描述： | 5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU |
| 文件： | 总9页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L5996
5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU
PRELIMINARY DATA
DYNAMIC DAC DETECTION ON CHIP
PROGRAMMABLE OUTPUT FROM 0.925V
TO 2.0V WITH 0.05V AND 0.025V BINARY
STEPS
ULTRA HIGH EFFICIENCY
SEPARATE 5V BIAS SUPPLY AVAILABLE
FOR HIGH EFFICIENCY PERFORMANCE
EXCELLENT OUTPUT ACCURACY ±1%
OVER LINE, LOAD AND TEMPERATURE
VARIATIONS
HIGH PRECISION INTERNAL REFERENCE
DIGITALLY TRIMMED
TQFP32
(7mm x 7mm)
OPERATING SUPPLY
4.75V TO 25V
VERYFAST LOAD TRANSIENT
REMOTE SENSING INPUTS
INTERNAL LINEAR REGULATOR 2.5V
/150mA, ±2% PRECISION
VOLTAGE FROM
Application
ADVANCED MICROPROCESSOR SUPPLIES
POWERSUPPLYFOR PENTIUM III INTEL MO-
BILE
DESCRIPTION
POWER MANAGEMENT
- PROGRAMMABLE POWER-UP TIME
- POWER GOOD OUTPUT, SKIP MODE
- OUTPUT OVERVOLTAGEPROTECTION
- OUTPUT UNDERVOLTAGE LOCKOUT
OPERATING FREQUENCY UP TO 1MHz
The L5996 is a power supply controller that offers
a complete power management for notebook
CPUs of the next generation especially for mobile
Pentium III. A high precise 5 bit digital to analog
converter (DAC) allows to adjust the output volt-
age from 0.925V to 2.0V. Dynamic DAC code
changes are detected on chip in order to switch
the output voltage between 1.3V and 1.45V in
less tahn 100µs.The high precision internal refer-
MEETS INTELMOBILE PENTIU III
TYPICAL APPLICATION CIRCUIT
L5996
POWER
SECTION
4.75V
to
25V
PWM SECTIONS
VO
CPU CORE
0.925V to 2.0V
D0
D1
D2
Pentium III
FREQ SETTING
SYNC
DAC
D3
Mobile
D4
POWER GOOD
ENABLE
POWER
MANAGEMENT
NOSKIP
3.3V
&
SYSTEM
SUPERVISOR
CPU CLK
2.5V
2.5V LIN. REG.
D98IN997A
July 1999
1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L5996
DESCRIPTION
(Continued)
PIN CONNECTION
ence, digitally trimmed, assures the selected out-
put voltage to within +/-1% over temperature and
battery voltage variations.
Thanks to the remote sensing inputs and to the
window comparator system, embedded in the er-
ror summing structure, the device provides excel-
lent load transient performance. The high peak
current gate drive affords to have fast switching
to the external power mos, performing an high ef-
ficiency. A complete power management include
on board a programmable power-up sequencing,
power good signal, skip mode operation and un-
dervoltege detection. The L5996 assures a fast
protection against load overvoltage and load
overcurrent. Linear regulator on-board is avail-
able with an output voltage of 2.5V (+/-2%) and a
current capability of 150mA, useful for CPU
CLOCK BUS.
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
ENABLE
VIN
24
23
22
21
20
19
18
17
VID4
VID3
REG5
VID2
V5SW
VID1
DISPROT
SSTART
HRSNS
LRSNS
VID0
ICURLIM
OSC
FREQ
9
10 11 12 13 14 15 16
D98IN998
BLOCK DIAGRAM
CSOFT
VIN3.3V
VID0 VID1 VID2 VID3 VID4
20 21 22 23 24
SSTART
6
VIN2.5
13
WINDOW
COMP
PROGRAMMABLE
BANDGAP
REFERENCE
VFB
9
14
15
VO2.5
VBG
+
-
VCPUCLK
&
SLOPE
2.5V
LIN.
LRSNS
HRSNS
8
REG.
-
+
+
-
ERROR
SUMMING
7
SOFT
START
10
COMP
REG5
Cboot
RSTRAP
HSTRAP
29
28
VPROG
11
3
VPROG
REG5
HRSNS
LRSNS
VIN
OVER CURRENT
COMPARATOR
INTERNAL SUPPLY
HGATE
HSRC
27
26
Hside
+
-
C5
ZERO CROSSING
COMPARATOR
CONTROL
LOGIC
Rsense
L
+
-
LINEAR
REGULATOR
4
2
V5SW
VIN
Vdc
5.5V to 25V
RGATE
30
31
C
Lside
PULSE SKIPPING
COMPARATOR
Load
+
-
PWRGND
SNSGND
32
1
12
16
VPROG
PWGOOD
ENABLE
OSCILLATOR
and
SYNC
OVER/UNDER VOLTAGE
COMPARATOR
POWER
MANAGEMENT
VSS
18
17
FREQ
19
25
5
5V
OSC
DISPROT
ICURLIM
NOSKIP
D98IN999
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
VIN to PWRGND
PWRGND to VSS
VREFS to PWRGND
-0.5 to 27
±0.5
V
5
V
HSTRAP, HGATE to PWRGND
RSTRAP, RGATE to PWRGND
-0.5V to VIN+14V
-0.5V to 14V
EABLE, FREQ, OSC, COMP, VFB, HRSNS, LRSNS
VID0-3, NOSKIP
5
V
V
7
Tj
Junction Temperature Range
Storage Temperature Range
-40 to 150
-55 to 150
°C
°C
Tstg
2/9
L5996
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction to Ambient
Value
Unit
RTh j-amb
60
°C/W
ELECTRICAL CHARACTERISTICS
( V = 12V; Ti = 25°C, OSC = GND, unless otherwise specified)
IN
•
= specifications referred to TJ from 0 to 70°C.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS
VIN
IOP
Input Supply Voltage
•
•
4.75
25
V
Operating Quiescent Current
RGATE = HGATE = OPEN
ENABLE = REG5
0.9
1.1
mA
ISB
Stand-By Current
ENABLE = GND
VIN = 12V
•
80
100
150
180
A
µ
µA
V
IN = 25V
INTERNAL REGULATOR (VREG5)
VREG5
Output Voltage
VIN = 7.5V to 25V
LOAD = 0 to 5mA,
CREG5 = 4.7 F
4.9
25
5.0
5.1
V
I
µ
IREG5
Total Current Capability
CREG5 = 4.7 F
µ
V
V
IN = 5.5V
IN ≥ 6V
mA
mA
60
Switch-Over Threshold Voltage
4.3
25
4.5
4.7
V
Current Capability
(internal switch on)
V5SW = 4.5 to 5.5V
REG5 ≥ 4.4V
mA
V
2.5V REFERENCE VOLTAGE
VO 2.5
Regulated Voltage
VIN 2.5 = 3.3V
VO 2.5 = 47µF
O 2.5 = 10mA
Regulation over Line and Load 6V < VIN < 25V
IN 2.5 = 3.3V
O 2.5 = 0-150mA
•
•
2.45
2.5
2.5
2.55
2.575
500
V
V
C
I
2.425
V
I
IVO 2.5 MAX Current Limit
VIN 2.5 = 3.3V
mA
PROGRAMMABLE REFERENCE VOLTAGE AND VBG
•
•
VPROG Accuracy VID0, VID1, VID2, VID3, VID4
-0.5%
-1%
VPROG
VPROG
+0.5%
+1%
V
V
see Table 1.
VFB
Ouput Voltage Accuracy
Line and Load Regulation
included, VID0, VID1, VID2, VID3
,
V
ID4, see Table 1.
•
VBG
Band Gap reference
CVBG = 220nF
1.240
2.4
1.246
1.252
V
POWER MANAGEMENT
Enable Voltage
HIGH LEVEL
LOW LEVEL
V
V
V
Disable Voltage
0.8
0.4
Power Good Saturation
Isink = 400 A
µ
Voltage
NOSKIP Mode (Active high)
High Level
Low Level
0.8
80
V
V
2.4
60
Output UVLO Threshold
OVP = GND
70
%
Output UVLO Lockout Time
Depending on CSS value
775
ms/µF
3/9
L5996
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
PROTECTION FUNCTIONS
V8-V7 Over-Current Threshold
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VSSTART = 3.1V
•
48
7
60
11
72
15
+4
mV
mV
Voltage
Pulse Skipping Mode
Threshold Voltage
NOSKIP = HIGH
Zero Crossing Threshold
Under-Voltage Threshold
-4
mV
V
Vprog
-13%
Vprog
-10%
Vprog
-7%
Upper Over-Voltage Threshold
Lower Over-Voltage Threshold
Vprog
+7%
Vprog
+10%
Vprog
+13%
V
V
Vprog
-4.5%
Over-Voltage Propagation
Time
1.5
1.5
µs
µs
Under-Voltage Propagation
Time
SOFT START
Soft start source current
Soft start clamp voltage
OSCILLATOR AND SYNC
fosc Fixed frequency
3.2
4
4.8
A
µ
3.1
V
OSC =0V; FREQ = REG5
•
225
180
250
200
275
220
120
KHz
KHz
KHz
OSC = REG5 FREQ = REG5 •
FREQ = REG5
OSC = EXTERNAL SIGNAL
f SINK MIN Minimum Synchronizzable
external frequency
Sync pulse width
Rising edge mode
200
3
ns
V
Sync pulse amplitude
5.5
•
FREQ and GND, OSC
connect to REG5 or GND
Rext = 680kΩ
fosc
Operating switching frequency Rext connected between
100
1
kHz
MHz
Rext = 40kΩ
HIGH AND LOW SIDE GATE DRIVERS
IOH5
RH5
IOH12
RH12
Output high source peak
current
HSTRAP = RSTRAP = REG5
550
3.5
2
mA
Ω
Output high sink impedance
Itest = 100mA,
HSTRAP = RSTRAP = REG5
Output high source peak
current
HSTRAP = RSTRAP = 12V
A
Output high sink impedance
Itest = 100mA,
2
Ω
HSTRAP - RSTRAP = 12V
IOL5
RL5
Output low peak current
Output low impedance
HSTRAP = RSTRAP = 5V
500
3
mA
Itest = 100mA,
Ω
HSTRAP = RSTRAP = 5V
IOL12
RL12
Output low peak current
Output low Impedance
HSTRAP = RSTRAP = 12V
2
2
A
Itest = 100mA,
HSTRAP = RSTRAP = 12V
Ω
TCC
Dead Time
GATE low to high
60
ns
4/9
L5996
FUNCTIONAL PIN DESCRIPTION
VPROG(pin11): Reference voltage test pin. This
pin provides the DAC output and should be de-
coupled to ground using a 0.22µF ceramic ca-
pacitor. No load has to be connected.
ENABLE(pin1): Enable input. A high level
(>2.4V) enables the device, a low level (<0.8V)
shuts it down. As ENABLE drops below 0.8V, the
drivers are turned off and all internal functionsare
disabled except REG5. In this condition the stand
by current is less than 80µA at VIN = 12V.
SNSGND(pin12):
Remote ground sense. This
pin is internally connected to the low power cir-
cuitry and for a precise output voltage regulation
can be connected to the output capacitor nega-
tive terminal.
VIN(pin2):
Device supply voltage. Input voltage
range at this pin is 4.75V to 25V and the operat-
ing current requirement at 12V is 650µA.
VIN2.5(pin13): 2.5V linear supply voltage. Is avail-
able on-chip a linear regulator useful for the 2.5V
bus. A max input voltage of 3.3V is recom-
mended at Iomax(150mA).
REG5(pin3): 5V Regulator supply. Used also to
supply the bootstrap capacitor. A minimum 2.2µF
ceramic capacitor connected to PWRGND is re-
quired.
VO2.5(pin14):
2.5V linear regulator output. The
linear regulator is realised with an internal NPN
transistor with +/-2% output accuracy. A mini-
mum of 47µF capacitor connected versus
PWRGND is required.
V5SW(pin4): 5V supply line. Connecting to 5V
bus(4.75V to 5.5V) the device is no longer pow-
ered by VIN but by this pin and the internal linear
regulator is disconnected increasing the effi-
ciency.
VBG(pin15):
220nF ceramic capacitor is required to assure the
band gap stability and noise immunity.
Band-gap reference voltage. A min
DISPROT (pin5) Disable Protection Functions. A
high level (3.3V CMOS LOGIC) on this pin dis-
ables the undervoltage and the overvoltage pro-
VSS(pin16):
connectedto the PWRGND pin.
Signal ground. This pin could be
SS
tection. Tie this pin to V for normal operation.
SSTART(pin6): Soft Start. The soft-start time is
programmed by an external capacitor connected
between this pin and SGND. The internal current
FREQ(pin17): Connecting an external resistor
versus ground is possible to select the switching
frequency between 100kHz and 1MHz. Using an
Rext=680k the fsw is 100kHz, using an Rext =
40k the fsw is 1MHz. In this condition is recom-
mended to connect the OSC pin to REG5 or to
VSS.
µ
generator forces 4 A throughthe capacitor imple-
menting the soft start function.
HRSNS(pin7): Error summing current sense non
inverting input.
OSC(pin18):
Connecting to REG5 is able to set
the switching frequency at 200kHz, connecting to
VSS is able to set the switching frequency at
250kHz. An external pulsed signal, with an ampli-
tude higher than 2.4V, could synchronise the de-
vice. In all these conditions pin FREQ has to be
connectedto REG5.
LRSNS(pin8):
verting input.
Error summing current sense in-
VFB(pin9): Regulator voltage feedback input.
Connect close to the CPU input supply pin realise
an accurate voltage regulation. VFB internally is
connected to the window comparator that is used
to increase the performance during the load tran-
sient.
OVP/CURLIM(pin19): Over voltage protection
and reduced current limit window. If the output
voltage reaches the 10% above the programmed
voltage (VPROG) this pin is driven low the high
side driver is turned off and the low, side driver is
turned on. All the internal blocks are active. The
device uses OVP function to discharge the output
during HIGH_TO_LOW core voltage transition.
The pin is driven low also during LOW_TO_HIGH
core voltage transition. The pin will stay low as
COMP(pin10):
Regulator stability compensation
pin. The compensation is realised internally and
normally it is not necessaryto connect any exter-
nal componentsto this pin.
5/9
L5996
long as the current limit value is reduced with re-
spect to the normal operating value. This is done
to limit voltage overshoots during core voltage
changes. Making this signal externally available
simplifies system debugging.
provide to supply the high side driver sinking the
current by the bootstrap capacitor.
RSTRAP(pin29):
Synchronous rectifier gate
driver supply voltage. This pin could be con-
nected to REG5 to reduce the switching losses
due to the external Mosfets gate capacitance.
This is useful to maintain an high efficiency at
light load.
VID0-4(pin20-24):
Voltage Identification code in-
put. These open collector compatible inputs are
used to program the output voltage as specified
in Table 1. Every pin has an internal pull up. If all
four pins are high or floating, the output voltage
and the 2.5V regulator are suspended and the
POWERGOOD is low.
RGATE(pin30): Gate driver output, low side N-
Channel switch. The driver internal impedance is
about 3Ω at VIN=12V.
NOSKIP(pin25):
high level (>2.4V) disables pulse skipping in low
load condition,a low level (>0.8V) enables it.
Pulse skipping mode control. A
PWRGND(pin31):
Power ground. This pin has to
be connected closely to the low side mosfet
source in order to reduce the noise injected into
the IC.
HSRC(pin26):
High side N-Channel switch
source connection. This pin provides the return
path for the high side driver.
POWER GOOD(pin32):
Open drain power good
output. This pin is pulled low if the output voltage
is not within ±10% and the 2.5V output is lower
than 2.175V (-13%). The pin is pulled low also if
REG5, VPROG and VBG have not reached the
expected values. This test could be useful in an
assembling fault condition.
HGATE(pin27): Gate driver output, high side N-
Channel switch. The driver internal impedance is
Ω
about 4 at VIN=12V.
HSTRAP(pin28):
Bootstrap capacitor pin. This pin
Table 1. VID [4:0] AND corresponding +VCC_CPU_CORE ranges
VID[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
+VCC_CPU_CORE
2.00V
VID[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
+VCC_CPU_CORE
1.275V
1.95V
1.250V
1.90V
1.225V
1.85V
1.200V
1.80V
1.175V
1.75V
1.150V
1.70V
1.125V
1.65V
1.100V
1.60V
1.075V
1.55V
1.050V
1.50V
1.025V
1.45V
1.000V
1.40V
0.975V
1.35V
0.950V
1.30V
0.925V
No CPU
No CPU
6/9
L5996
Figure 1. Application Circuit
Vin
4.5V to 25V
REG5
VIN
RSTRAP
SSTART
VBG
3
2
29
6
HSTRAP
28
27
15
HGATE
NOSKIP
VSS
Vo
25
16
18
HSRC
0.925V to 2.0V
26
30
31
OSC
FREQ
RGATE
PWRGND
17
5
L5996
Pentium III
Mobile
DISPROT
VPROG
11
HRSNS
LRSNS
SNSGND
VFB
7
8
5V BUS
V5SW
4
12
9
Vin2
3.3V
Vo2.5
13
14
Vo2
2.5V/150mA
19
20÷24
1
32
PWRGOOD
ENABLE
VID
ICURLIM
5
D98IN1000B
Figure 2. Output voltage transition between 1.3V and 1,5V measured at 200mA load current.
CH1: VID 2 transition.
CH2: Output voltage transition between 1.3V and 1.5V measured at 200mA load current.
7/9
L5996
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
A2
B
1.60
0.063
0.006
0.05
1.35
0.30
0.09
0.15 0.002
1.40
0.37
1.45 0.053 0.055 0.057
0.45 0.012 0.015 0.018
C
0.20 0.004
0.008
D
9.00
7.00
5.60
0.80
9.00
7.00
5.60
0.60
1.00
0.354
0.276
0.220
0.031
0.354
0.276
0.220
D1
D3
e
E
E1
E3
L
0.45
0.75 0.018 0.024 0.030
0.039
L1
K
TQFP32
0°(min.), 7°(max.)
D
A
D1
D3
A2
A1
24
17
25
16
0.10mm
.004
Seating Plane
9
32
8
1
C
e
K
TQFP32
8/9
L5996
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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