L6229D [STMICROELECTRONICS]
DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTOR; DMOS驱动三相无刷直流电机
| 型号： | L6229D |
| 厂家： | 
ST |
| 描述： | DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTOR |
| 文件： | 总25页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6229
DMOS DRIVER FOR
THREE-PHASE BRUSHLESS DC MOTOR
Figure 1. Package
1 FEATURES
■ OPERATING SUPPLY VOLTAGE FROM 8 TO
52V
■ 2.8A OUTPUT PEAK CURRENT (1.4A DC)
■ RDS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C
■ OPERATING FREQUENCY UP TO 100KHz
■ NON DISSIPATIVE OVERCURRENT
DETECTION AND PROTECTION
■ DIAGNOSTIC OUTPUT
PowerDIP24
(20+2+2)
■ CONSTANT tOFF PWM CURRENT
CONTROLLER
■ SLOW DECAY SYNCHR. RECTIFICATION
■ 60° & 120° HALL EFFECT DECODING LOGIC
■ BRAKE FUNCTION
PowerSO36
■ TACHO OUTPUT FOR SPEED LOOP
■ CROSS CONDUCTION PROTECTION
■ THERMAL SHUTDOWN
■ UNDERVOLTAGE LOCKOUT
■ INTEGRATED FAST FREEWEELING DIODES
SO24
(20+2+2)
2 DESCRIPTION
The L6229 is a DMOS Fully Integrated Three-Phase
Motor Driver with Overcurrent Protection.
Table 1. Order Codes
Realized in MultiPower-BCD technology, the device
combines isolated DMOS Power Transistors with
CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to drive a
three-phase BLDC motor including: a three-phase
DMOS Bridge, a constant off time PWM Current Con-
troller and the decoding logic for single ended hall
sensors that generates the required sequence for the
power stage.
Part Number
L6229N
Package
PowerDIP24
L6229PD
L6229PDTR
L6229D
PowerSO36
PowerSO36 in Tape & Reel
SO24
L6229DTR
SO24 in Tape & Reel
dissipative overcurrent protection on the high side
Power MOSFETs and thermal shutdown.
Available in PowerDIP24 (20+2+2), PowerSO36 and
SO24 (20+2+2) packages, the L6229 features a non-
Rev. 3
1/25
October 2004
L6229
Figure 2. Block Diagram
VBOOT
VSA
VBOOT
VCP
VBOOT
THERMAL
PROTECTION
CHARGE
PUMP
OCD1
OUT
1
DIAG
10V
OCD1
OCD2
OCD
OCD3
OCD
VBOOT
EN
BRAKE
FWD/REV
OCD2
OUT
2
GATE
LOGIC
H
3
10V
HALL-EFFECT
SENSORS
DECODING
LOGIC
H
2
1
SENSEA
VSB
VBOOT
H
TACHO
MONOSTABLE
RCPULSE
TACHO
OCD3
10V
OUT
3
10V
5V
SENSEB
PWM
VOLTAGE
REGULATOR
+
-
ONE SHOT
MONOSTABLE
MASKING
TIME
VREF
SENSE
COMPARATOR
RCOFF
D99IN1095B
Table 2. Absolute Maximum Ratings
Symbol
VS
Parameter
Supply Voltage
Test conditions
VSA = VSB = VS
Value
60
Unit
V
V
VOD
Differential Voltage between:
VSA, OUT1, OUT2, SENSEA
and VSB, OUT3, SENSEB
VSA = VSB = VS = 60V;
VSENSEA = VSENSEB = GND
60
VBOOT
VIN, VEN
VREF
Bootstrap Peak Voltage
VSA = VSB = VS
VS + 10
-0.3 to 7
-0.3 to 7
-0.3 to 7
-0.3 to 7
-1 to 4
V
V
V
V
V
V
Logic Inputs Voltage Range
Voltage Range at pin VREF
Voltage Range at pin RCOFF
VRCOFF
VRCPULSE Voltage Range at pin RCPULSE
VSENSE
IS(peak)
IS
Voltage Range at pins SENSEA
and SENSEB
Pulsed Supply Current (for each VSA = VSB = VS; TPULSE < 1ms
VSA and VSB pin)
3.55
1.4
A
A
DC Supply Current (for each
VSA and VSB pin)
VSA = VSB = VS
T
stg, TOP Storage and Operating
-40 to 150
°C
Temperature Range
2/25
L6229
Table 3. Recommended Operating Condition
Symbol
VS
Parameter
Supply Voltage
Test Conditions
VSA = VSB = VS
MIN
MAX
52
Unit
V
12
VOD
Differential Voltage between:
VSA, OUT1, OUT2, SENSEA and
VSB, OUT3, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
52
V
VREF
Voltage Range at pin VREF
-0.1
5
V
VSENSE
Voltage Range at pins SENSEA
and SENSEB
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
IOUT
TJ
DC Output Current
VSA = VSB = VS
1.4
125
100
A
Operating Junction Temperature
Switching Frequency
-25
°C
fSW
KHz
Table 4. Thermal Data
Symbol
Description
PDIP24
SO24
PowerSO36
Unit
°C/W
°C/W
°C/W
Rth(j-pins)
Rth(j-case) Maximum Thermal Resistance Junction-Case
Maximum Thermal Resistance Junction-Pins
19
15
2
-
MaximumThermal Resistance Junction-Ambient (1)
Maximum Thermal Resistance Junction-Ambient (2)
MaximumThermal Resistance Junction-Ambient (3)
Maximum Thermal Resistance Junction-Ambient (4)
Rth(j-amb)1
Rth(j-amb)1
Rth(j-amb)1
Rth(j-amb)2
44
-
55
-
36
16
63
°C/W
°C/W
°C/W
-
-
59
78
2
(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm (with a thickness of 35 µm).
2
(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm).
2
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm),
16 via holes and a ground layer.
(4) Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board.
3/25
L6229
Figure 3. Pin Connections (Top view)
GND
N.C.
N.C.
VSA
1
GND
N.C.
N.C.
VSB
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
2
H
1
24
23
22
21
20
19
18
17
16
15
14
13
H
H
3
1
3
2
4
DIAG
SENSEA
RCOFF
2
OUT
2
5
OUT
3
3
VCP
OUT
VSA
N.C.
VCP
6
N.C.
4
2
7
VBOOT
BRAKE
VREF
EN
OUT
5
1
H
2
8
GND
GND
6
GND
GND
VSB
H
3
9
7
H
1
10
11
12
13
14
15
16
17
18
TACHO
RCPULSE
SENSEB
FWD/REV
EN
8
DIAG
SENSEA
RCOFF
N.C.
FWD/REV
SENSEB
RCPULSE
N.C.
9
OUT
3
10
11
12
VBOOT
BRAKE
VREF
OUT
1
TACHO
N.C.
N.C.
N.C.
GND
D01IN1194A
N.C.
GND
D01IN1195A
PowerSO36 (5)
PowerDIP24/SO24
(5) The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 5. Pin Description
PACKAGE
SO24/
PowerDIP24
PowerSO36
Name
Type
Function
PIN #
PIN #
10
1
2
H1
Sensor Input Single Ended Hall Effect Sensor Input 1.
11
DIAG
Open Drain Overcurrent Detection and Thermal Protection pin. An
Output
internal open drain transistor pulls to GND when an
overcurrent on one of the High Side MOSFETs is
detected or during Thermal Protection.
3
4
5
12
13
15
SENSEA
RCOFF
Power Supply Half Bridge 1 and Half Bridge 2 Source Pin. This pin
must be connected together with pin SENSEB to
Power Ground through a sensing power resistor.
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current
Controller OFF-Time.
OUT1
GND
Power Output Output 1
6, 7,
1, 18,
GND Ground terminals. On PowerDIP24 and SO24
18, 19
19, 36
packages, these pins are also used for heat
dissipation toward the PCB. On PowerSO36 package
the slug is connected on these pins.
8
9
22
24
TACHO
Open Drain Frequency-to-Voltage open drain output. Every pulse
Output
from pin H1 is shaped as a fixed and adjustable length
pulse.
RCPULSE
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the duration of the
Monostable Pulse used for the Frequency-to-Voltage
converter.
4/25
L6229
Table 5. Pin Description (continued)
PACKAGE
SO24/
PowerDIP24
PowerSO36
Name
Type
Function
PIN #
PIN #
10
25
SENSEB
Power Supply Half Bridge 3 Source Pin. This pin must be connected
together with pin SENSEA to Power Ground through a
sensing power resistor. At this pin also the Inverting
Input of the Sense Comparator is connected.
11
12
26
27
FWD/REV
EN
Logic Input
Selects the direction of the rotation. HIGH logic level
sets Forward Operation, whereas LOW logic level sets
Reverse Operation.
If not used, it has to be connected to GND or +5V..
Logic Input
Chip Enable. LOW logic level switches OFF all Power
MOSFETs.
If not used, it has to be connected to +5V.
13
14
28
29
VREF
Logic Input
Logic Input
Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
BRAKE
Brake Input pin. LOW logic level switches ON all High
Side Power MOSFETs, implementing the Brake
Function.
If not used, it has to be connected to +5V.
15
30
VBOOT
Supply Voltage Bootstrap Voltage needed for driving the upper Power
MOSFETs.
16
17
32
33
OUT3
VSB
Power Output Output 3.
Power Supply Half Bridge 3 Power Supply Voltage. It must be
connected to the supply voltage together with pin VSA.
20
4
VSA
Power Supply Half Bridge 1 and Half Bridge 2 Power Supply Voltage.
It must be connected to the supply voltage together
with pin VSB.
21
22
23
24
5
7
8
9
OUT2
VCP
H2
Power Output Output 2.
Output
Charge Pump Oscillator Output.
Sensor Input Single Ended Hall Effect Sensor Input 2.
Sensor Input Single Ended Hall Effect Sensor Input 3.
H3
Table 6. Electrical Characteristics
(VS = 48V , Tamb = 25 °C , unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
5.8
5
Typ
6.3
5.5
5
Max
6.8
6
Unit
V
VSth(ON) Turn ON threshold
VSth(OFF) Turn OFF threshold
V
IS
Quiescent Supply Current
All Bridges OFF;
Tj = -25 to 125°C (6)
10
mA
TJ(OFF) Thermal Shutdown Temperature
165
°C
Output DMOS Transistors
RDS(ON) High-Side + Low-Side Switch ON
Resistance
Tj = 25 °C
1.47
2.35
1.69
2.70
Ω
Ω
Tj =125 °C (7)
IDSS
Leakage Current
EN = Low; OUT = VCC
EN = Low; OUT = GND
2
mA
mA
-0.3
5/25
L6229
Table 6. Electrical Characteristics (continued)
(VS = 48V , Tamb = 25 °C , unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Source Drain Diodes
VSD
trr
Forward ON Voltage
ISD = 1.4A, EN = LOW
If = 1.4A
1.15
300
200
1.3
V
Reverse Recovery Time
Forward Recovery Time
ns
ns
tfr
Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE)
VIL
VIH
IIL
Low level logic input voltage
High level logic input voltage
Low level logic input current
High level logic input current
-0.3
2
0.8
7
V
V
GND Logic Input Voltage
7V Logic Input Voltage
-10
µA
µA
V
IIH
10
Vth(ON) Turn-ON Input Threshold
Vth(OFF) Turn-OFF Input Threshold
VthHYS Input Thresholds Hysteresys
Switching Characteristics
1.8
1.3
0.5
2.0
0.8
V
0.25
V
Enable to out turn-ON delay time (7)
tD(on)EN
ILOAD = 1.4 A, Resistive Load
ILOAD = 1.4 A, Resistive Load
500
500
650
800
ns
ns
µs
(7
)
tD(off)EN
1000
Enable to out turn-OFF delay time
tD(on)IN Other Logic Inputs to Output Turn- ILOAD = 1.4 A, Resistive Load
ON delay Time
1.6
tD(off)IN Other Logic Inputs to out Turn-OFF ILOAD = 1.4 A, Resistive Load
delay Time
800
ns
Output Rise Time (7)
tRISE
tFALL
tDT
fCP
ILOAD = 1.4 A, Resistive Load
ILOAD = 1.4 A, Resistive Load
40
40
250
250
ns
ns
Output Fall Time (7)
Dead Time
0.5
1
µs
Tj = -25 to 125°C (6)
Charge Pump Frequency
0.6
1
MHz
PWM Comparator and Monostable
Source current at pin RCOFF
I
VRCOFF = 2.5 V
Vref = 0.5 V
3.5
5.5
5
mA
mV
RCOFF
VOFFSET Offset Voltage on Sense
Comparator
Turn OFF Propagation delay (8)
tprop
Vref = 0.5 V
500
1
ns
µs
tblank
Internal Blanking Time on Sense
Comparator
tON(min) Minimum on Time
2.5
13
3
µs
µs
µs
µA
tOFF
PWM RecirculationTime
ROFF= 20kΩ ; COFF =1nF
ROFF= 100kΩ ; COFF =1nF
61
IBIAS
Input Bias Current at pin VREF
10
Tacho Monostable
IRCPULSE Source Current at pin RCPULSE
VRCPULSE = 2.5V
3.5
5.5
mA
6/25
L6229
Table 6. Electrical Characteristics (continued)
(VS = 48V , Tamb = 25 °C , unless otherwise specified)
Symbol
Parameter
Test Conditions
RPUL = 20kΩ ; CPUL =1nF
RPUL = 100kΩ ; CPUL =1nF
Min
Typ
12
Max
Unit
µs
tPULSE Monostable of Time
60
µs
RTACHO Open Drain ON Resistance
40
60
Ω
Over Current Detection & Protection
TJ = -25 to 125°C (6)
ISOVER Supply Overcurrent Protection
Threshold
2
2.8
3.55
60
A
ROPDR Open Drain ON Resistance
IDIAG = 4mA
40
1
Ω
µA
ns
IOH
OCD high level leakage current
OCD Turn-ON Delay Time (9)
OCD Turn-OFF Delay Time (9)
VDIAG = 5V
tOCD(ON)
IDIAG = 4mA; CDIAG < 100pF
200
t
IDIAG = 4mA; CDIAG < 100pF
100
ns
OCD(OFF)
(6) Tested at 25°C in a restricted range and guaranteed by characterization.
(7) See Fig. 4.
(8) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(9) See Fig. 5.
Figure 4. Switching Characteristic Definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tFALL
tRISE
tD(OFF)EN
tD(ON)EN
Figure 5. Overcurrent Detection Timing Definition
I
OUT
SOVER
I
ON
BRIDGE
OFF
V
DIAG
90%
10%
D02IN1387
t
t
OCD(OFF)
OCD(ON)
7/25
L6229
3 CIRCUIT DESCRIPTION
3.1 POWER STAGES and CHARGE PUMP
The L6229 integrates a Three-Phase Bridge, which consists of 6 Power MOSFETs connected as shown on the
Block Diagram. Each Power MOS has an R
diode. Switching patterns are generated by the PWM Current Controller and the Hall Effect Sensor Decoding
= 0.73
Ω
(typical value @25°C) with intrinsic fast freewheeling
DS(ON)
Logic (see relative paragraphs). Cross conduction protection is implemented by using a dead time (t = 1µs
DT
typical value) set by internal timing circuit between the turn off and turn on of two Power MOSFETs in one leg
of a bridge.
Pins VS and VS MUST be connected together to the supply voltage (V ).
A
B
S
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The Bootstrapped Supply (V ) is obtained through an internal oscillator and few ex-
BOOT
ternal components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a
square wave at 600KHz (typically) with 10V amplitude. Recommended values/part numbers for the charge
pump circuit are shown in Table 7.
Table 7. Charge Pump External Component Values.
CBOOT
220nF
CP
10nF
RP
100Ω
D1
1N4148
1N4148
D2
Figure 6. Charge Pump Circuit
VS
D1
D2
CBOOT
RP
CP
D01IN1328
VCP
VBOOT
VSA VSB
3.2 LOGIC INPUTS
Pins FWD/REV, BRAKE, EN, H , H and H are TTL/CMOS and µC compatible logic inputs. The internal struc-
1
2
3
ture is shown in Figure 4. Typical value for turn-ON and turn-OFF thresholds are respectively V
= 1.8V and
th(ON)
V
= 1.3V.
th(OFF)
Pin EN (enable) may be used to implement Overcurrent and Thermal protection by connecting it to the open collector
DIAG output If the protection and an external disable function are both desired, the appropriate connection must be
implemented. When the external signal is from an open collector output, the circuit in Figure 8 can be used . For ex-
ternal circuits that are push pull outputs the circuit in Figure 9 could be used. The resistor REN should be chosen in
the range from 2.2K
Ω to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF. More
information for selecting the values can be found in the Overcurrent Protection section.
8/25
L6229
Figure 7. Logic Input Internal Structure
5V
ESD
PROTECTION
D01IN1329
Figure 8. Pin EN Open Collector Driving
DIAG
EN
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
CEN
ESD
PROTECTION
D02IN1378
Figure 9. Pin EN Push-Pull Driving
DIAG
EN
5V
REN
PUSH-PULL
OUTPUT
CEN
ESD
PROTECTION
D02IN1379
3.3 PWM CURRENT CONTROL
The L6229 includes a constant off time PWM Current Controller. The current control circuit senses the bridge
current by sensing the voltage drop across an external sense resistor connected between the source of the
three lower power MOS transistors and ground, as shown in Figure 10. As the current in the motor increases
the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor
becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the mo-
tor current recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section.
When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent
cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time t
the monostable time plus the dead time.
is the sum of
OFF
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re-
9/25
L6229
verse recovery of the freewheeling diodes. The L6229 provides a 1µs Blanking Time t
that inhibits the
BLANK
comparator output so that the current spike cannot prematurely retrigger the monostable.
Figure 10. PWM Current Controller Simplified Schematic
VS
VSB
VSA
BLANKING TIME
MONOSTABLE
TO GATE
LOGIC
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
5mA
MONOSTABLE
SET
BLANKER
S
R
OUT
OUT
OUT
2
3
1
Q
(0)
(1)
DRIVERS
+
DRIVERS
+
-
DEAD TIME
DEAD TIME
DRIVERS
+
5V
+
DEAD TIME
2.5V
+
-
SENSE
COMPARATOR
RCOFF
ROFF
SENSE
SENSE
A
VREF
B
COFF
R
SENSE
D02IN1380
Figure 11. Output Current Regulation Waveforms
I
OUT
V
REF
R
SENSE
t
t
t
OFF
OFF
ON
1µs t
1µs t
BLANK
V
BLANK
SENSE
V
REF
Slow Decay
Slow Decay
0
t
t
V
RC
RCRISE
RCRISE
5V
2.5V
t
t
RCFALL
RCFALL
1µs t
1µs t
DT
DT
ON
SYNCHRONOUS RECTIFICATION
D02IN1351
OFF
B
C
D
A
B
C
D
10/25
L6229
Figure 12 shows the magnitude of the Off Time t
calculated from the equations:
versus C
and R values. It can be approximately
OFF
OFF
OFF
t
t
= 0.6 · R
· C
RCFALL
OFF OFF
= t
+ t = 0.6 · R
· C
+ t
OFF
OFF
RCFALL
DT
OFF
DT
where R
and C
are the external component values and t is the internally generated Dead Time with:
OFF DT
OFF
20KΩ ≤
0.47nF
= 1µs (typical value)
R
≤
100KΩ
OFF
≤
C
≤
100nF
OFF
t
DT
Therefore:
t
t
= 6.6µs
= 6ms
OFF(MIN)
OFF(MAX)
These values allow a sufficient range of t
to implement the drive circuit for most motors.
OFF
The capacitor value chosen for C
also affects the Rise Time t
of the voltage at the pin RCOFF. The
OFF
RCRISE
Rise Time t
will only be an issue if the capacitor is not completely charged before the next time the
RCRISE
monostable is triggered. Therefore, the On Time t , which depends by motors and supply parameters, has to
ON
be bigger than t
can not be smaller than the minimum on time t
for allowing a good current regulation by the PWM stage. Furthermore, the On Time t
RCRISE
ON
.
ON(MIN)
t
ON > tON(MIN) = 2.5µs (typ. value)
ON > tRCRISE – tDT
⎧
⎨
⎩
t
t
= 600 · C
OFF
RCRISE
Figure 13 shows the lower limit for the On Time t for having a good PWM current regulation capacity. It has
ON
to be said that t is always bigger than t
because the device imposes this condition, but it can be smaller
ON
ON(MIN)
than t
- t . In this last case the device continues to work but the Off Time t
RCRISE DT
is not more constant.
OFF
So, small C
value gives more flexibility for the applications (allows smaller On Time and, therefore, higher
OFF
switching frequency), but, the smaller is the value for C
, the more influential will be the noises on the circuit
OFF
performance.
Figure 12. tOFF versus COFF and ROFF
.
4
.
1 10
= 100kΩ
Roff
3
.
1 10
= 47kΩ
Roff
= 20kΩ
Roff
100
10
1
0.1
1
10
100
Coff [nF]
11/25
L6229
Figure 13. Area where tON can vary maintaining the PWM regulation.
100
10
µ
1.5 s (typ. value)
1
0.1
1
10
100
Coff [nF]
3.4 SLOW DECAY MODE
Figure 14 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two
legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure
and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current
recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slow-
ly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the
impendence of the freewheeling diode and the related conducting losses. When the monostable times out, up-
per MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after
some delay set by the Dead Time to prevent cross conduction.
Figure 14. Slow Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
D01IN1336
12/25
L6229
3.5 DECODING LOGIC
The Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase
bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3-
phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors
spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a uni-
versal IC without dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor posi-
tions with 120 electrical degrees sensor phasing (see Figure 15, positions 1, 2, 3a, 4, 5 and 6a) and six combi-
nations are valid for rotor positions with 60 electrical degrees phasing (see Figure 17, positions 1, 2, 3b, 4, 5
and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 elec-
trical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phas-
ing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the Table 8. For any input
configuration (H , H and H ) there is one output configuration (OUT , OUT and OUT ). The output configura-
1
2
3
1
2
3
tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the
Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive
the motor with all the four conventions by changing the direction set.
Table 8. 60 and 120 Electrical Degree Decoding Logic in Forward Direction.
Hall 120°
Hall 60°
H1
1
1
2
2
3a
-
-
3b
4
4
5
5
6a
-
-
6b
H
H
L
H
L
L
H
L
H2
L
H
H
H
H
L
L
L
H3
L
L
L
H
H
H
H
L
OUT1
OUT2
OUT3
Phasing
Vs
High Z
Vs
GND
Vs
GND
Vs
GND
High Z
Vs
High Z
GND
Vs
Vs
Vs
High Z
GND
1->3
GND
High Z
1->2
GND
High Z
1->2
GND
2->3
High Z
2->1
High Z
2->1
3->1
3->2
Figure 15. 120° Hall Sensor Sequence.
H1
H1
H1
H1
H1
H1
H3
H2 H3
H2 H3
H2 H3
H2 H3
H2 H3
H2
1
2
3a
4
5
6a
= H
= L
13/25
L6229
Figure 16. 60° Hall Sensor Sequence.
H1
H1
H1
H1
H1
H1
H2
H2
H2
H2
H2
H2
H3
H3
H3
H3
H3
H3
1
2
3b
4
5
6b
= H
= L
3.6 TACHO
A tachometer function consists of a monostable, with constant off time (t
), whose input is one Hall Effect
PULSE
signal (H ). It allows developing an easy speed control loop by using an external op amp, as shown in Figure
1
18. For component values refer to Application Information section.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall Effect Sensors
H , the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time
1
t
(see Figure 17). The off time t
can be set using the external RC network (R
, C
) connected
PULSE
PULSE
PUL
PUL
to the pin RCPULSE. Figure 19 gives the relation between t
and C
, R
. We have approximately:
PULSE
PUL
PUL
t
= 0.6 · R
· C
PUL PUL
PULSE
where C
should be chosen in the range 1nF … 100nF and R
in the range 20KΩ … 100KΩ.
PUL
PUL
By connecting the tachometer pin to an external pull-up resistor, the output signal average value V is propor-
M
tional to the frequency of the Hall Effect signal and, therefore, to the motor speed. This realizes a simple Fre-
quency-to-Voltage Converter. An op amp, configured as an integrator, filters the signal and compares it with a
reference voltage V
, which sets the speed of the motor.
REF
tPULSE
-----------------
T
VM
=
⋅ VDD
Figure 17. Tacho Operation Waveforms.
H1
H2
H3
VTACHO
VM
VDD
tPULSE
T
14/25
L6229
Figure 18. Tachometer Speed Control Loop.
H1
RCPULSE
TACHO
MONOSTABLE
VDD
RPUL
CPUL
RDD
R3
TACHO
C1
R4
VREF
CREF1
R1
VREF
CREF2
R2
Figure 19. tPULSE versus CPUL and RPUL
.
4
.
1 10
Ω
= 100k
RPUL
Ω
= 47k
RPUL
3
.
1 10
Ω
= 20k
RPUL
100
10
1
10
Cpul [nF]
100
15/25
L6229
3.7 NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTION
The L6229 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides Output-to-
Output and Output-to-Ground short circuit protection as well. With this internal over current detection, the exter-
nal current sense resistor normally used and its associated power dissipation are eliminated. Figure 20 shows
a simplified schematic for the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each High Side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
. When the output current reaches the detection threshold (typically I
= 2.8A) the OCD compar-
REF
SOVER
ator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a µC or to shut down the Three-Phase Bridge simply
by connecting it to pin EN and adding an external R-C (see R , C ).
EN
EN
Figure 20. Overcurrent Protection Simplified Schematic
OUT1 VSA OUT2
OUT3 VSB
HIGH SIDE DMOS
I1
HIGH SIDE DMOS
I2
HIGH SIDE DMOS
I3
POWER SENSE
1 cell
TO GATE
POWER SENSE
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
POWER DMOS
n cells
1 cell
µC or LOGIC
+
LOGIC
VDD
I1 / n
I2/ n
OCD
COMPARATOR
REN
CEN
EN
I1+I2 / n
IREF
INTERNAL
OPEN-DRAIN
DIAG
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
I3/ n
IREF
D02IN1381
Figure 21 shows the Overcurrent Detetection operation. The Disable Time t
before recovering normal
DISABLE
operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected
whether by C and R values and its magnitude is reported in Figure 22. The Delay Time t before turn-
EN
EN
DELAY
ing off the bridge when an overcurrent has been detected depends only by C value. Its magnitude is reported
EN
in Figure 23
C
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
EN
should be chosen as big as possible according to the maximum tolerable Delay Time and the R value should
EN
be chosen according to the desired Disable Time.
The resistor R should be chosen in the range from 2.2K
Ω
to 180K
Ω. Recommended values for R and C
EN EN
EN
are respectively 100K
Ω and 5.6nF that allow obtaining 200µs Disable Time.
16/25
L6229
Figure 21. Overcurrent Protection Waveforms
I
OUT
I
SOVER
V
=V
EN DIAG
V
DD
V
th(ON)
V
th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF
t
t
DELAY
DISABLE
t
t
t
t
t
OCD(ON)
EN(FALL)
OCD(OFF)
EN(RISE)
D(ON)EN
D02IN1383
t
D(OFF)EN
Figure 22. tDISABLE versus CEN and REN
.
Ω
Ω
R E N = 100 k
R E N = 2 20 k
3
.
Ω
Ω
R E N = 47 k
R E N = 33 k
1
10
Ω
R E N = 10 k
1 00
10
1
1
10
1 00
C E N [n F ]
Figure 23. tDELAY versus CEN
.
10
1
0.1
1
10
100
Cen [nF]
17/25
L6229
4 APPLICATION INFORMATION
A typical application using L6229 is shown in Figure 24. Typical component values for the application are shown
in Table 9. A high quality ceramic capacitor (C ) in the range of 100nF to 200nF should be placed between the
2
power pins VS and VS and ground near the L6229 to improve the high frequency filtering on the power supply
A
B
and reduce high frequency transients generated by the switching. The capacitor (C ) connected from the EN
EN
input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two
current sensing inputs (SENSE and SENSE ) should be connected to the sensing resistor R with a trace
A
B
SENSE
length as short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the di/
dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5V (High
Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and
Signal Ground separated on PCB.
Table 9. Component Values for Typical Application.
C1
C2
100µF
100nF
220nF
220nF
1nF
R1
R2
5K6Ω
1K8Ω
4K7Ω
1MΩ
C3
R3
CBOOT
COFF
CPUL
CREF1
CREF2
CEN
CP
R4
RDD
1KΩ
10nF
REN
100KΩ
100Ω
0.6Ω
33nF
RP
100nF
5.6nF
10nF
RSENSE
ROFF
RPUL
RH1, RH2, RH3
33KΩ
47KΩ
10KΩ
D1
1N4148
1N4148
D2
Figure 24. Typical Application
R1
VSA
VSB
VREF
13
+
-
VREF
CREF2
+
VS
8-52VDC
20
17
C1
C2
CREF1
R2
C3
POWER
GROUND
-
D1
CP
RP
VCP
22
DIAG
2
D2
R4
CBOOT
REN
CEN
VBOOT
SENSEA
SENSEB
EN
12
15
3
ENABLE
SIGNAL
GROUND
RSENSE
R3
11
FWD/REV
BRAKE
10
FWD/REV
THREE-PHASE MOTOR
OUT
OUT
OUT
14
1
2
3
5
BRAKE
HALL
M
21
16
SENSOR
8
+5V
RH1
TACHO
COFF
RDD
H
H
H
1
2
3
1
RH2
RH3
5V
23
24
4
9
RCOFF
ROFF
CPUL
18
19
6
RCPULSE
7
RPUL
GND
D02IN1357
18/25
L6229
4.1 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Figure 25 is shown the approximate relation between the output current and the IC power dissipation using
PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which
package should be used and how large must be the on-board copper dissipating area to guarantee a safe op-
erating junction temperature (125°C maximum).
Figure 25. IC Power Dissipation versus Output Power.
I1
IOUT
10
I2
IOUT
8
6
4
2
0
PD [W]
I3
IOUT
Test Conditions:
Supply Voltage = 24 V
No PWM
fSW = 30 kHz (slow decay)
0
0.25 0.5 0.75
1
1.25 1.5
I
OUT [A]
4.2 THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking con-
figuration for the application is required to maintain the IC within the allowed operating temperature range for
the application. Figures 26, 27 and 28 show the Junction-to-Ambient Thermal Resistance values for the
PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
2
with 6cm dissipating footprint (copper thickness of 35
µ
m), the R
is about 35°C/W. Figure 29 shows
th(j-amb)
mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance
can be reduced down to 15°C/W.
Figure 26. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
43
38
33
W ithout Ground Layer
28
W ith Ground Layer
W ith Ground Layer+16 via
H oles
23
On-Board Copper Area
18
13
1
2
3
4
5
6
7
8
9
10 11 12 13
sq. cm
19/25
L6229
Figure 27. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
On-Board Copper Area
49
48
Copper Are a is on Bottom
S ide
47
46
Copper Are a is on To p Side
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10 11 12
sq. cm
Figure 28. SO24 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
On-Board Copper Area
68
66
64
62
60
C o pp er Are a is on Top Sid e
58
56
54
52
50
48
1
2
3
4
5
6
7
8
9
10 11 12
sq. cm
Figure 29. Mounting the PowerSO Package.
Slug soldered
to PCB with
dissipating area
Slug soldered
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
to PCB with
dissipating area
plus ground layer
20/25
L6229
Figure 30. PowerSO36 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN. TYP. MAX. MIN.
TYP. MAX.
0.138
0.13
OUTLINE AND
MECHANICAL DATA
A
A2
A4
A5
a1
b
3.25
3.5
3.3
1
0.128
0.031
0
0.8
0.039
0.008
0.003
0.015
0.012
0.630
0.38
0.2
0
0.075
0.22
0.23
15.8
9.4
0.38 0.008
0.32 0.009
c
D
16
0.622
0.37
D1
D2
E
9.8
1
0.039
0.57
13.9
10.9
14.5 0.547
11.1 0.429
2.9
E1
E2
E3
E4
e
0.437
0.114
0.244
1.259
0.026
0.435
0.003
0.625
0.043
0.043
5.8
2.9
6.2
3.2
0.228
0.114
0.65
e3
G
11.05
0
0.075
15.9
1.1
0
H
15.5
0.61
h
L
0.8
1.1
0.031
N
10˚ (max)
8˚ (max)
s
PowerSO36
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
N
N
a2
A
c
a1
e
A
DETAIL B
lead
E
DETAIL A
e3
H
DETAIL A
D
slug
a3
BOTTOM VIEW
36
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
- C -
SEATING PLANE
1
1
8
S
L
G
C
M
b
0.12
A B
PSO36MEC
h x 45
(COPLANARITY)
0096119 B
21/25
L6229
Figure 31. PDIP-24 Mechanical Data & Package Dimensions
mm
MIN. TYP. MAX. MIN. TYP. MAX.
4.320 0.170
inch
DIM.
OUTLINE AND
MECHANICAL DATA
A
A1
A2
B
0.380
0.015
3.300
0.130
0.410 0.460 0.510 0.016 0.018 0.020
1.400 1.520 1.650 0.055 0.060 0.065
0.200 0.250 0.300 0.008 0.010 0.012
31.62 31.75 31.88 1.245 1.250 1.255
B1
c
D
E
7.620
8.260 0.300
0.325
e
2.54
0.100
E1
6.350 6.600 6.860 0.250 0.260 0.270
0.300
7.620
e1
L
3.180
3.430 0.125
0.135
PDIP 24 (0.300")
M
0˚ min, 15˚ max.
E1
A2
A
A1
L
B
B1
e
e1
D
24
1
13
12
c
M
SDIP24L
0034965 D
22/25
L6229
Figure 32. SO24 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.104
A
A1
B
2.35
0.10
0.33
0.23
15.20
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
15.60 0.598
0.012
0.200
Weight: 0.60gr
C
0.013
(1)
D
0.614
E
e
7.40
7.60 0.291
0.299
0.050
1.27
H
10.0
0.25
0.40
10.65 0.394
0.75 0.010
1.27 0.016
0˚ (min.), 8˚ (max.)
0.10
0.419
h
0.030
L
0.050
k
ddd
0.004
SO24
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
0070769 C
23/25
L6229
Table 10. Revision History
Date
Revision
Description of Changes
September 2003
January 2004
October 2004
1
2
3
First Issue
Migration from ST-Press dms to EDOCS.
Updated the style graphic form.
24/25
L6229
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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