L6246 [STMICROELECTRONICS]
12V VOICE COIL MOTOR DRIVER; 12V音圈电机驱动器
| 型号： | L6246 |
| 厂家： | 
ST |
| 描述： | 12V VOICE COIL MOTOR DRIVER |
| 文件： | 总12页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6246
12V VOICE COIL MOTOR DRIVER
12V (±10%) OPERATION
3A MAXIMUM CURRENT CAPABILITY
MULTIPOWER BCD TECHNOLOGY
0.3 MAXIMUM ON RESISTANCE OF EACH
Ω
POWER DMOS AT A JUNCTION TEM-
PERATAURE OF 25°C
CLASS AB POWER AMPLIFIERS
LOGIC AND POWER SUPPLY MONITOR
POWER ON RESET
PARKING FUNCTION WITH SELECTABLE
RETRACT VOLTAGE AND DYNAMIC BRAKE
BEFORE PARKING
PQFP44 (10x10)
ENABLE FUNCTION
GATE DRIVER FOR EXTERNAL BLOCKING
N-MOSFET
OVERTEMPERATUREPROTECTION
OVERTEMPERATUREWARNING OUTPUT
PQFP44 PACKAGE
figuration. Drive voltage for the upper DMOS
FETs is provided by a charge pump circuit to en-
sure low Rdson.
Automatic brake and parking of the head actuator
is performed by logic or when a failure condition
is detected by power supply monitors. An external
resistor programs the parking voltage that en-
ables the head retract. In addition, a 5V stable
output is provided for the external usage, and a
gate driver circuit enables an external power sup-
ply isolation N-MOSFET.
This device is built in BCD II technology allowing
dense digital circuitry to be combined with high
power bipolar power devices and is assembled in
PQFP44.
DESCRIPTION
The voice coil driver L6246 is a linear power am-
plifier designed to drive single phase bipolar DC
motors for hard disk drive applications. The de-
vice contains a selectable transconductanceloop,
which allows high precision for head positioning.
The power stage is composed of 2 power amplifi-
ers, in AB class, with 4 DMOSs, with Rdson of
0.5Ω (Sink+Source) maximum, in a H-bridge con-
1/12
February 1998
L6246
PIN CONNECTION (Top view)
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
N.C.
33
32
31
30
29
28
27
26
25
24
23
N.C.
FILTER_CAP
BRAKE DELAY
-THERMAL SD
SENSE-IN+
SENSE-IN-
GND
ENABLE
-SPINDLE START
VCM PARK
-W_GATE
RPARK
VBEMF
ERR-OUT
ERR-
+12SETPT
+5SETPT
+5V REF_GND
N.C.
SENSE-OUT
N.C.
10
11
12 13 14 15 16 17 18 19 20 21 22
D95IN241B
BLOCK DIAGRAM
-SPINDLE MOTOR
START START W_GATE
-W_GATE
-AE
VCM
PARK
CP_GND
GATE DRIVE
INPUT
AMPLIFIER
VIN-
C1
C2
VIN+
CHARGE
PUMP
GATE
DRIVER
VCP
VIN_OUT
-POR
VCC
+5
30K
THERMAL
-THERMAL SD
BRAKE DELAY
4µA
+12
FILTER CAP
25K
+
-
10K
BRAKE
CIRCUIT
10K
+
-
REF1
VDD
POWER AMPLIFIERS
VCC
-
10K
20K
+
+5
FILTER CAP
+
-
OUT+
T_CAP
REF1
VCC/2
VPARK
+
-
PARKING
RPARK
GND
VCC
ERR_OUT
ERROR
AMPL.
VCC/2
+
ERR-
-
SENSE
AMPLIFIER
+
-
+
-
OUT-
GND
REF1
+5V REF
REF. VOLT.
GENERATOR
+5V REF_GND
D95IN242B
VCC/2
SENSE
_IN+
SENSE
_IN-
SENSE_
OUT
VBEMF
2/12
L6246
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Vpow. max.
Vdigitalmax.
Vin max.
Vin min.
Ipeak
Maximum supply voltage
Maximum supply voltage
Maximum input voltage
Minimum input voltage
15
7
V
V
digital ±0.3
V
GND - 0.3
V
Peak sink/source output current
DC sink/source output current
Maximum total power dissipation
Operative temperature range
3
1.7
A
Idc
A
Ptot
1.7
W
°C
Top
0 to 80
THERMAL DATA
Symbol
Parameter
Value
20
Unit
°C/W
°C/W
°C/W
Rth j-case
Rth j-amb
Rth j-amb
Thermal resistance junction to case
Thermal resistance junction toambient mountedon standard PCB (*)
Thermal resistance junction to ambient mounted on PCB (**)
66
35
(*) Standard board construction: single layer (1S 0P); size 100mm long by 100mm wide.
(**) The board construction includes: a 6 layer board (2S 4P, with power planes 80%); size 136mm long by 99mm wide; package location
near middle point of lenght and one third of width.
PIN FUNCTIONS
Pin
1
Name
N.C.
Description
Not Connected.
2
Filter_cap
Brake Delay
-Thermal SD
Sense_in+
Sense_in-
Gnd
Filter capacitor for 10V internal regulator. The capacitor is optional.
Voice Coil Motor brake delay capacitor.
Pre Thermal Shut Down indication Output.
Non inverting Input of Sense Amplifier.
Inverting Input of Sense Amplifier.
Ground.
3
4
5
6
7
8
Err_out
Err-
Error Amplifier Output.
9
Inverting Input of Error Amplifier.
Output of Sense Amplifier.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Sense_out
N.C.
Not Connected.
Vin_out
Vin-
Output of Input Amplifier.
Inverting Input of Input Amplifier.
Non inverting Input of Input Amplifier.
Half Supply Voltage reference.
Vin+
+Vcc/2
+Motor start
-AE_W_Gate
+Vdd
Motor start Output to Spindle Controller.
Write Gate Output to AE.
+5V Supply.
+Vcc
+12V Supply.
-POR
Power On Reset. Low willsignal thefailure of thelogic supply or 12V supply
+5V Reference Output from the Voltage Reference Regulator.
Power On Reset Timing Capacitor. The capacitor sets the POR delay.
Not Connected.
+5V Ref
T_cap
N.C.
+5V Ref Gnd
+5Setpt
Ground for Voltage Reference Generator.
+5V Monitor Set Point and filtering
3/12
L6246
PIN FUNCTIONS (continued)
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
+12Setpt
Vbemf
Rpark
-W_Gate
+VCM park
-Spindle_start
+Enable
N.C.
Description
+12V Monitor Set Point and filtering
Input BEMF from spindle motor for parking circuit.
Resistor for setting the park voltage.
Write Gate Input.
External input for parking. High will activate the park procedure.
Spindle Start input.
Input. logic low will disable only the IC.
Not Connected.
Cpgnd
Gnd
Charge Pump Ground.
Ground.
Out+
Power Amplifier Output.
Vcc
+12V Power Supply.
C1
Charge Pump Oscillator Output.
Input for external Charge Pump Capacitor.
Output for Charge Pump Storage Capacitor.
+12V Power Supply.
C2
Vcp
Vcc
Out-
Power Amplifier Output.
Gnd
Ground.
Gate Drive
Gate Drive for External Isolation N-MOSFETS.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, Vdd = 5V, Vcc = 12V; unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vcc
Analog/Power supply voltage
range
10.8
12
13.2
V
Vdd
Idd
Idd
Icc
Digital supply voltage range
Digital supply quiescent current
Digital supply quiescent current
4.5
5
5
5.5
V
Output ENABLED
Output DISABLED
mA
mA
mA
mA
5
Power supply quiescent current Output ENABLED
Power supply quiescent current Output DISABLED
20
10
Icc
THERMAL SHUT DOWN DATA
Th_SD
Th_SD_H
Th_Warn
Shut down Temperature
Shut down hysteresys
135
115
160
25
°C
°C
°C
°C
Pre Shut down alarm
140
15
Pre Shut down alarm hysteresys
EXTERNAL N-MOSFET GATE DRIVER
Vll
Vhl
Low level voltage
500
mV
V
High level voltage
Vcc+4
4
Isink
Isource
Current sinking capability
Current source capability
mA
mA
0.5
POWER ON RESET AND GATE SPECIFICATION
Vdd_und_th
Vcc_und_th
POR_to
Digital undervoltage threshold
Power undervoltage threshold
POR timeout
3.8
8.5
4.1
9.25
500
4.45
10.0
625
1
V
V
Cpor = 1µF
375
ms
POR_delay
Time delay for POR Active
s
µ
Vdd_POR_T_R Power supply POR thereshold
Resistance
10
K
Ω
4/12
L6246
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VCC_POR_T_R Logic supply POR thereshold
Resistance
10
K
Ω
I_POR_O
POR output current drive
4
4.10
2
mA
LOGIC INTERFACE VOLTAGE LEVEL (All digital inputs are CMOS compatible)
Voh
Vol
Vih
Vil
CMOS high level output voltage Iout = 1.0mA
V
V
V
V
CMOS low level output voltage
TTL high level input voltage
TTL low level input voltage
Iout = 1.0mA
0.40
0.80
5V REFERENCE GENERATOR
Vref
Drift
loref
Voltage reference at Power On
4.75
-2
5.00
5.25
+2
V
%
Drift from Power On
Current output
10
mA
INPUT AMPLIFIER
Vi
Input voltage range
Vref (-)
0
Vref (+)
5.00
V
V
Vcm
Input common mode voltage
range
Vds
Vos
Ib
Input differential voltage swing
Input offset voltage
-5
-5
+5
+5
V
mV
nA
Input Bias current
-500
80
0.6
1
+500
Gv
Open Loop voltage Gain
Output slew rate
dB
SR
V/µs
MHz
dB
GBW
PSRR
Vo
Gain bandwidth product
Power supply rejection ratio
Output voltage swing
80
9
V
ERROR AMPLIFIER
Vi
Input voltage range
VCC/2
-0.5
VCC/2
+0.5
V
Vos
Ib
Input offset voltage
-5
-500
80
+5
mV
nA
dB
Input Bias current
+500
Gv
Open Loop voltage Gain
Output slew rate
SR
0.6
1
V/ s
µ
GBW
PSRR
Vo
Gain bandwidth product
Power supply rejection ratio
Output voltage swing
MHz
dB
V
80
VCC/2
-2Vbe
VCC/2
+2Vbe
SENSE AMPLIFIER
Vi
Vos
Ii
Input voltage range
Gnd
-6
Vcc
+6
V
mV
mA
dB
Input offset voltage
Input sink and source current
Power supply rejection ratio
Vloltage gain
-1.5
50
+1.5
PSRR
Gv
9.9
3
10
10.1
V/V
KΩ
MHz
V
Rin
GBW
Vli
Differential input resistance
Gain bandwidth product
1
Linear differential input voltage
range
Gv = 10(V/V)
-0.35
+0.55
CMRR
Common mode rejection ratio
56
dB
5/12
L6246
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
0.3
500
5
Unit
POWER AMPLIFIER
Rdson
Gdv
DMOS on resistance
Differential voltage gain
Output current leakage
Output slew rate
at 25°C
Ω
32
V/V
µA
Iol
SR
0.4
V/µs
µs
Tsr
Saturation recovery time
Gain bandwidth product
GBW
RETRACT
Vr
100
KHz
Max. retract voltage
Max. retract voltage
Vcc shorted to GND
Vcc Normal
300
1
mV
V
Vr
CHARGE PUMP
Cs
Vs
Cp
Storage capacitor
1
µF
V
Storage voltage
Pump capacitor
Vcc +4
0.2
µF
RETRACT TRUTH TABLE
Input
Input
Output
Output
-Retract
+Enable
Bridge Enable
+Retract
Brake and Retract
Run
0
1
1
X
1
0
0
1
0
1
0
0
Disable
BLOCK DESCRIPTION
POWER AMPLIFIERS
The open loop gain and bandwith of this amplifier
are similar to the senseamplifier.
The negative input and the output of the error am-
plifier are accessible externally in order to have
the current loop compensationuser configurable.
The two power amplifiers are connected in bridge
configurationworking in AB class.
The dynamic of the output is limited at +/- 2Vbe to
have a faster responseof the output voltage.
SENSE AMPLIFIER
This stage senses the voltage drop across the
Rsense.
The input stage is supplied by the charge pump
voltage to have an high dynamic, while the other
sections of the amplifier are supplied by the volt-
age of 10.5V internally regulated to have an high
power supply rejection (this voltage, supplies also
the error amplifier, the input amplifier and the op-
erational amplifier which generatesthe Vcc/2 volt-
age).
INPUT AMPLIFIER
The inputs and the output pins are externally ac-
cessible to have the possibility to configure the
transconductance gain of the current control loop
selecting the voltagegain of this amplifier.
The open loop gain and bandwith of this amplifier
are similar to the senseamplifier.
The open loop gain is around 80dB and the band-
with is more than 1MHz.
The voltage gain is fixed internallyat 10 V/V.
REFERENCE VOLTAGEGENERATOR
This block generates the two reference voltage
Vcc/2 and +5VREF.
The Vcc/2 voltage is used as reference by the
current control loop.
The +5VREF is a very stable voltage generator
that can be used as reference voltage of an exter-
nal DAC.
ERROR AMPLIFIER
This is the stage which compares the input volt-
age and the sense voltage, generating the control
voltage for the power section.
6/12
L6246
POWER SUPPLY MONITOR
Vr is the retract voltage for parking the heads
This circuit monitors the logic supply (5V) and the
power supply (12V) and activates the power on
reset output (POR) and the VCM PARK circuit.
After both logic and power supply reach their
nominal value a timing capacitor (T_CAP) has to
be charge before the POR output change from
low to high level.
Vbandgap is the internal bandgap reference
voltage of 1.4V
Rpark is value of the resistor connected at
RPARK pin
The parking circuit takes the power supply from
the spindle driver through the VBEMF pin, so that
in case of power fail the retract of the heads is
possible using the rectified BEMF voltage coming
from the spindle motor.
C V
I
POR delay=
where:
C is the capacitor value connected at pin
T_CAP
CHARGE PUMP
V is delta voltage that capacitor have to be
charged (2.3V)
The charge pump circuit is used as a means of al-
most doubling the power supply voltage (12V) in
order to drive the upper DMOS of the power
bridge.
I is the costant current charging the capacitor
µ
(4 A typ.)
The energy stored in the in the capacitor con-
nected at VCP pin is also used to drive the gate
of the externalN-MOSFET.
At the two input pins, +12 FILTER CAP and + 5
FILTER CAP, can be connected two capacitors
for filtering the noise on the power supply, avoid-
ing in this case undesired commutations of the
POR signal because of some fast negative spikes
on the line.
GATE DRIVER
This circuit provide the voltage driving the gate of
the external isolation N-MOSFET, and it is con-
trolledby the POR signal.
BRAKE AND PARKING CIRCUITS
The voice coil driver is switched into the parking
condition through the VCM PARK input or when
the POR signal is low. In such condition immedi-
ately the output stage turns on the two lower
DMOS of the power bridge to activate the BRAKE
of the voice coil motor.
After a delay generated by the capacitor at the
BRAKE DELAY pin, only one of the two lower
DMOS stays on while the opposite half bridge is
tristated.
THERMAL
The thermal protection circuit has two threshold,
the first if the pre shut down alarm that activates
the THERMAL SD signal and the second is the
shut down temperature that tristates the output
stage when the junction temperature increases
over this level.
APPLICATION INFORMATION
Example of calculation of the error amplifier com-
pansation for the stability of the current control
loop. As can be seen from the draw of the current
control loop circuit of the next page, the voltage
across the load is:
C V
I
BRAKE delay=
where:
C is the capacitor value connected at pin
BRAKE DELAY
#1
V is delta voltage that capacitor have to be
CPW
CERR
CINP
(A
CENSE
VIN - A
VL = A
sense = Rs IL
VL = ( ZL + Rs) IL
A
Vsense)
charged (3V)
V
I is the costant current charging the capacitor
(5µA typ.)
where AC... is the closed loop gain of Power, Er-
ror, Sense and Input Amplifier.
Changing in the #1 the transfer function between
the load current and the VIN is:
The parking voltage is then supplied by the
PARKING circuit connected to the output that has
been tristated.
The value of such a voltage is set by connecting
an external resistor between the RPARK pin and
ground.
#2
104
Vbandgap
V =
r
ACPW
I
ACERR ACINP
L
Rpark
=
VIN
ZL + RS + ACPW ACERR ACSENSE RS
where:
7/12
L6246
Typical Application Circuit
VDD
VOICE COIL
MOTOR
100nF
LL
RL
Rs 0.2
10nF
OUT_
SENSE_IN-
SENSE_IN+
OUT+
VDD
C1
C2
VCC
VCC
VCC
VCC
19
41
37
42
SENSE_OUT
10
ERR_OUT
8
6
5
36
18
38
39
1K
1M
1K
22µF
100nF
G
100nF
GATE DRV
S
P322
44
9
D
FROM SPINDLE
DRIVER
ERR-
1K
VBEMF
VCP
27
40
28
VIN_OUT
1µF
12
100nF
10K
51K
RPARK
10K
10K
VIN-
VCTL
VREF
13
14
5VREF
VIN+
21
24
5VREF
GND
L6246
5VREFGND
PQFP44
10K
(*)
(*)
12SEPT
5SSEPT
12SEPT
5SSEPT
VCC/2
26
25
22
3
VCC/2
15
34
CPGND
GND
7,35,43
1µF
1µF
AE W GATE
17
16
4
MOTOR START
THERMAL SHTD
POR
20
32
30
31
29
ENABLE
VCM PARK
FILTER_CAP
10.5V
INT.REG.
2
SPINDLE START
W GATE
(*)
D95IN268
FILTER CAPACITORS TO BE SET IN APPLICATION
Current Control Loop Circuit
VCC/2 + 10VSENSE
VCC/2 + (RA/RB) (ZC/RC) VIN-10 (ZC/R1) VSENSE
20K
ERROR
AMPL.
TO SENSE
AMPLIFIER
+
-
2K
VCC/2
-
+
-
VSENSE
+
R1
2K
20K
SENSE
AMPL.
16.5K
-
R2
R3
17.5K
ZC
C
1.1K
LL
LOAD
RS
RL
VCC/2
-
RA
VCC/2
+
+
-
+
1.1K
RC (=R1)
POWER
AMPL.
POWER
AMPL.
RB
RB
-
VL
VIN
+
VCC/2
INPUT
AMPL.
RA
VL=32 ( (ZC/RC) VIN - 10 (ZC/R1) VSENSE
)
VCC/2
VCC/2 - (RA-RB) VIN
= A
* A
( A
- A
* V
)
SENSE
CPW
CERR
CIMP * VIN
CSENSE
D95IN269B
8/12
L6246
1
If Now We Define:
and its pole is at frequency
2 π L
(RS + RL)
#3
RS
R + Z
so around 1KHz if L = 1.2mH.
Aloop = A
ACERR ACSENSE
CPW
S
L
So considering:
we obtain:
#4
CERR
CPW
dB A
Ax | dB = Aloop | dB
A
|
|
ACINP
ACSENSE RS
1 + Aloop
1
R
Aloop
S
dB+ ACSENSE | dB
+
IL
V
IN
dB
=
RS + RL
we have these Bode diagrams:
Atlowfrequencyis:
RS
R2
R1
Aloop = 32
10
(RS + ZL)
ACPW
30dB
S
L
if R2 = 1M, R1 = 1K, R = 0.2, R = 7
130KHz
then Aloop = 8889 = 80dB.
Being Aloop very high we can simplify the #4 in
this way:
ACSENSE
20dB
I
A
CINP
1
1
2
1
L
=
=
=
210KHz
VIN ACSENSE RS
10 0.2
For the stability we have to study the stability of
Aloop, that as we can see from the #3 is a multi-
plication, so in dB is a sum:
-31dB
Aloop |
= ACPW | dB+ACERR | dB+ACSENSE |
dB
dB
S
LOAD
AX
R
+
dB
+
RS ZL
19dB
So we can take in consideration the BODE dia-
grams of the each operational amplifier, with par-
ticular attentionto the Error amplifier.
1K
10K
100K
D95IN270A
1)The Power amplifier is actually composed by
two operational amplifiers in the way to have
a gain of +16 and -16 (in voltage) respec-
tevely, for a total of 32 = 30dB.
The point at -3dB is around 130KHz.
As can be easily see the bandwith is narrow and
the gain is low. It is possible to increase both
choosing an appropriate compensation of the Er-
ror amplifier.
2)The Sense amplifier has a gain of 20dB with
the point at -3dB around 210KHz.
The total bandwith should be, of course, at least a
decade lower of the 130KHz to avoid instability
problem. The bandwith guaranteed by the Error
amplifier has a Gmax of 80dB and a gain of 0dB
at 1MHz approximately, the real is some dB more
with a larger bandwith.
3)The load introduce an attenuationof:
R
S
20log
= -31dB with RS = 0.2 and RL = 7
RS + RL
9/12
L6246
As can be seen the choice of the pole influence
overall in fixing the gain at high frequency.
The gain at high frequency must be choosen in
order to not create instability problem, because
more higher is this gain and lower is the second
pole that we have at high frequency.
If this pole is taken close to the other that we
have already seen at 130KHz and 210KHz, insta-
bility problems can arise.
ERROR AMPL. GAIN
(dB)
OPEN LOOP GAIN
120
100
80
Adding together AX |
taine the Aloop:
and ACERR
|
we ob-
dB
dB
60
ACERR
(dB)
40
20
COMPENSATION AT 3Hz
COMPENSATION AT 100Hz
D95IN271
1
10
100
1K
10K
100K
1M
10M
60
40
20
Using the compensation network of the draw of
pag.8, we have a error amplifier transfer function
of:
AX(dB)
19
+
VO
VI
1
scR3
ZC
R1
R2
R1
= −
= −
1 + sc (R3 + R2)
ALOOP (dB)
so:
Gmax (DC) =
R2
R1
= 1000= 60dB
79
60
IS STABLE
IS NOT STABLE
Ω
Ω
with R1 = 1M and R2 = 1K
40
20
1
zero =
2 π R3C
D95IN273
10
100
1K
10K 100K
1M
10M
1
pole =
So the choice of the compensation network must
be done in order to fix at the beginning the Gmax
2 π (R3 + R2) C
R2
R1
Note: Fpole is lower than Fzero
of the error amplifier dependingon the ratio
.
The best choice is to cancel the pole of the load
(at around 1KHz) with the zero of the compensa-
tion.
To calculate the R3 and C values satisfying the
following system:
1
2 π L
1
=
2 π R3C RL + Rsense
ACERR (dB)
Error amplifier zero equal to load pole
120
DIFFERENTS
POLES
EXAMPLES
1
Admissible Bandwith
100
=
=
X
Gloop
2 π (R3 + R2)C
80
X
60
130KHz
10
8912
40
20
CLOSED LOOP
ACERR
=
=
1.5Hz
X
D95IN272
1
10
100
1K
10K 100K
1M
10M
This example is for crossing the 0dB one decade
before the first pole of the Power Amplifier
(130KHz), starting with a Gloop max of 79dB.
10/12
L6246
PQFP44 (10x10) PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
MIN.
MAX.
A
A1
A2
B
2.45
0.096
0.25
1.95
0.30
0.13
12.95
9.90
0.010
0.077
0.012
0.005
0.51
2.00
2.10
0.45
0.079
0.083
0.018
0.009
0.53
c
0.23
D
13.20
10.00
8.00
13.45
10.10
0.52
D1
D3
e
0.390
0.394
0.315
0.031
0.520
0.394
0.315
0.031
0.063
0.398
0.80
E
12.95
9.90
13.20
10.00
8.00
13.45
10.10
0.510
0.390
0.530
0.398
E1
E3
L
0.65
0.80
0.95
0.026
0.037
L1
K
1.60
0 (min.), 7 (max.)
°
°
D
D1
D3
A
A2
A1
23
33
22
34
0.10mm
.004
Seating Plane
44
12
11
1
C
e
K
PQFP44
11/12
L6246
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1998 SGS-THOMSON Microelectronics – Printedin Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12
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