L6398D
更新时间：2024-09-18 22:09:50
描述：High voltage high and low side driver
概述
数据手册L6398D 概述
High voltage high and low side driver
L6398D 数据手册
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High voltage high and low side driver
Features
■ High voltage rail up to 600 V
■ dV/dt immunity ±±0 V/ns in full temperature
range
■ Driver current capability:
– 290 mA source,
– 430 mA sink
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■ Switching times 7±/3± ns rise/fall with 1 nF load
■ 3.3 V, ± V TTL/CMOS input comparators with
hysteresis
Description
■ Integrated bootstrap diode
■ Fixed 320 ns dead-time
■ Interlocking function
The L6398 is a high-voltage device manufactured
with the BCD “OFF-LINE” technology. It is a single
chip half-bridge gate driver for N-channel power
MOSFET or IGBT.
■ Compact and simplified layout
■ Bill of material reduction
■ Flexible, easy and fast design
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
Applications
■ Motor driver for home appliances, factory
automation, industrial drives and fans.
Table 1.
Device summary
Order codes
Package
Packaging
L6398N
L6398D
DIP-8
SO-8
SO-8
Tube
Tube
L6398DTR
Tape and reel
April 2011
Doc ID 18199 Rev 3
1/16
www.st.com
16
Contents
L6398
Contents
1
2
3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
±.1
±.2
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
7
8
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.1
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10
2/16
Doc ID 18199 Rev 3
L6398
1
Block diagram
Block diagram
Figure 1.
Block diagram
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Doc ID 18199 Rev 3
3/16
Pin connection
L6398
2
Pin connection
Figure 2.
Pin connection (top view)
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Table 2.
Pin n #
Pin description
Pin name
Type
Function
1
2
3
4
±
6
7
8
LIN
HIN
I
Low side driver logic input (active low)
High side driver logic input (active high)
Lower section supply voltage
Ground
I
VCC
P
P
O
P
O
P
GND
LVG (1)
Low side driver output
OUT
High side (floating) common voltage
High side driver output
HVG (1)
BOOT
Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low.
4/16
Doc ID 18199 Rev 3
L6398
Truth table
3
Truth table
Table 3.
Truth table
Input
Output
LIN
HIN
LVG
HVG
H
L
L
H
L
L
L
L
L
L
H
L
L
H
H
H
Doc ID 18199 Rev 3
±/16
Electrical data
L6398
4
Electrical data
4.1
Absolute maximum ratings
Table 4.
Absolute maximum rating
Value
Symbol
Parameter
Unit
Min
Max
Vcc
Vout
Vboot
Vhvg
Vlvg
Vi
Supply voltage
-0.3
Vboot - 21
-0.3
21
Vboot + 0.3
620
V
V
Output voltage
Bootstrap voltage
V
High side gate output voltage
Low side gate output voltage
Logic input voltage
Vout - 0.3
-0.3
Vboot + 0.3
Vcc + 0.3
1±
V
V
-0.3
V
dVout/dt Allowed output slew rate
±0
V/ns
mW
°C
°C
Ptot
TJ
Total power dissipation (TA = 2± °C)
800
Junction temperature
Storage temperature
1±0
Tstg
-±0
1±0
Note:
ESD immunity for pins 6, 7 and 8 is guaranteed up to 1 kV (human body model)
4.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Thermal resistance junction to ambient
SO-8
DIP-8
Unit
Rth(JA)
1±0
100
°C/W
4.3
Recommended operating conditions
Table 6.
Symbol
Recommended operating conditions
Pin
Parameter
Supply voltage
Test condition
Min
Max
Unit
Vcc
3
8-6
6
10
9.8
20
20
V
V
(1)
VBO
Floating supply voltage
Output voltage
Vout
fsw
TJ
- 11 (2)
±80
800
12±
V
Switching frequency
Junction temperature
HVG, LVG load CL = 1 nF
kHz
°C
-40
1. VBO = Vboot - Vout
2. LVG off. Vcc = 10 V
Logic is operational if Vboot > ± V
6/16
Doc ID 18199 Rev 3
L6398
Electrical characteristics
5
Electrical characteristics
5.1
AC operation
Table 7.
Symbol
AC operation electrical characteristics (V = 15 V; T = +25 °C)
CC J
Pin
Parameter
Test condition
Min Typ Max Unit
High/low side driver turn-on Vout = 0 V
ton
±0 12± 200 ns
propagation delay
1, 2
vs
Vboot = Vcc
CL = 1 nF
High/low side driver turn-off
propagation delay
±, 7
VIN = 0 to 3.3 V
toff
±0 12± 200 ns
See Figure 3
DT
tr
Dead time (1)
Rise time
Fall time
CL = 1 nF
CL = 1 nF
CL = 1 nF
22± 320 41± ns
7± 120 ns
±, 7
tf
3±
70
ns
1. See Figure 4 on page 9.
Figure 3.
Timing
50%
50%
LIN
tr
tf
90%
90%
10%
10%
LVG
ton
toff
50%
50%
HIN
tr
tf
90%
90%
10%
10%
HVG
ton
toff
Doc ID 18199 Rev 3
7/16
Electrical characteristics
L6398
Unit
5.2
DC operation
Table 8.
Symbol
DC operation electrical characteristics (V = 15 V; T = + 25 °C)
CC J
Pin
Parameter
Test condition
Min
Typ
Max
Vcc_hys
Vcc_thON
Vcc_thOFF
Vcc UV hysteresis
1.2
9
1.±
9.±
8
1.8
10
V
V
V
Vcc UV turn ON threshold
Vcc UV turn OFF threshold
7.6
8.4
3
Vcc = 7 V
Undervoltage quiescent
supply current
Iqccu
90
1±0
440
μA
μA
LIN = ± V; HIN = GND;
Vcc = 1± V
Iqcc
Quiescent current
380
LIN = ± V; HIN = GND;
Bootstrapped supply voltage section (1)
VBO_hys
VBO_thON
VBO_thOFF
VBO UV hysteresis
0.8
8.2
7.3
1
9
8
1.2
9.8
8.7
V
V
V
VBO UV turn ON threshold
VBO UV turn OFF threshold
8
Undervoltage VBO quiescent
current
IQBOU
VBO = 7 V, LIN = HIN = ±V
VBO = 1± V, LIN = HIN = ±V
30
60
μA
IQBO
ILK
VBO quiescent current
190
240
10
μA
μA
High voltage leakage current Vhvg = Vout = Vboot = 600 V
Bootstrap driver on resistance
RDS(on)
LVG ON
120
Ω
(2)
Driving buffers section
High/low side source short
circuit current
Iso
VIN = Vih (tp < 10 μs)
VIN = Vil (tp < 10 μs)
200
2±0
290
430
mA
mA
±,
7
High/low side sink short
circuit current
Isi
Logic inputs
Vil
Low logic level voltage
High logic level voltage
0.8
V
V
1, 2
1, 2
Vih
2.2±
110
3
LIN and HIN connected
together and floating
Vil_S
IHINh
IHINl
Single input voltage
0.8
260
1
V
HIN logic “1” input bias
current
HIN = 1± V
HIN = 0 V
17±
6
μA
μA
2
1
HIN logic “0” input bias
current
ILINl
LIN logic “0” input bias current LIN = 0 V
LIN logic “1” input bias current LIN = 1± V
20
1
μA
μA
ILINh
1. VBO = Vboot - Vout
2. RDSON is tested in the following way: RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
.
8/16
Doc ID 18199 Rev 3
L6398
Waveforms definitions
6
Waveforms definitions
Figure 4.
Dead time and interlocking waveforms definitions
LIN
HIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
LVG
HVG
DTHL
DTLH
DTLH
DTLH
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
LVG
HVG
DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
LVG
HVG
DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
LVG
HVG
DTLH
DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
Doc ID 18199 Rev 3
9/16
Typical application diagram
L6398
7
Typical application diagram
Figure 5.
Application diagram
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10/16
Doc ID 18199 Rev 3
L6398
Bootstrap driver
8
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 6). In the L6398 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in
Figure 7. An internal charge pump (Figure 7) provides the DMOS driving voltage.
8.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Qgate
CEXT = -------------
Vgate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
Equation 2
C
>>> C
EXT
BOOT
e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 190 μA, so if HVG TON is ± ms, CBOOT has
to supply 1 μC to CEXT. This charge on a 1 μF capacitor means a voltage drop of 1V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
Qgate
------------------
Rdson
Vdrop = IchargeRdson → Vdrop
=
Tcharge
Doc ID 18199 Rev 3
11/16
Bootstrap driver
L6398
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap
DMOS is about 1 V, if the Tcharge is ± μs. In fact:
Equation 4
30nC
±μs
--------------
⋅ 120Ω ∼ 0.7V
Vdrop
=
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 6.
Bootstrap driver with high voltage fast recovery diode
DBOOT
VCC
BOOT
H.V.
HVG
LVG
CBOOT
OUT
TO LOAD
Figure 7.
Bootstrap driver with internal charge pump
BOOT
VCC
H.V.
HVG
CBOOT
OUT
TO LOAD
LVG
12/16
Doc ID 18199 Rev 3
L6398
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Table 9.
Dim.
DIP-8 mechanical data
mm.
inch
Min
Typ
Max
Min
Typ
Max
A
3.32
0.131
a1
B
0.±1
1.1±
0.020
0.04±
0.014
0.008
1.6±
0.±±
0.06±
0.022
0.012
0.430
0.384
b
0.3±6
0.204
b1
D
E
0.304
10.92
9.7±
7.9±
0.313
e
2.±4
7.62
7.62
0.100
0.300
0.300
e3
e4
F
6.6
0.260
0.200
0.1±0
0.060
I
±.08
3.81
1.±2
L
3.18
0.12±
Z
Figure 8.
Package dimensions
Doc ID 18199 Rev 3
13/16
Package mechanical data
L6398
Table 1. SO-8 mechanical data
mm.
inch
Typ
Dim.
Min
Typ
Max
Min
Max
A
1.3±
1.7±
0.0±3
0.069
A1
A2
B
0.10
1.10
0.33
0.19
4.80
0.2±
1.6±
0.±1
0.2±
±.00
0.004
0.043
0.013
0.007
0.189
0.010
0.06±
0.020
0.010
0.197
C
(1)
D
E
e
3.80
4.00
0.1±
0.1±7
1.27
0.0±0
H
±.80
0.2±
0.40
6.20
0.±0
1.27
0.228
0.010
0.016
0.244
0.020
0.0±0
h
L
k
0° (min.), 8° (max.)
0.10
ddd
0.004
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.1±mm (.006inch) in total (both side).
Figure 9. Package dimensions
14/16
Doc ID 18199 Rev 3
L6398
Revision history
10
Revision history
Table 10. Document revision history
Date
Revision
Changes
14-Dec-2010
16-Feb-2011
01-Apr-2011
1
2
3
First release.
Updated Table 8.
Typo in coverpage
Doc ID 18199 Rev 3
1±/16
L6398
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16/16
Doc ID 18199 Rev 3
L6398D CAD模型
引脚图
封装焊盘图
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