L6482HTR [STMICROELECTRONICS]
cSPINâ¢: microstepping motor controller with motion engine and SPI; cSPINâ ?? ¢ ：微步进电机控制器与运动引擎和SPI
| 型号： | L6482HTR |
| 厂家： | 
ST |
| 描述： | cSPINâ¢: microstepping motor controller with motion engine and SPI |
| 文件： | 总73页 (文件大小：1012K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6482
cSPIN™: microstepping motor controller
with motion engine and SPI
Datasheet − production data
Features
■ Operating voltage: 7.5 V - 85 V
■ Dual full-bridge gate driver for N-channel
MOSFETs
■ Fully programmable gate driving
■ Embedded Miller clamp function
■ Programmable speed profile
■ Up to 1/16 microstepping
HTSSOP38
non-dissipative overcurrent protection. Thanks to
■ Advanced current control with auto-adaptive
a new current control, a 1/16 microstepping is
achieved through an adaptive decay mode which
outperforms traditional implementations. The
digital control core can generate user defined
motion profiles with acceleration, deceleration,
speed or target position easily programmed
through a dedicated register set. All application
commands and data registers, including those
used to set analog values (i.e. current protection
trip point, deadtime, PWM frequency, etc.) are
sent through a standard 5-Mbit/s SPI. A very rich
set of protections (thermal, low bus voltage,
overcurrent and motor stall) make the L6482
“bullet proof”, as required by the most demanding
motor control applications.
decay mode
■ Integrated voltage regulators
■ SPI interface
■ Low quiescent standby currents
■ Programmable non-dissipative overcurrent
protection
■ Overtemperature protection
Applications
■ Bipolar stepper motor
Description
The L6482, realized in analog mixed signal
technology, is an advanced fully integrated
solution suitable for driving two-phase bipolar
stepper motors with microstepping.
It integrates a dual full-bridge gate driver for N-
channel MOSFET power stages with embedded
Table 1.
Device summary
Order code
Package
Packaging
L6482H
HTSSOP38
HTSSOP38
Tube
L6482HTR
Tape and reel
December 2012
Doc ID 023768 Rev 2
1/73
This is information on a product in full production.
www.st.com
73
Contents
L6482
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
6
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
6.2
6.3
6.4
Device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1
Automatic Full-step and Boost modes . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
6.6
Absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Programmable speed profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6.1
Infinite acceleration/deceleration mode . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7
Motor control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
Constant speed commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Positioning commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Motion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Stop commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Step-clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
GoUntil and ReleaseSW commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.8
Internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8.1
6.8.2
Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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6.9
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.10 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11 VS undervoltage lockout (UVLO_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.12 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.13 Reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.14 External switch (SW pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.15 Programmable gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.16 Deadtime and blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.17 Integrated analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.18 Supply management and internal voltage regulators . . . . . . . . . . . . . . . . 33
6.19 BUSY/SYNC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.20 FLAG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Phase current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1
7.2
7.3
7.4
Predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 38
Torque regulation (output current amplitude regulation) . . . . . . . . . . . . . . 39
8
9
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
Register and flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
ABS_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
EL_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MAX_SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MIN_SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FS_SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.10 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC . . . . . . . . . . . . 47
9.1.11 T_FAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1.12 TON_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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9.1.13 TOFF_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1.14 ADC_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1.15 OCD_TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1.16 STEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1.17 ALARM_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1.18 GATECFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1.19 GATECFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1.20 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.1.21 STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2
Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
Command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SetParam (PARAM, VALUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
GetParam (PARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Run (DIR, SPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
StepClock (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Move (DIR, N_STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
GoTo (ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
GoTo_DIR (DIR, ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.10 GoUntil (ACT, DIR, SPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.11 ReleaseSW (ACT, DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.12 GoHome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.13 GoMark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.14 ResetPos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.15 ResetDevice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.16 SoftStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.17 HardStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.18 SoftHiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.19 HardHiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.20 GetStatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10
11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical application values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CL values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UVLO thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal protection summarizing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
EL_POS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MIN_SPEED register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FS_SPD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers . 48
FS_SPD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Minimum on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Minimum off-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ADC_OUT value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STEP_MODE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SYNC output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SYNC signal source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ALARM_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
GATECFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
IGATE parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TCC parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TBOOST parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GATECFG2 register (voltage mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TDT parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TBLANK parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CONFIG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Oscillator management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
External switch HardStop interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Overcurrent event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Programmable VCC regulator output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Programmable UVLO thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
External torque regulation enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Motor supply voltage compensation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STATUS register TH_STATUS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STATUS register DIR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STATUS register MOT_STATE bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Doc ID 023768 Rev 2
5/73
List of tables
L6482
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
SetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
GetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Run command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
StepClock command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Move command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
GoTo command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
GoTo_DIR command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
GoUntil command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ReleaseSW command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
GoHome command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
GoMark command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ResetPos command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ResetDevice command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SoftStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HardStop command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SoftHiZ command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HardHiZ command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
GetStatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HTSSOP38 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6/73
Doc ID 023768 Rev 2
L6482
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Normal mode and microstepping (16 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Automatic Full-step switching in Normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Automatic Full-step switching in Boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Speed profile in infinite acceleration/deceleration mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Constant speed command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Positioning command examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Motion command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. OSCIN and OSCOUT pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. Overcurrent detection-principle scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. External switch connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. Gate driving currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Device supply pin management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. Predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Non-predictive current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Adaptive decay - fast decay tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. Adaptive decay - switch from normal to slow+fast decay mode and vice versa. . . . . . . . . 38
Figure 21. Fast decay tuning during the falling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Current sensing and reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. SPI timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. Daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. Command with 3-byte argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 26. Command with 3-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 27. Command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 28. HTSSOP38 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. HTSSOP38 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Doc ID 023768 Rev 2
7/73
Block diagram
L6482
1
Block diagram
Figure 1.
Block diagram
VSREG
VCC
VCC REG
VREG
CP
VBOOT
VS
Charge
pump
VCC
VREG
Voltage reg.
Voltage reg.
Vboot
HVGA1
VCC
Temperature
sensing
ADC
ADCIN
OUTA1
LVGA1
Vboot
Vdd
VDD
HVGA2
OUTA2
LVGA2
VCC
CS
CK
SDO
SDI
CORE
LOGIC
VSENSEA
Vboot
Vboot
HVB1
STBY/RESET
VCC
VCC
Current
sensing
OUTB1
LVGB1
FLAG
BUSY/SYNC
HVGB2
OUTB2
16 MHz
Oscillator
STCK
SW
LVGB2
Ext. Osc. driver
&
Clock gen.
VSENSEB
DGND
PGND
AGND
OSCIN
OSCOUT
AM15031v1
8/73
Doc ID 023768 Rev 2
L6482
Electrical data
2
Electrical data
2.1
Absolute maximum ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Test condition
Value
Unit
VDD
VREG
VS
Logic interface supply voltage
Logic supply voltage
5.5
3.6
95
V
Motor supply voltage
V
V
V
V
Low-side gate driver supply
voltage
VCC
18
100
VBOOT
ΔVBOOT
Boot voltage
High-side gate driver supply
voltage
0 to 20
Internal VCC regulator supply
voltage
VSREG
95
18
V
V
V
Internal VREG regulator
supply voltage
VCCREG
-5 to
VBOOT
VOUT1A
VOUT2A
VOUT1B
VOUT2B
DC
AC
Full-bridge output voltage
-15 to
VBOOT
Full-bridge output slew rate
(10% - 90%)
SRout
10
V/ns
V
VHVG1A
VHVG2A High-side output driver
VHVG1B voltage
VHVG2B
VOUT to
VBOOT
ΔVHVG1A
High-side output driver to
ΔVHVG2A
respective bridge output
15
V
V
ΔVHVG1B
voltage(VHVG - VOUT
)
ΔVHVG2B
VLVG1A
VLVG2A
VLVG1B
VLVG2B
Low-side output driver voltage
VCC + 0.3
IGATE-
High-side gate voltage clamp
current capability
100
mA
V
CLAMP
Integrated ADC input voltage
range (ADCIN pin)
VADCIN
-0.3 to 3.6
Differential voltage between
VBOOT, VS, OUT1A, OUT2A,
PGND and VBOOT, VS,
Vout_diff
100
V
OUT1B, OUT2B, PGND pins
Doc ID 023768 Rev 2
9/73
Electrical data
Table 2.
L6482
Absolute maximum ratings (continued)
Symbol
Parameter
Test condition
Value
Unit
Vin
Logic inputs voltage range
-0.3 to 5.5
V
Storage and operating
junction temperature
Ts TOP
Ptot
-40 to 150 °C
Total power dissipation (Tamb
= 25 ºC)
(1)
4
W
2
1. HTSSOP38 mounted on a four-layer FR4 PCB with a dissipating copper surface of about 30 cm .
2.2
Recommended operating conditions
Table 3.
Symbol
Recommended operating conditions
Parameter
Test condition
Min.
Typ. Max. Unit
3.3 V logic outputs
5 V logic outputs
3.3
VDD
Logic interface supply voltage
V
5
VREG
VS
Logic supply voltage
Motor supply voltage
3.3
V
V
VSREG
VCC +3
85
Vs
VCC voltage internally
generated
VSREG Internal VCC voltage regulator
V
V
V
CC voltage imposed by
external source (VSREG
= VCC
VCC
Gate driver supply voltage
7.5
15
)
Internal VREG voltage regulator VREG voltage internally
VCCREG
6.3
0
VCC
V
V
supply voltage
generated
Integrated ADC input voltage
(ADCIN pin)
VADC
VREG
2.3
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Thermal resistance junction-to-ambient
Package
Typ.
Unit
Rthj-a
HTSSOP38(1)
31
°C/W
2
1. HTSSOP38 mounted on a four-layer FR4 PCB with a dissipating copper surface of about 30 cm .
10/73
Doc ID 023768 Rev 2
L6482
Electrical characteristics
3
Electrical characteristics
VS = 48 V; VCC = 7.5 V; Tj = 25 °C, unless otherwise specified.
Table 5.
Electrical characteristics
Symbol
General
VCCthOn
Parameter
Test condition
Min.
Typ.
Max. Unit
UVLO_VAL set high(1) 9.9
UVLO_VAL set low(1)
6.5
UVLO_VAL set high(1) 9.5
UVLO_VAL set low(1)
5.9
UVLO_VAL set high(1) 8.6
UVLO_VAL set low(1)
5.7
UVLO_VAL set high(1) 8.2
10.4
6.9
10
10.9
7.3
V
V
V
V
V
V
V
V
V
V
VCC UVLO turn-on threshold
VCC UVLO turn-off threshold
10.5
6.7
VCCthOff
6.3
9.2
6
9.8
ΔVBOOTthOn VBOOT - VS UVLO turn-on threshold
ΔVBOOTthOff VBOOT - VS UVLO turn-off threshold
6.3
8.8
5.5
3
9.5
UVLO_VAL set low(1)
5.3
2.8
2.2
5.8
(1)
VREGthOn
VREGthOff
VREG turn-on threshold
VREG turn-off threshold
3.18
2.5
(1)
2.4
Undervoltage VSREG quiescent supply
current
IVSREGqu
VCCREG= VREG< 2.2 V
40
μA
VCCREG= VREG< 3.3 V,
IVSREGq
IVSREGq
Quiescent VSREG supply current
Quiescent VSREG supply current
internal oscillator
3.8
6.5
mA
mA
selected(1)
VCCREG = VREG = 15V
Thermal protection
Tj(WRN)Set Thermal warning temperature
135
125
155
°C
°C
°C
Tj(WRN)Rec Thermal warning recovery temperature
Tj(OFF)Set
Tj(OFF)Rec
Tj(SD)Set
Thermal bridge shutdown temperature
Thermal bridge shutdown recovery
temperature
145
170
130
°C
°C
°C
Thermal device shutdown temperature
Thermal device shutdown recovery
temperature
Tj(SD)Rec
Charge pump
Vpump
Voltage swing for charge pump oscillator
VCC
660
V
fpump,min
Minimum charge pump oscillator frequency(2)
kHz
Maximum charge pump oscillator
frequency(2)
fpump,max
RpumpHS
800
10
kHz
Charge pump high-side RDS(on) resistance
Ω
Doc ID 023768 Rev 2
11/73
Electrical characteristics
L6482
Table 5.
Symbol
RpumpLS
Iboot
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max. Unit
Charge pump low-side RDS(ON) resistance
Average boot current
10
Ω
2.6
mA
Gate driver outputs
2.4
5.4
11.3
17.3
23.2
50.2
81
4
5.6
8
10.6
20.7
30.7 mA
40.8
77.8
113
16
24
32
64
96
4
VS = 38 V
VHVGX - VOUTX > 3 V
LVGX > 3 V
Programmable high-side and low-side gate
sink current
IGATE,Sink
V
2.8
5.8
12
5.2
8
10.2
20
VS = 38 V
16
24
32
64
96
Programmable high-side and low-side gate
source current
VBOOTX - VHVGX > 3.5
V
IGATE,Source
18
30
40
mA
24
VCC-VLVGX > 3.5 V
51
77
82
112
High-side and low-side turn-off overboost
gate current
IOB
85
103
117 mA
RCLAMP(LS) Low-side gate driver Miller clamp resistance
RCLAMP(HS) High-side gate driver Miller clamp resistance
VGATE-CLAMP High-side gate voltage clamp
6.5
3
10
10
Ω
Ω
v
IGATE-CLAMP=100 mA
TCC=’00000’
16.7
125
3750
tcc
tOB
IDSS
tr
Programmable constant gate current time(2)
ns
ns
TCC= 11111
TBOOST=’001’,
internal oscillator
62.5
Programmable. Turn-off overboost; gate
current time(2)
TBOOST=’111’
OUT = VS
1000
100
μA
μA
Leakage current
Rise time
OUT = GND
-100
IGATE = 96 mA
VCC = 15 V
2.5
2.5
μs
μs
CGATE = 15 nF
I
GATE = 96 mA
VCC = 15 V
GATE = 15 nF
tf
Fall time
C
12/73
Doc ID 023768 Rev 2
L6482
Electrical characteristics
Table 5.
Electrical characteristics (continued)
Parameter
Symbol
Test condition
IGATE= 96 mA
VCC = 15 V
GATE = 15 nF
Min.
Typ.
Max. Unit
SRgate
Gate driver output slew rate
6
V/μs
C
Deadtime and blanking
TDT= '00000'
TDT=’11111’
TBLANK= '000'
TBLANK=’111’
125
4000
125
tDT
Programmable deadtime(2)
ns
ns
tblank
Programmable blanking time(2)
1000
Logic
VIL
VIH
IIH
Low level logic input voltage
High level logic input voltage
High level logic input current
Low level logic input current
0.8
1
V
V
2
VIN = 5 V, VDDIO = 5 V
µA
µA
IIL
VIN = 0 V, VDDIO = 5 V -1
VDD = 3.3 V, IOL = 4
mA
0.3
0.3
VOL
Low level logic output voltage(3)
V
V
V
DD = 5 V, IOL = 4 mA
DD = 3.3 V, IOH = 4
V
2.4
mA
VOH
High level logic output voltage
VDD = 5 V, IOH = 4 mA 4.7
RPUCS
RPDRST
RPUSW
CS pull-up resistor
430
450
80
STBY/RESET pull-down resistor
SW pull-up resistor
kΩ
thigh,STCK
tlow,STCK
Step-clock input high time
Step-clock input low time
300
300
ns
ns
Internal oscillator and external oscillator driver
fosc,int
fosc,ext
Internal oscillator frequency
Tj = 25 °C,
-5%
8
16
+5% MHz
32 MHz
V
Programmable external oscillator frequency
VOSCOUTH OSCOUT clock source high level voltage
VOSCOUTL OSCOUT clock source low level voltage
Internal oscillator
Internal oscillator
2.4
0.3
10
V
trOSCOUT
OSCOUT clock source rise and fall time
tfOSCOUT
Internal oscillator
Internal oscillator
ns
thigh
OSCOUT clock source high time
62.5
3
ns
textosc
tintosc
Internal to external oscillator switching delay
External to internal oscillator switching delay
ms
µs
100
Doc ID 023768 Rev 2
13/73
Electrical characteristics
L6482
Table 5.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max. Unit
SPI
fCK,MAX
trCK
tfCK
thCK
tlCK
tsetCS
tholCS
Maximum SPI clock frequency(4)
SPI clock rise and fall time(4)
5
MHz
1
µs
ns
SPI clock high and low time(4)
90
Chip select setup time(4)
Chip select hold time (4)
Deselect time(4)
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
tdisCS
625
20
tsetSDI
tholSDI
tenSDO
tdisSDO
tvSDO
Data input setup time(4)
Data input hold time(4)
Data output enable time(4)
Data output disable time(4)
Data output valid time(4)
Data output hold time(4)
30
95
95
35
tholSDO
0
Current control
VREF, max Maximum reference voltage
VREF, min Minimum reference voltage
Overcurrent protection
1000
7.8
mV
mV
OCD_TH = ‘11111’
OCD_TH = ‘00000’
OCD_TH = ‘01001’
OCD_TH = ‘10011’
800
27
1000
31
1100 mV
35 mV
Programmable overcurrent detection voltage
DS threshold
VOCD
V
270
500
312.5
625
100
230
344 mV
688 mV
tOCD,Comp OCD comparator delay
200
530
ns
ns
tOCD,Flag
OCD to flag signal delay time
OCD_TH = '11111'
tOCD,SD
OCD to shutdown delay time
400
630
ns
OCD event to 90% of
gate voltage
Standby
VCC = VCCREG = 7.5 V
42
VSREG = 48 V
ISTBY
Standby mode supply current (VSREG pin)
µA
VCC = VCCREG = 7.5
V VSREG = 18 V
37.5
ISTBY,vreg
tSTBY,min
tlogicwu
Standby mode supply current (VREG pin)
Minimum standby time
6
µA
ms
µs
0.5
500
Logic power-on and wake-up time
14/73
Doc ID 023768 Rev 2
L6482
Electrical characteristics
Table 5.
Electrical characteristics (continued)
Parameter
Symbol
Test condition
Power bridges
Min.
Typ.
Max. Unit
disabled,
tcpwu
Charge pump power-on and wake-up time
1
ms
Cp = 10 nF, Cboot = 220
nF, VCC=15 V
Internal voltage regulators
Low (default), ICC = 10
mA
7.3
4
7.5
15
V
VCCOUT
Internal VCC voltage regulator output voltage
High, ICC = 10 mA
ICC = 50 mA
VCCREG, drop VSREG to VCC dropout voltage
3
V
Internal VCC voltage regulator power
dissipation
PCC
2.5
W
Internal VREG voltage regulator output
3.13
5
VREGOUT
voltage
IREG = 10 mA
IREG = 50 mA
3.3
V
V
VSREG, drop VCCREG to VREG dropout voltage
3
Internal VREG voltage regulator output
VREG pin shorted to
ground
IREGOUT
current
125
55
mA
IREGOUT,STB Internal VREG voltage regulator output
VREG pin shorted to
ground
mA
W
standby current
Y
Internal VREG voltage regulator power
dissipation
PREG
0.5
Integrated analog-to-digital converter
NADC
Analog-to-digital converter resolution
5
bit
V
VADC,ref
Analog-to-digital converter reference voltage
3.3
Analog-to-digital converter sampling
frequency
(2)
fS
fOSC/512
1.16
kHz
V
VADC,UVLO ADCIN UVLO threshold
1.05
1.35
1. Guaranteed in the temperature range -25 to 125 °C.
2. The value accuracy is dependent on oscillator frequency accuracy (Section 6.8).
3. FLAG and BUSY open drain outputs included.
4. See Figure 23.
Doc ID 023768 Rev 2
15/73
Pin connection
L6482
4
Pin connection
Figure 2.
Pin connection (top view)
LVGA1 1
38
LVGA2
OUTA2
2
3
37
OUTA1
HVGA1
NC
36 HVGA2
35 SENSEA
34
EPAD
4
5
ADCIN
VS
STBY/RESET
SW
6
33
32
31
30
7
VBOOT
PGND
CP
STCK
8
FLAG
9
BUSY/SYNC
10
11
29 DGND
28 SDO
VCC
VCCREG
VSREG 12
VREG 13
27 VDDIO
26
25
24
23
SDI
CK
14
OSCIN
OSCOUT15
AGND
CS
16
SENSEB
HVGB1 17
22 HVGB2
OUTB118
21
20
OUTB2
LVGB2
LVGB1
19
AM15032v1
4.1
Pin list
Table 6.
No.
Pin description
Name
Type
Function
11
13
27
12
10
VCCREG
VREG
VDD
Power supply
Power supply
Power supply
Power supply
Power supply
Internal VREG voltage regulator supply voltage
Logic supply voltage
Logic interface supply voltage
VSREG
VCC
Internal VCC voltage regulator supply voltage
Gate driver supply voltage
Oscillator pin1. To connect an external oscillator or
clock source
14
15
OSCIN
Analog input
Oscillator pin2. To connect an external oscillator.
When the internal oscillator is used, this pin can
supply a 2/4/8/16 MHz clock
OSCOUT
Analog output
9
7
CP
Output
Charge pump oscillator output
Bootstrap voltage needed for driving the high-side
power DMOS of both bridges (A and B)
VBOOT
Power supply
5
6
3
ADCIN
VS
Analog input
Power supply
Power output
Internal analog-to-digital converter input
Motor voltage
HVGA1
High-side half-bridge A1 gate driver output
16/73
Doc ID 023768 Rev 2
L6482
Pin connection
Table 6.
No.
Pin description (continued)
Name
Type
Function
36
17
22
1
HVGA2
HVGB1
HVGB2
LVGA1
LVGA2
LVGB1
LVGB2
Power output
Power output
Power output
Power output
Power output
Power output
Power output
High-side half-bridge A2 gate driver output
High-side half-bridge B1 gate driver output
High-side half-bridge B2 gate driver output
Low-side half-bridge A1 gate driver output
Low-side half-bridge A2 gate driver output
Low-side half-bridge B1 gate driver output
Low-side half-bridge B2 gate driver output
38
19
20
Power ground pins. They must be connected to other
ground pins
8
PGND
Ground
35
23
2
SENSEA
SENSEB
OUTA1
Analog input
Analog input
Power input
Power input
Power input
Power input
Phase A current sensing input
Phase B current sensing input
Full-bridge A output 1
37
18
21
OUTA2
Full-bridge A output 2
OUTB1
OUTB2
Full-bridge B output 1
Full-bridge B output 2
Analog ground. It must be connected to other ground
pins
16
33
29
AGND
SW
Ground
Logical input
Ground
External switch input pin
Digital ground. It must be connected to other ground
pins
DGND
28
26
25
24
SDO
SDI
CK
Logical output
Logical input
Logical input
Logical input
Data output pin for serial interface
Data input pin for serial interface
Serial interface clock
CS
Chip select input pin for serial interface
By default, the BUSY / SYNC pin is forced low when
the device is performing a command.
30
BUSY/SYNC Open drain output
The pin can be programmed in order to generate a
synchronization signal
Status flag pin. An internal open drain transistor can
pull the pin to GND when a programmed alarm
31
34
FLAG
Open drain output condition occurs (step loss, OCD, thermal pre-warning
or shutdown, UVLO, wrong command, non-
performable command)
Standby and reset pin. LOW logic level puts the device
STBY
in Standby mode and reset logic.
Logical input
Logical input
RESET
If not used, it should be connected to VREG
32
STCK
Step-clock input
Exposed pad. It must be connected to other ground
pins
EPAD
Exposed pad Ground
Doc ID 023768 Rev 2
17/73
Typical applications
L6482
5
Typical applications
Table 7.
Typical application values
Name
CVSPOL
CVS
CBOOT
CFLY
CVSREG
CVCC
CVCCREG
CVREG
CVREGPOL
CVDD
Value
220 µF
220 nF
470 nF
47 nF
100 nF
470 nF
100 nF
100 nF
22 µF
100 nF
D1
Charge pump diodes
Q1,Q2,Q3,Q4,Q5,Q6,Q7
,Q8
STD25NF10
RPU
39 kΩ
RSENSE
0.2 Ω (maximum phase current 5 A)
Figure 3.
Typical application schematic
S
V
(10.5V - 85V )
C
C
C
BOOT
VS
VSPOL
D1
C
VREGPOL
C
C
R
C
C
C
VSREG
VREG
VDD
VCC
Analog signal
C
VCCREG
FLY
R
PU
VCCREG
VCC VSREG
VS CP VBOOT
ADCIN
VREG
VDD
PU
Q1
Q2
FLAG
HVGA1
OUTA1
L VGA1
BUSY/SYNC
STBY/RESET
STCK
R
SENSE
LVGA2
OUTA2
HVGA2
HOST
CS
Q3
Q4
Q6
SENSEA
CK
Motor
SDO
SDI
L6482
Q5
HVGB1
OUTB1
LVGB1
SW
R
SENSE
LVGB2
OUTB2
OSCIN
OSCOUT
HVGB2
Q7
Q8
SENSEB
DGND AGND PGND
AM15033v1
18/73
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L6482
Functional description
6
Functional description
6.1
Device power-up
During power-up, the device is under reset (all logic IOs disabled and power bridges in high
impedance state) until the following conditions are satisfied:
●
●
●
●
●
VCC is greater than VCCthOn
VBOOT - VS is greater than ΔVBOOTthOn
VREG is greater than VREGthOn
Internal oscillator is operative
STBY/RESET input is forced high.
After power-up, the device state is the following:
●
Parameters are set to default
●
Internal logic is driven by internal oscillator and a 2-MHz clock is provided by the
OSCOUT pin
●
Bridges are disabled (high impedance).
After power-up, a period of tlogicwu must pass before applying a command to allow proper
oscillator and logic startup.
Any movement command makes the device exit from High Z state (HardStop and SoftStop
included).
6.2
Logic I/O
Pins CS, CK, SDI, STCK, SW and STBY/RESET are TTL/CMOS 3.3 V-5 V compatible logic
inputs.
Pin SDO is a TTL/CMOS compatible logic output. VDD pin voltage imposes a logical output
voltage range.
Pins FLAG and BUSY/SYNC are open drain outputs.
SW and CS inputs are internally pulled up to VDD and STBY/RESET input is internally
pulled down to ground.
6.3
Charge pump
To ensure the correct driving of the high-side integrated MOSFETs, a voltage higher than
the motor power supply voltage needs to be applied to the VBOOT pin. The high-side gate
driver supply voltage VBOOT is obtained through an oscillator and a few external
components realizing a charge pump (see Figure 4).
Doc ID 023768 Rev 2
19/73
Functional description
Figure 4.
L6482
Charge pump circuitry
V
VS + V
D1
CP
C
BOOT
VS
D2
D1
V
V
D2
VS + V
C
FLY
CP
D1
VBOOT
CP
VCP
to high-side
gate drivers
VDD
fPUMP
Charge pump oscillator
AM15034v1
6.4
Microstepping
The driver is able to divide the single step into up to 16 microsteps. Stepping mode can be
programmed by the STEP_SEL parameter in the STEP_MODE register (Table 22).
Step mode can only be changed when bridges are disabled. Every time the step mode is
changed, the electrical position (i.e. the point of microstepping sinewave that is generated)
is reset to the first microstep and the absolute position counter value (Section 6.5) becomes
meaningless.
Figure 5.
Normal mode and microstepping (16 microsteps)
Normal driving
Microstepping
Reset
position
Reset
position
PHASE A current
PHASE B current
PHASE A current
PHASE B current
microsteps
step 1 step 2 step 3 step 4 step 1
step 1 step 2 step 3 step 4 step 1
16
16
16
16
microsteps microsteps microsteps microsteps
AM15035v1
20/73
Doc ID 023768 Rev 2
L6482
Functional description
6.4.1
Automatic Full-step and Boost modes
When motor speed is greater than a programmable full-step speed threshold, the L6482
switches automatically to Full-step mode; the driving mode returns to microstepping when
motor speed decreases below the full-step speed threshold.
The switching between the microstepping and Full-step mode and vice versa is always
performed at an electrical position multiple of π/4 (Figure 6 and Figure 7).
Full-step speed threshold is set through the related parameter in the FS_SPD register
(Section 9.1.9).
When the BOOST_MODE bit of the FS_SPD register is low (default), the amplitude of the
voltage squarewave in Full-step mode is equal to the peak of the voltage sinewave multiplied
by sine(π/4) (Figure 6). This avoids the current drop between the two driving modes.
When the BOOST_MODE bit of the FS_SPD register is high, the amplitude of the voltage
squarewave in Full-step mode is equal to the peak of the voltage sinewave (Figure 7). That
improves the output current increasing the maximum motor torque.
Figure 6.
Automatic Full-step switching in Normal mode
V
peak
sin(π /4)x V
peak
Phase A
Phase B
Full-Step
Microstepping
Microstepping
(2N+1) xπ /4
(2N+1) xπ /4
AM15036v1
Doc ID 023768 Rev 2
21/73
Functional description
Figure 7.
L6482
Automatic Full-step switching in Boost mode
V
peak
Phase A
V
peak
Phase B
Full-Step
Microstepping
Microstepping
(2N+1) xπ /4
(2N+1) xπ/4
AM15037v1
6.5
6.6
Absolute position counter
An internal 22-bit register (ABS_POS) records all the motor motions according to the
selected step mode; the stored value unit is equal to the selected step mode (full, half,
quarter, etc.). The position range is from -221 to +221-1 steps (see Section 9.1.1).
Programmable speed profiles
The user can easily program a customized speed profile defining independently
acceleration, deceleration, and maximum and minimum speed values by ACC, DEC,
MAX_SPEED and MIN_SPEED registers respectively (see Section 9.1.5, 9.1.6, 9.1.7 and
9.1.8).
When a command is sent to the device, the integrated logic generates the microstep
frequency profile that performs a motor motion compliant to speed profile boundaries.
All acceleration parameters are expressed in step/tick2 and all speed parameters are
expressed in step/tick; the unit of measurement does not depend on the selected step
mode. Acceleration and deceleration parameters range from 2-40 to (212-2)•2-40 step/tick2
(equivalent to 14.55 to 59590 step/s2).
Minimum speed parameter ranges from 0 to (212-1)•2-24 step/tick (equivalent to 0 to 976.3
step/s).
Maximum speed parameter ranges from 2-18 to (210-1)• 2-18 step/tick (equivalent to 15.25 to
15610 step/s).
6.6.1
Infinite acceleration/deceleration mode
When the ACC register value is set to max. (0xFFF), the system works in “infinite
acceleration mode”: acceleration and deceleration phases are totally skipped, as shown in
Figure 8. It is not possible to skip the acceleration or deceleration phase independently.
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L6482
Functional description
Speed profile in infinite acceleration/deceleration mode
Figure 8.
SPEED
Programmed
maximum
speed
Programmed number of microsteps
time
time
Indexing mode
Constant speed mode
AM15038v1
6.7
Motor control commands
The L6482 can accept different types of commands:
●
●
●
●
constant speed commands (Run, GoUntil, ReleaseSW)
absolute positioning commands (GoTo, GoTo_DIR, GoHome, GoMark)
motion commands (Move)
stop commands (SoftStop, HardStop, SoftHiz, HardHiz).
For detailed command descriptions refer to Section 9.2.
6.7.1
Constant speed commands
A constant speed command produces a motion in order to reach and maintain a user-
defined target speed starting from the programmed minimum speed (set in the MIN_SPEED
register) and with the programmed acceleration/deceleration value (set in the ACC and DEC
registers). A new constant speed command can be requested anytime.
Figure 9.
Constant speed command examples
Speed
(step frequency)
SPD3
Run(SPD4,BW)
SPD1
SPD2
Run(SPD2,FW)
Run(SPD3,FW)
Minimum
speed
Minimum
speed
time
Run(SPD1,FW)
SPD4
AM15039v1
6.7.2
Positioning commands
An absolute positioning command produces a motion in order to reach a user-defined
position that is sent to the device together with the command. The position can be reached
Doc ID 023768 Rev 2
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Functional description
performing the minimum path (minimum physical distance) or forcing a direction (see
L6482
Figure 10).
Performed motor motion is compliant to programmed speed profile boundaries
(acceleration, deceleration, minimum and maximum speed).
Note that with some speed profiles or positioning commands, the deceleration phase can
start before the maximum speed is reached.
Figure 10. Positioning command examples
Forward
direction
0
0
Present
position
Present
position
Target
position
Target
position
-221 +221-1
GoTo(Target pos)
-221 +221-1
GoTo_DIR(Target pos,FW)
AM15040v1
6.7.3
Motion commands
Motion commands produce a motion in order to perform a user-defined number of
microsteps in a user-defined direction that are sent to the device together with the command
(see Figure 11).
Performed motor motion is compliant to programmed speed profile boundaries
(acceleration, deceleration, minimum and maximum speed).
Note that with some speed profiles or motion commands, the deceleration phase can start
before the maximum speed is reached.
Figure 11. Motion command examples
SPEED
SPEED
programmed number of microsteps
programmed number of microsteps
programmed
maximum
speed
programmed
maximum
speed
Note: with some
Acceleration/Decelaration profiles
the programmed maximum speed
is never reached
programmed
ACCELERATION
programmed
DECELERATION
programmed
ACCELERATION
programmed
DECELERATION
programmed
minimum
speed
programmed
minimum
speed
time
time
AM15041v1
24/73
Doc ID 023768 Rev 2
L6482
Functional description
6.7.4
Stop commands
A stop command forces the motor to stop. Stop commands can be sent anytime.
The SoftStop command causes the motor to decelerate with a programmed deceleration
value until the MIN_SPEED value is reached and then stops the motor keeping the rotor
position (a holding torque is applied).
The HardStop command stops the motor instantly, ignoring deceleration constraints and
keeping the rotor position (a holding torque is applied).
The SoftHiZ command causes the motor to decelerate with a programmed deceleration
value until the MIN_SPEED value is reached and then forces the bridges into high
impedance state (no holding torque is present).
The HardHiZ command instantly forces the bridges into high impedance state (no holding
torque is present).
6.7.5
6.7.6
Step-clock mode
In Step-clock mode the motor motion is defined by the step-clock signal applied to the STCK
pin. At each step-clock rising edge, the motor is moved one microstep in the programmed
direction and the absolute position is consequently updated.
When the system is in Step-clock mode, the SCK_MOD flag in the STATUS register is
raised, the SPEED register is set to zero and the motor status is considered stopped
regardless of the STCK signal frequency (the MOT_STATUS parameter in the STATUS
register equal to “00”).
GoUntil and ReleaseSW commands
In most applications the power-up position of the stepper motor is undefined, so an
initialization algorithm driving the motor to a known position is necessary.
The GoUntil and ReleaseSW commands can be used in combination with external switch
input (see Section 6.14) to easily initialize the motor position.
The GoUntil command makes the motor run at target constant speed until the SW input is
forced low (falling edge). When this event occurs, one of the following actions can be
performed:
●
ABS_POS register is set to zero (home position) and the motor decelerates to zero
speed (as a SoftStop command)
●
ABS_POS register value is stored in the MARK register and the motor decelerates to
zero speed (as a SoftStop command).
If the SW_MODE bit of the CONFIG register is set to ‘0’, the motor does not decelerate but
it immediately stops (as a HardStop command).
The ReleaseSW command makes the motor run at a programmed minimum speed until the
SW input is forced high (rising edge). When this event occurs, one of the following actions
can be performed:
●
ABS_POS register is set to zero (home position) and the motor immediately stops (as a
HardStop command)
●
ABS_POS register value is stored in the MARK register and the motor immediately
stops (as a HardStop command).
If the programmed minimum speed is less than 5 step/s, the motor is driven at 5 step/s.
Doc ID 023768 Rev 2
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Functional description
L6482
6.8
Internal oscillator and oscillator driver
The control logic clock can be supplied by the internal 16-MHz oscillator, an external
oscillator (crystal or ceramic resonator) or a direct clock signal.
These working modes can be selected by EXT_CLK and OSC_SEL parameters in the
CONFIG register (see Table 35).
At power-up the device starts using the internal oscillator and provides a 2-MHz clock signal
on the OSCOUT pin.
Attention: In any case, before changing clock source configuration, a
hardware reset is mandatory. Switching to different clock
configurations during operation may cause unexpected
behavior.
6.8.1
6.8.2
Internal oscillator
In this mode the internal oscillator is activated and OSCIN is unused. If the OSCOUT clock
source is enabled, the OSCOUT pin provides a 2, 4, 8 or 16-MHz clock signal (according to
OSC_SEL value); otherwise it is unused (see Figure 12).
External clock source
Two types of external clock source can be selected: crystal/ceramic resonator or direct clock
source. Four programmable clock frequencies are available for each external clock source:
8, 16, 24 and 32-MHz.
When an external crystal/resonator is selected, the OSCIN and OSCOUT pins are used to
drive the crystal/resonator (see Figure 12). The crystal/resonator and load capacitors (CL)
must be placed as close as possible to the pins. Refer to Table 8 for the choice of the load
capacitor value according to the external oscillator frequency.
Table 8.
CL values according to external oscillator frequency
(2)
Crystal/resonator frequency (1)
CL
8 MHz
16 MHz
24 MHz
32 MHz
25 pF (ESRmax = 80 Ω)
18 pF (ESRmax = 50 Ω)
15 pF (ESRmax = 40 Ω)
10 pF (ESRmax = 40 Ω)
1. First harmonic resonance frequency.
2. Lower ESR value allows greater load capacitors to be driven.
If a direct clock source is used, it must be connected to the OSCIN pin and the OSCOUT pin
supplies the inverted OSCIN signal (see Figure 12).
The L6482 integrates a clock detection system that resets the device in the case of a failure
of the external clock source (direct or crystal/resonator). The monitoring of the clock source
is disabled by default, it can be enabled setting high the WD_EN bit in the GATECFG1
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L6482
Functional description
register (Section 9.1.18). When the external clock source is selected, the device continues
to work with the integrated oscillator for textosc milliseconds and then the clock management
system switches to the OSCIN input.
Figure 12. OSCIN and OSCOUT pin configuration
EXT_CLK = "0"
EXT_CLK = "1"
8/16/24/32 MHz
C
L
CL
8/16/24/32 MHz
OSC_SEL = "1xx"
OSCIN
OSCOUT
OSCIN
OSCOUT
External oscillator
configuration
External clock source
configuration
2/4/8/16 MHz
OSC_SEL = "0xx"
UNUSED
UNUSED
OSCOUT
UNUSED
OSCIN
OSCIN
OSCOUT
Internal oscillator
Internal oscillator
configuration
configuration
without clock source
with clock generation
AM15042v1
Note:
When OSCIN is UNUSED, it should be left floating.
When OSCOUT is UNUSED, it should be left floating.
6.9
Overcurrent detection
The L6482 measures the load current of each half-bridge sensing the VDS voltage of all the
Power MOSFETs (Figure 13). When any of the VDS voltages rise above the programmed
threshold, the OCD flag in the STATUS register is forced low until the event expires and a
GetStatus command is sent to the device (Section 9.1.21 and Section 9.2.20). The
overcurrent event expires when all the Power MOSFET VDS voltages fall below the
programmed threshold.
The overcurrent threshold can be programmed by the OCD_TH register in one of 32
available values ranging from 31.25 mV to 1 V with steps of 31.25 mV (Table 21,
Section 9.1.17).
Doc ID 023768 Rev 2
27/73
Functional description
Figure 13. Overcurrent detection-principle scheme
L6482
Vs
LOGIC CORE
Vs
+
-
OCD_HSxx
HVGxx
Voltage
Comparator
BLANKING
OUTxx
CURRENT
DAC
OC
LVGxx
GNDx
THRESHOLD
Voltage
Comparator
OCD_LSxx
+
-
GND
GND
AM15043v1
The overcurrent detection comparators are disabled, in order to avoid wrong voltage
measurements, in the following cases:
●
●
●
The respective half-bridge is in high impedance state (both gates forced off)
The respective half-bridge is commutating
The respective half-bridge is commutated and the programmed blanking time has not
yet elapsed
●
The respective gate is turned off.
It is possible to set, if an overcurrent event causes the bridge turn-off or not, through the
OC_SD bit in the CONFIG register.
When the power bridges are turned off by an overcurrent event, they cannot be turned on
until the OCD flag is released by a GetStatus command.
6.10
Undervoltage lockout (UVLO)
The L6482 provides a programmable gate driver supply voltage UVLO protection. When
one of the supply voltages of the gate driver (VCC for the low sides and VBOOT - VS for the
high sides) falls below the respective turn-off threshold, an undervoltage event occurs. In
this case, all gates are immediately turned off and the UVLO flag in the STATUS register is
forced low.
The UVLO flag is forced low and the gates are kept off until the gate driver supply voltages
return to above the respective turn-on threshold; in this case the undervoltage event expires
and the UVLO flag can be released through a GetStatus command.
The UVLO thresholds can be selected between two sets according to the UVLOVAL bit
value in the CONFIG register.
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L6482
Functional description
Table 9.
UVLO thresholds
UVLOVAL
0
1
Low-side gate driver supply turn-off threshold
(VCCthOff
6.3 V
10 V
)
Low-side gate driver supply turn-on threshold
(VCCthOn
6.9 V
5.5 V
6 V
10.4 V
8.8 V
9.2 V
)
High-side gate driver supply turn-off threshold
(ΔVBOOTthOff
)
High-side gate driver supply turn-on threshold
(ΔVBOOTthOff
)
6.11
6.12
VS undervoltage lockout (UVLO_ADC)
The device provides an undervoltage signal of the integrated ADC input voltage (the
UVLO_ADC flag in the STATUS register). When VADCIN falls below the VADC,UVLO value, the
UVLO_ADC flag is forced low and it is kept in this state until the ADCIN voltage is greater
than VADC,UVLO and a GetStatus command is sent to the device.
The ADCIN undervoltage event does not turn off the gates of the power bridges.
The motor supply voltage undervoltage detection can be performed by means of this
feature, connecting the ADCIN pin to VS through a voltage divider.
Thermal warning and thermal shutdown
An integrated sensor allows detection of the internal temperature and implementation of a 3-
level protection.
When the Tj(WRN)Set threshold is reached, a warning signal is generated. This is the thermal
warning condition and it expires when the temperature falls below the Tj(WRN)Rel threshold.
When the Tj(OFF)Set threshold is reached, all the gates are turned off and the gate driving
circuitry is disabled (Miller clamps are still operative). This condition expires when the
temperature falls below the Tj(OFF)Rel threshold.
When the Tj(SD)OFF threshold is reached, all the gates are turned off using Miller clamps, the
internal VCC voltage regulator is disabled and the current capability of the internal VREG
voltage regulator is reduced (thermal shutdown). In this condition, logic is still active (if
supplied). The thermal shutdown condition only expires when the temperature goes below
Tj(SD)ON
.
The thermal condition of the device is shown by TH_STATUS bits in the STATUS register
(Table 10).
Doc ID 023768 Rev 2
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Functional description
L6482
Table 10. Thermal protection summarizing table
State
Normal
Set condition
Release condition
Description
TH_STATUS
Normal operation state
00
Temperature warning: operation is
not limited
Warning
Tj > Tj(WRN)Set
Tj > Tj(WRN)Rel
01
10
High temperature protection: the
gates are turned off and the gate
drivers are disabled
Bridge shutdown
Tj > Tj(OFF)Set
Tj > Tj(OFF)Rel
Overtemperature protection: the
gates are turned off, the gate
drivers are disabled, the internal
VCC voltage regulator is disabled,
the current capability of the
internal VREG voltage regulator is
limited, and the charge pump is
disabled
Device shutdown
Tj > Tj(SD)Set
Tj > Tj(SD)Rel
11
6.13
Reset and standby
The device can be reset and put into Standby mode through the STBY/RESET pin. When it
is forced low, all the gates are turned off (High Z state), the charge pump is stopped, the SPI
interface and control logic are disabled and the internal VREG voltage regulator maximum
output current is limited; as a result, the L6482 heavily reduces the power consumption. At
the same time the register values are reset to their default and all the protection functions
are disabled. The STBY/RESET input must be forced low at least for tSTBY,min in order to
ensure the complete switch to Standby mode.
On exiting Standby mode, as well as for IC power-up, a delay must be given before applying
a new command to allow proper oscillator and charge pump startup. Actual delay could vary
according to the values of the charge pump external components.
On exiting Standby mode all the gates are off and the HiZ flag is high.
The registers can be reset to the default values without putting the device into Standby
mode through the ResetDevice command (Section 9.2.15).
6.14
External switch (SW pin)
The SW input is internally pulled up to VDD and detects if the pin is open or connected to
ground (see Figure 14).
The SW_F bit of the STATUS register indicates if the switch is open (‘0’) or closed (‘1’)
(Section 9.1.21); the bit value is refreshed at every system clock cycle (125 ns). The
SW_EVN flag of the STATUS register is raised when a switch turn-on event (SW input falling
edge) is detected (Section 9.1.21). A GetStatus command releases the SW_EVN flag
(Section 9.2.20).
By default, a switch turn-on event causes a HardStop interrupt (SW_MODE bit of the
CONFIG register set to ‘0’). Otherwise (SW_MODE bit of the CONFIG register set to ‘1’),
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Functional description
switch input events do not cause interrupts and the switch status information is at the user’s
disposal (Table 36, Section 9.1.20).
The switch input can be used by GoUntil and ReleaseSW commands as described in
Section 9.2.10 and Section 9.2.11.
If the SW input is not used, it should be connected to VDD
.
Figure 14. External switch connection
VDD
External
Switch
SW
AM15044v1
6.15
Programmable gate drivers
The L6482 integrates eight programmable gate drivers that allow the fitting of a wide range
of applications.
The following parameters can be adjusted:
●
●
●
gate sink/source current (IGATE
controlled current time (tCC
turn-off overboost time (tOB).
)
)
During turn-on, the gate driver charges the gate forcing an IGATE current for all the controlled
current time period. At the end of the controlled current phase the gate of the external
MOSFET should be completely charged, otherwise the gate driving circuitry continues to
charge it using a holding current.
This current is equal to IGATE for the low-side gate drivers and 1 mA for the high-side ones.
During turn-off, the gate driver discharges the gate sinking an IGATE current for all the
controlled current time period. At the beginning of turn-off an overboost phase can be
added: in this case the gate driver sinks an IOB current for the programmed tOB period in
order to rapidly reach the plateau region. At the end of the controlled current time the gate of
the external MOSFET should be completely charged, otherwise the gate driving circuitry
discharges it using the integrated Miller clamp.
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Functional description
L6482
Figure 15. Gate driving currents
Gate discharged
tOB
tCC
Gate charged
tCC
IOB
Igate
Igate
Gate Current
Gate turn-on
Gate turn-off
AM15045v1
The gate current can be set to one of the following values: 4, 8, 16, 24, 32, 64 and 96 mA
through the IGATE parameter in the GATECFG1 register (see Section 9.1.18).
Controlled current time can be programmed within range from 125 ns to 3.75 μs with a
resolution of 125 ns (TCC parameter in the GATECFG1 register) (see Section 9.1.18).
Turn-off overboost time can be set to one of the following values: 0, 62.5, 125, 250 ns
(TBOOST parameter in the GATECFG1 register). The 62.5 ns value is only available when
clock frequency is 16 MHz or 32 MHz; when clock frequency is 8 MHz it is changed to 125
ns and when a 24-MHz clock is used it is changed to 83.3 ns. (see Section 9.1.18).
6.16
6.17
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Deadtime and blanking time
During the bridge commutation, a deadtime is added in order to avoid cross conductions.
The deadtime can be programmed within a range from 125 ns to 4 μs with a resolution of
125 ns (TDT parameter in the GATECFG2 register) (see Section 9.1.19).
At the end of each commutation the overcurrent and stall detection comparators are
disabled (blanking) in order to avoid the respective systems detecting body diode turn-off
current peaks.
The duration of blanking time is programmable through the TBLANK parameter in the
GATECFG2 register at one of the following values: 125, 250, 375, 500, 625, 750, 875, 1000
ns (see Section 9.1.19).
Integrated analog-to-digital converter
The L6482 integrates an NADC bit ramp-compare analog-to-digital converter with a
reference voltage equal to VREG. The analog-to-digital converter input is available through
the ADCIN pin and the conversion result is available in the ADC_OUT register
(Section 9.1.14).
The ADC_OUT value can be used for torque regulation or can be at the user’s disposal.
Doc ID 023768 Rev 2
L6482
Functional description
6.18
Supply management and internal voltage regulators
The L6482 integrates two linear voltage regulators: the first one can be used to obtain gate
driver supply starting from a higher voltage (e.g. the motor supply one). Its output voltage
can be set to 7.5 V or 15 V according to the VCCVAL bit value (CONFIG register). The
second linear voltage regulator can be used to obtain the 3.3 V logic supply voltage.
The regulators are designed to supply the internal circuitry of the IC and should not be used
to supply external components.
The input and output voltages of both regulators are connected to external pins and the
regulators are totally independent: in this way a very flexible supply management can be
performed using external components or external supply voltages (Figure 16).
Figure 16. Device supply pin management
All voltages are internally generated
All voltages are externally supplied
VBOOT
VBOOT
CP
CP
VBUS
VBUS
VS
VS
VCC
VSREG
VSREG
7V5 - 15V
VCC
7V5 - 15V
VCC
Using external components
(zener diodes, resistors, ...) it
is possible to reduce internal
power dissipation constrains.
3.3 V
VCCREG
VCCREG
VREG
3V3
3V3
VREG
AM15046v1
If VCC is externally supplied, the VSREG and VCC pins must be shorted (VSREG must be
compliant with VCC range).
If VREG is externally supplied, the VCCREG and VREG pins must be shorted and equal to
3.3 V.
V
SREG must be always less than VBOOT in order to avoid related ESD protection diode turn-
on. The device can be protected from this event by adding an external low drop diode
between the VSREG and VS pins, charge pump diodes should be low drop too.
V
CCREG must be always less than VCC in order to avoid ESD protection diode turn-on. The
device can be protected from this event by adding an external low drop diode between the
VCCREG and VSREG pins.
Both regulators provide a short-circuit protection limiting the load current within the
respective maximum ratings.
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Functional description
L6482
6.19
BUSY/SYNC pin
This pin is an open drain output which can be used as busy flag or synchronization signal
according to the SYNC_EN bit value (STEP_MODE register) (see Section 9.1.17).
6.20
FLAG pin
By default, an internal open drain transistor pulls the FLAG pin to ground when at least one
of the following conditions occurs:
●
●
●
●
●
●
●
●
Power-up or standby/reset exit
Overcurrent detection
Thermal warning
Thermal shutdown
UVLO
UVLO on ADC input
Switch turn-on event
Command error.
It is possible to mask one or more alarm conditions by programming the ALARM_EN
register (see Section 9.1.17 Table 26). If the corresponding bit of the ALARM_EN register is
low, the alarm condition is masked and it does not cause a FLAG pin transition; all other
actions imposed by alarm conditions are performed anyway. In case of daisy chain
configuration, FLAG pins of different ICs can be OR-wired to save host controller GPIOs.
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L6482
Phase current control
7
Phase current control
The L6482 performs a new current control technique, named predictive current control,
allowing the device to obtain the target average phase current. This method is described in
detail in Section 7.1. Furthermore, the L6482 automatically selects the better decay mode in
order to follow the current profile.
Current control algorithm parameters can be programmed by T_FAST, TON_MIN,
TOFF_MIN and CONFIG registers (see Section 9.1.11, 9.1.12, 9.1.13 and 9.1.20 for
details).
Different current amplitude can be set for acceleration, deceleration and constant speed
phases and when the motor is stopped through TVAL_ACC, TVAL_DEC, TVAL_RUN and
TVAL_HOLD registers (see Section 9.1.10). The output current amplitude can also be
regulated by the ADCIN voltage value (see Section 7.4).
Each bridge is driven by an independent control system that shares with the other bridge the
control parameters only.
7.1
Predictive current control
Unlike classical peak current control systems, that make the phase current decay when the
target value is reached, this new method keeps the power bridge ON for an extra time after
reaching the current threshold.
At each cycle the system measures the time required to reach the target current (tSENSE).
After that the power stage is kept in a “predictive” ON state (tPRED) for a time equal to the
mean value of tSENSE in the last two control cycles (actual one and previous one), as
shown in Figure 17.
Figure 17. Predictive current control
I
out
predictive ON
tSENSE (n-1) + tSENSE(n)
2
state
tPRED(n) =
OFF
state
I
ref
t
tSENSE (n-1)
tPRED(n)
SENSE (n)
OFF
tOFF
t
AM15048v1
t
PRED(n-1)
At the end of the predictive ON state the power stage is set in OFF state for a fixed time, as
in a constant tOFF current control. During the OFF state both slow and fast decay can be
performed; the better decay combination is automatically selected by the L6482, as
described in Section 7.2.
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Phase current control
L6482
As shown in Figure 17, the system is able to center the triangular wave on the desired
reference value, improving dramatically the accuracy of the current control system: in fact
the average value of a triangular wave is exactly equal to the middle point of each of its
segment and at steady-state the predictive current control tends to equalize the duration of
the tSENSE and the tPRED time.
Furthermore, the tOFF value is recalculated each time a new current value is requested
(microstep change) in order to keep the PWM frequency as near as possible to the
programmed one (TSW parameter in the CONFIG register).
The device can be forced to work using classic peak current control setting low the
PRED_EN bit in the CONFIG register (default condition). In this case, after the sense phase
(tSENSE) the power stage is set in OFF state, as shown in Figure 18.
Figure 18. Non-predictive current control
I
out
sense ON
state
OFF
state
I
ref
t
OFF
t
OFF
AM15049v1
7.2
Auto-adjusted decay mode
During the current control, the device automatically selects the better decay mode in order
to follow the current profile reducing the current ripple.
At reset, the off-time is performed turning on both the low-side MOS of the power stage and
the current recirculates in the lower half of the bridge (slow decay).
If, during a PWM cycle, the target current threshold is reached in a time shorter than the
TON_MIN value, a fast decay of TOFF_FAST/8 (T_FAST register) is immediately performed
turning on the opposite MOS of both half-bridges and the current recirculates back to the
supply bus.
After this time, the bridge returns to ON state: if the time needed to reach the target current
value is still less than TON_MIN, a new fast decay is performed with a period twice the
previous one. Otherwise, the normal control sequence is followed as described in
Section 7.1. The maximum fast decay duration is set by the TOFF_FAST value.
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Phase current control
Figure 19. Adaptive decay - fast decay tuning
1st fast decay:
Tfast = TOFF_FAST/8
3rd fast decay:
Tfast = TOFF_FAST/2
Ton > TON_MIN
Tfast = TOFF_FAST/2
2nd fast decay (*):
Tfast = TOFF_FAST/4
reference current
(*)Note: starting from 2nd fast decay the system combines
fast and slow decay during the OFF phase.
AM15050v1
When two or more fast decays are performed with the present target current, the control
system adds a fast decay at the end of every off-time keeping the OFF state duration
constant (tOFF is split into tOFF, SLOW and tOFF, FAST). When the current threshold is
increased by a microstep change (rising step), the system returns to normal decay mode
(slow decay only) and the tFAST value is halved.
Stopping the motor or reaching the current sinewave zero crossing causes the current
control system to return to the reset state.
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Phase current control
L6482
Figure 20. Adaptive decay - switch from normal to slow+fast decay mode and vice
versa
2nd fast decay
switch to fast + slow decay mode
st
1 fast decay
reference current
Time
tOFF
tOFF
tOFF,SLOW
tOFF,FAST
tFAST
Target current is increased (raising step)
system returns to slow decay mode and t
vaule is halved
FAST
reference current
Time
AM15051v1
7.3
Auto-adjusted fast decay during the falling steps
When the target current is decreased by a microstep change (falling step), the device
performs a fast decay in order to reach the new value as fast as possible. However,
exceeding the fast duration could cause a strong ripple on the step change. The L6482
automatically adjusts these fast decays reducing the current ripple.
At reset the fast decay value (tFALL) is set to FALL_STEP/4 (T_FAST register). The tFALL
value is doubled every time, within the same falling step, an extra fast decay is necessary to
obtain an on-time greater than TON_MIN (see Section 9.1.12). The maximum tFALL value is
equal to FALL_STEP.
At the next falling step, the system uses the last tFALL value of the previous falling step.
Stopping the motor or reaching the current sinewave zero crossing causes the current
control system to return to the reset state.
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Phase current control
Figure 21. Fast decay tuning during the falling steps
Falling step
st
1 fast decay:
t FALL = FALL_STEP/4
Falling step
st
1 fast decay:
tFALL= FALL_STEP/2
reference current
2nd fast decay:
tFALL = FALL_STEP/2
Time
AM15052v1
7.4
Torque regulation (output current amplitude regulation)
The phase currents are monitored through two shunt resistors (one for each power bridge)
connected to the respective sense pin (see Figure 22). The integrated comparator
compares the sense resistor voltage with the internal reference generated using the peak
value, which is proportional to the output current amplitude, and the microstepping code.
The comparison result is provided to the logic in order to implement the current control
algorithm as described in previous sections.
The peak reference voltage can be regulated in two ways: writing TVAL_ACC, TVAL_DEC,
TVAL_RUN and TVAL_HOLD registers or varying the ADCIN voltage value.
The EN_TQREG bit (CONFIG register) sets the torque regulation method. If this bit is high,
ADC_OUT prevalue is used to regulate output current amplitude (see Table 20,
Section 9.1.14). Otherwise the internal analog-to-digital converter is at the user’s disposal
and the output current amplitude is managed by TVAL_HOLD, TVAL_RUN, TVAL_ACC and
TVAL_DEC registers (see Table 14, Section 9.1.10).
The voltage applied to the ADCIN pin is sampled at fS frequency and converted in an NADC
bit digital signal. The analog-to-digital conversion result is available in the ADC_OUT
register.
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Phase current control
L6482
Figure 22. Current sensing and reference voltage generation
Peak reference DAC
To gate
drivers
To gate
TVAL_X or ADCIN
drivers
Load
Microstepping DAC
Microstep
To gate
drivers
To gate
drivers
V
ref
To current
control logic
SENSEX
R
sense
AM15047v1
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L6482
Serial interface
8
Serial interface
The integrated 8-bit serial peripheral interface (SPI) is used for a synchronous serial
communication between the host microprocessor (always master) and the L6482 (always
slave).
The SPI uses chip select (CS), serial clock (CK), serial data input (SDI) and serial data
output (SDO) pins. When CS is high the device is unselected and the SDO line is inactive
(high impedance).
The communication starts when CS is forced low. The CK line is used for synchronization of
data communication.
All commands and data bytes are shifted into the device through the SDI input, most
significant bit first. The SDI is sampled on the rising edges of the CK.
All output data bytes are shifted out of the device through the SDO output, most significant
bit first. The SDO is latched on the falling edges of the CK. When a return value from the
device is not available, an all zero byte is sent.
After each byte transmission the CS input must be raised and be kept high for at least tdisCS
in order to allow the device to decode the received command and put the return value into
the shift register.
All timing requirements are shown in Figure 23 (see Section 3 for values).
Multiple devices can be connected in daisy chain configuration, as shown in Figure 24.
Figure 23. SPI timings diagram
CS
t
disCS
t
setCS
t
rCK
t
hCK
t
fCK
t
lCK
CK
SDI
t
enSDO
t
disSDO
t
holCS
t
setSDI
t
holSDI
MSB
N-1
N-1
N-2
N-2
LSB
t
vSDO
t
holSDO
HiZ
SDO
MSB
LSB
MSB
AM15053v1
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Serial interface
Figure 24. Daisy chain configuration
L6482
DEV 1
CS
CS
CK
SDI
CK
HOST
SDO
M
SDI
M
SDO
DEV 2
CS
CK
HOST SPI signals
SDI
SDO
CS
SDO
M
Byte N
Byte N
Byte N-1
Byte N-1
Byte 1
Byte 1
Byte N
Byte N
DEV N
SDI
M
CS
CK
SDI
SDO
AM15054v1
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Programming manual
9
Programming manual
9.1
Register and flag description
Table 11 shows the user registers available (a detailed description can be found in the
respective paragraphs):
Table 11. Register map
Address
Reset
Hex
Reset
value
Len.
[bit]
Remarks
Register name
[Hex]
Register function
(1)
h01
h02
h03
h04
ABS_POS
EL_POS
MARK
Current position
Electrical position
Mark position
22 000000
000
22 000000
0
0
0
R, WS
R, WS
R, WR
R
9
SPEED
Current speed
20
12
00000 0 step/tick (0 step/s)
125.5e-12 step/tick2 (2008
h05
h06
ACC
DEC
Acceleration
Deceleration
08A
R, WS
R, WS
step/s2)
125.5e-12 step/tick2 (2008
12
08A
step/s2)
h07
h08
MAX_SPEED Maximum speed
MIN_SPEED Minimum speed
10
12
041
000
248e-6 step/tick (991.8 step/s)
0 step/tick (0 step/s)
R, WR
R, WS
150.7e-6 step/tick (602.7
step/s)
h15
h09
h0A
h0B
h0C
FS_SPD
TVAL_HOLD
TVAL_RUN
TVAL_ACC
TVAL_DEC
Full-step speed
10
7
027
29
R, WR
R, WR
R, WR
R, WR
R, WR
Holding reference
voltage
328 mV
328 mV
328 mV
328 mV
Constant speed
reference voltage
7
29
Acceleration starting
reference voltage
7
29
Deceleration starting
reference voltage
7
29
h0D
h0E
h0F
h10
h11
h12
h13
h14
RESERVED
T_FAST
-
Fast decay settings
Minimum on-time
Minimum off-time
-
16
8
-
19
29
29
-
-
-
1 us / 5 us
R, WH
R, WH
R, WH
-
TON_MIN
TOFF_MIN
RESERVED
ADC_OUT
OCD_TH
8
20.5 us
8
20.5 us
8
-
ADC output
OCD threshold
-
5
XX(2)
0
R
5
8
281.25 mV
-
R, WR
-
RESERVED
8
-
16 μsteps, SYNC mode
h16
h17
STEP_MODE Step mode
8
8
7
R, WH
R, WS
disabled
ALARM_EN Alarms enabled
FF
All alarms enabled
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L6482
Table 11. Register map (continued)
Address
Reset
Hex
Reset
value
Len.
[bit]
Remarks
Register name
Register function
(1)
[Hex]
Gate driver
configuration
I
gate = 4 mA, tCC = 125 ns, no
h18
GATECFG1
GATECFG2
11
8
0
0
R, WH
R, WH
boost
Gate driver
configuration
h19
h1A
tBLANK = 125 ns, tDT = 125 ns
Internal 16 MHz oscillator
(OSCOUT@2 MHz),
SW event causes HardStop,
motor supply voltage
compensation disabled,
CONFIG
STATUS
IC configuration
16
2C88
R, WH
overcurrent shutdown,
V
CC = 7.5 V,
UVLO threshold low,
tSW = 44 us
High impedance state,
motor stopped,
h1B
Status
16 XXXX(2)
R
reverse direction,
all fault flags released
UVLO/Reset flag set
1. R: readable, WH: writable, only when outputs are in high impedance, WS: writable only when motor is stopped, WR: always
writable.
2. According to startup conditions.
9.1.1
9.1.2
ABS_POS
The ABS_POS register contains the current motor absolute position in agreement with the
selected step mode; the stored value unit is equal to the selected step mode (full, half,
quarter, etc.). The value is in 2's complement format and it ranges from -221 to +221-1.
At power-on the register is initialized to “0” (HOME position).
Any attempt to write the register when the motor is running causes the command to be
ignored and the NOTPERF_CMD flag to rise (Section 9.1.21).
EL_POS
The EL_POS register contains the current electrical position of the motor. The two MSbits
indicate the current step and the other bits indicate the current microstep (expressed in
step/16) within the step.
Table 12. EL_POS register
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STEP
MICROSTEP
0
0
0
When the EL_POS register is written by the user, the new electrical position is instantly
imposed. When the EL_POS register is written, its value must be masked in order to match
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Programming manual
with the step mode selected in the STEP_MODE register in order to avoid a wrong
microstep value generation (Section 9.1.17); otherwise the resulting microstep sequence is
incorrect.
Any attempt to write the register when the motor is running causes the command to be
ignored and the NOTPERF_CMD flag to rise (Section 9.1.21).
9.1.3
9.1.4
MARK
The MARK register contains an absolute position called MARK, according to the selected
step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.).
It is in 2's complement format and it ranges from -221 to +221-1.
SPEED
The SPEED register contains the current motor speed, expressed in step/tick (format
unsigned fixed point 0.28).
In order to convert the SPEED value in step/s, the following formula can be used:
Equation 1
SPEED ⋅ 2–28
[step/s]= ---------------------------------------
tick
where SPEED is the integer number stored in the register and tick is 250 ns.
The available range is from 0 to 15625 step/s with a resolution of 0.015 step/s.
The range effectively available to the user is limited by the MAX_SPEED parameter.
Note:
Any attempt to write the register causes the command to be ignored and the
NOTPERF_CMD flag to rise (Section 9.1.21).
9.1.5
ACC
The ACC register contains the speed profile acceleration expressed in step/tick2 (format
unsigned fixed point 0.40).
In order to convert the ACC value in step/s2, the following formula can be used:
Equation 2
ACC ⋅ 2–40
2
[step/s ]= -------------------------------
tick2
where ACC is the integer number stored in the register and tick is 250 ns.
The available range is from 14.55 to 59590 step/s2 with a resolution of 14.55 step/s2.
When the ACC value is set to 0xFFF, the device works in infinite acceleration mode.
Any attempt to write to the register when the motor is running causes the command to be
ignored and the NOTPERF_CMD flag to rise (Section 9.1.21).
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L6482
9.1.6
DEC
The DEC register contains the speed profile deceleration expressed in step/tick2 (format
unsigned fixed point 0.40).
In order to convert the DEC value in step/s2, the following formula can be used:
Equation 3
DEC ⋅ 2–40
2
[step/s ]= -------------------------------
tick2
where DEC is the integer number stored in the register and tick is 250 ns.
The available range is from 14.55 to 59590 step/s2 with a resolution of 14.55 step/s2.
When the device is working in infinite acceleration mode this value is ignored.
Any attempt to write the register when the motor is running causes the command to be
ignored and the NOTPERF_CMD flag to rise (Section 9.1.21).
9.1.7
MAX_SPEED
The MAX_SPEED register contains the speed profile maximum speed expressed in
step/tick (format unsigned fixed point 0.18).
In order to convert it in step/s, the following formula can be used:
Equation 4
MAX_SPEED ⋅ 2–18
[step/s]= -------------------------------------------------------
tick
where MAX_SPEED is the integer number stored in the register and tick is 250 ns.
The available range is from 15.25 to 15610 step/s with a resolution of 15.25 step/s.
9.1.8
MIN_SPEED
The MIN_SPEED register contains the following parameters:
Table 13. MIN_SPEED register
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
MIN_SPEED
The MIN_SPEED parameter contains the speed profile minimum speed. Its value is
expressed in step/tick and to convert it in step/s the following formula can be used:
Equation 5
MIN_SPEED ⋅ 2–24
[step/s]= -----------------------------------------------------
tick
where MIN_SPEED is the integer number stored in the register and tick is the ramp 250 ns.
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Programming manual
The available range is from 0 to 976.3 step/s with a resolution of 0.238 step/s.
Any attempt to write the register when the motor is running causes the NOTPERF_CMD flag
to rise.
9.1.9
FS_SPD
The FS_SPD register contains the following parameters:
Table 14. FS_SPD register
Bit 11
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BOOST_MODE
FS_SPD
The FS_SPD threshold speed value over which the step mode is automatically switched to
full-step two-phase on. Its value is expressed in step/tick (format unsigned fixed point 0.18)
and to convert it in step/s the following formula can be used:
Equation 6
(FS_SPD + 0.5) ⋅ 2–18
[step/s]= -------------------------------------------------------------
tick
If FS_SPD value is set to hFF (max.) the system always works in Microstepping mode
(SPEED must go over the threshold to switch to Full-step mode). Setting FS_SPD to zero
does not have the same effect as setting the step mode to full-step two-phase on: the zero
FS_SPD value is equivalent to a speed threshold of about 7.63 step/s.
The available range is from 7.63 to 15625 step/s with a resolution of 15.25 step/s.
The BOOST_MODE bit sets the amplitude of the voltage squarewave during the full-step
operation (see Section 6.4.1).
9.1.10
TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC
The TVAL_HOLD register contains the reference voltage that is assigned to the torque
regulation DAC when the motor is stopped.
The TVAL_RUN register contains the reference voltage that is assigned to the torque
regulation DAC when the motor is running at constant speed.
The TVAL_ACC register contains the reference voltage that is assigned to the torque
regulation DAC during acceleration.
The TVAL_DEC register contains the reference voltage that is assigned to the torque
regulation DAC during deceleration.
The available range is from 7.8 mV to 1 V with a resolution of 7.8 mV, as shown in Table 15.
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Table 15. Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and
TVAL_RUN registers
TVAL_X [6..0]
Peak reference voltage
0
0
0
0
0
0
0
0
0
0
0
0
0
1
7.8 mV
15.6 mV
1
1
1
1
1
1
1
1
1
1
1
1
0
1
992.2 mV
1 V
9.1.11
T_FAST
The T_FAST register contains the maximum fast decay time (TOFF_FAST) and the
maximum fall step time (FALL_STEP) used by the current control system (Section 7.2 and
Section 7.3 for details):
Table 16. FS_SPD register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOFF_FAST
FAST_STEP
The available range for both parameters is from 2 µs to 32 µs.
Table 17. Maximum fast decay times
TOFF_FAST [3..0] FAST_STEP[3..0]
Fast decay time
0
0
0
0
0
0
0
1
2 µs
4 µs
1
1
1
1
1
1
0
1
28 µs
32 µs
Any attempt to write to the register when the motor is running causes the command to be
ignored and NOTPERF_CMD to rise (Section 9.1.21).
9.1.12
TON_MIN
This parameter is used by the current control system when current mode operation is
selected.
The TON_MIN register contains the minimum on-time value used by the current control
system (see Section 7.2).
The available range for both parameters is from 0.5 µs to 64 µs.
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Time
Table 18. Minimum on-time
TON MIN [6..0]
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0.5 µs
1 µs
1
1
1
1
1
1
1
1
1
1
1
1
0
1
63.5 µs
64 µs
Any attempt to write to the register when the motor is running causes the command to be
ignored and the NOTPERF_CMD to rise (see Section 9.1.21).
9.1.13
TOFF_MIN
This parameter is used by the current control system when current mode operation is
selected.
The TOFF_MIN register contains the minimum off-time value used by the current control
system (see Section 7.1 for details).
The available range for both parameters is from 0.5 µs to 64 µs.
Table 19. Minimum off-time
TOFF MIN [6..0]
Time
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0.5 µs
1 µs
1
1
1
1
1
1
1
1
1
1
1
1
0
1
63.5 µs
64 µs
Any attempt to write to the register when the motor is running causes the command to be
ignored and NOTPERF_CMD to rise (see Section 9.1.21).
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9.1.14
ADC_OUT
The ADC_OUT register contains the result of the analog-to-digital conversion of the ADCIN
pin voltage.
Any attempt to write to the register causes the command to be ignored and the
NOTPERF_CMD flag to rise (see Section 9.1.21).
Table 20. ADC_OUT value and torque regulation feature
VADCIN/ VREG
ADC_OUT [4..0]
Reference voltage
0
0
0
0
0
0
0
0
0
0
1
31.25 mV
62.5 mV
1/32
30/32
31/32
1
1
1
1
1
1
1
1
0
1
968.8 mV
1 V
9.1.15
OCD_TH
The OCD_TH register contains the overcurrent threshold value (see Section 6.9 for details).
The available range is from 31.25 mV to 1 V, steps of 31.25 mV, as shown in Table 21.
Table 21. Overcurrent detection threshold
OCD_TH [4..0]
Overcurrent detection threshold
0
0
0
0
0
0
0
0
0
1
31.25 mV
62.5 mV
1
1
1
1
1
1
1
1
0
1
968.8 mV
1 V
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9.1.16
STEP_MODE
The STEP_MODE register has the following structure:
Table 22. STEP_MODE register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYNC_EN
SYNC_SEL
1(1)
STEP_SEL
1. When the register is written this bit must be set to 1.
The STEP_SEL parameter selects one of five possible stepping modes:
Table 23. Step mode selection
STEP_SEL[2..0]
Step mode
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Full-step
Half-step
1/4 microstep
1/8 microstep
1/16 microstep
Every time the step mode is changed, the electrical position (i.e. the point of microstepping
sinewave that is generated) is reset to the first microstep.
Warning: Every time STEP_SEL is changed, the value in the ABS_POS
register loses meaning and should be reset.
Any attempt to write the register when the motor is running causes the command to be
ignored and the NOTPERF_CMD flag to rise (see Section 9.1.21).
When the SYNC_EN bit is set low, the BUSY/SYNC output is forced low during the
command execution, otherwise, when the SYNC_EN bit is set high, the BUSY/SYNC output
provides a clock signal according to the SYNC_SEL parameter.
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Table 24. SYNC output frequency
STEP_SEL (fFS is the full-step frequency)
000
fFS/2
NA
001
fFS/2
fFS
010
fFS/2
fFS
011
fFS/2
fFS
100
fFS/2
fFS
101
fFS/2
fFS
110
fFS/2
fFS
111
fFS/2
fFS
000
001
010
011
100
101
110
111
NA
NA
NA
NA
NA
NA
NA
2· fFS
NA
2· fFS
4· fFS
NA
2· fFS
4· fFS
8· fFS
NA
2· fFS
4· fFS
8· fFS
NA
2· fFS
4· fFS
8· fFS
NA
2· fFS
4· fFS
8· fFS
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
The synchronization signal is obtained starting from the electrical position information
(EL_POS register), according to Table 25:
Table 25. SYNC signal source
SYNC_SEL[2..0]
Source
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EL_POS[7]
EL_POS[6]
EL_POS[5]
EL_POS[4]
EL_POS[3]
UNUSED (1)
UNUSED (1)
UNUSED (1)
1. When this value is selected, the BUSY output is forced low.
9.1.17
ALARM_EN
The ALARM_EN register allows the selection of which alarm signals are used to generate
the FLAG output. If the respective bit of the ALARM_EN register is set high, the alarm
condition forces the FLAG pin output down.
Table 26. ALARM_EN register
ALARM_EN bit
Alarm condition
0 (LSB)
1
Overcurrent
Thermal shutdown
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Table 26. ALARM_EN register (continued)
ALARM_EN bit
Alarm condition
2
Thermal warning
UVLO
3
4
ADC UVLO
5
6
Unused
Switch turn-on event
Command error
7 (MSB)
9.1.18
GATECFG1
The GATECFG1 register has the following structure:
Table 27. GATECFG1 register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 4
Bit 11
Bit 10
Bit 9
Bit 8
Bit 0
WD_EN
TBOOST
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
IGATE
TCC
The IGATE parameter selects the sink/source current used by gate driving circuitry to
charge/discharge the respective gate during commutations. Seven possible values ranging
from 4 mA to 96 mA are available, as shown in Table 28.
Table 28. IGATE parameter
IGATE [2..0}
Gate current [mA}
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
4
8
16
24
32
64
96
The TCC parameter defines the duration of constant current phase during gate turn-on and
turn-off sequences (Section 6.15).
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Table 29. TCC parameter
Constant current time
TCC [4..0]
[ns]
0
0
⇓
1
1
1
1
0
0
⇓
1
1
1
1
0
0
⇓
1
1
1
1
0
0
⇓
0
0
1
1
0
1
⇓
0
1
0
1
125
250
⇓
3625
3750
3750
3750
The TBOOST parameter defines the duration of the overboost phase during gate turn-off
(Section 6.15).
Table 30. TBOOST parameter
TBOOST
[2..0]
Turn-off boost time
[ns]
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
62.5(1)/83.3(2)/125(3)
125
250
375
500
750
1000
1. Clock frequency equal to 16 MHz or 32 MHz.
2. Clock frequency equal to 24 MHz.
3. Clock frequency equal to 8 MHz.
The WD_EN bit enables the clock source monitoring (Section 6.8.2).
9.1.19
GATECFG2
The GATECFG2 register has the following structure:
Table 31. GATECFG2 register (voltage mode)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
TBLANK
TDT
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The TCC parameter defines the deadtime duration between the gate turn-off and the
opposite gate turn-on sequences (Section 6.16).
Table 32. TDT parameter
TDT [4..0]
Deadtime [ns]
0
0
⇓
1
1
0
0
⇓
1
1
0
0
⇓
1
1
0
0
⇓
1
1
0
1
⇓
0
1
125
250
⇓
3875
4000
The TBLANK parameter defines the duration of the blanking of the current sensing
comparators (stall detection and overcurrent) after each commutation (Section 6.16).
Table 33. TBLANK parameters
TBLANK [2..0]
Blanking time [ns]
0
0
⇓
1
1
0
0
⇓
1
1
0
1
⇓
0
1
125
250
⇓
875
1000
9.1.20
CONFIG
The CONFIG register has the following structure:
Table 34. CONFIG register
Bit 15
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
TSW
Bit 11
Bit 10
Bit 2
Bit 9
Bit 8
PRED_E
VCCVAL
UVLOVAL
Bit 7
Bit 4
Bit 3
Bit 1
Bit 0
SW_MOD
E
OC_SD
RESERVED EN_TQREG
EXT_CLK
OSC_SEL
The OSC_SEL and EXT_CLK bits set the system clock source:
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Table 35. Oscillator management
EXT_CLK OSC_SEL[2..0]
Clock source
OSCIN
OSCOUT
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Internal oscillator: 16 MHz
Unused
Unused
Supplies a 2-MHz
clock
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal oscillator: 16 MHz
Internal oscillator: 16 MHz
Internal oscillator: 16 MHz
Internal oscillator: 16 MHz
Unused
Unused
Unused
Unused
Supplies a 4-MHz
clock
Supplies an 8-MHz
clock
Supplies a 16-MHz
clock
External crystal or
resonator: 8 MHz
Crystal/resonator Crystal/resonator
driving driving
External crystal or
resonator: 16 MHz
Crystal/resonator Crystal/resonator
driving driving
External crystal or
resonator: 24 MHz
Crystal/resonator Crystal/resonator
driving driving
External crystal or
resonator: 32 MHz
Crystal/resonator Crystal/resonator
driving
driving
Ext. clock source: 8 MHz
(crystal/resonator driver
disabled)
Supplies inverted
OSCIN signal
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Clock source
Ext. clock source: 16 MHz
(crystal/resonator driver
disabled)
Supplies inverted
OSCIN signal
Clock source
Clock source
Clock source
Ext. clock source: 24 MHz
(crystal/resonator driver
disabled)
Supplies inverted
OSCIN signal
Ext. clock source: 32 MHz
(crystal/resonator driver
disabled)
Supplies inverted
OSCIN signal
The SW_MODE bit sets the external switch to act as HardStop interrupt or not:
Table 36. External switch HardStop interrupt mode
SW_MODE
Switch mode
0
1
HardStop interrupt
User disposal
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The OC_SD bit sets if an overcurrent event causes or not the bridges to turn off; the OCD
flag in the status register is forced low anyway:
Table 37. Overcurrent event
OC_SD
Overcurrent event
1
0
Bridges shutdown
Bridges do not shutdown
The VCCVAL bit sets the internal VCC regulator output voltage.
Table 38. Programmable VCC regulator output voltage
VCCVAL
VCC voltage
0
1
7.5 V
15 V
The UVLOVAL bit sets the UVLO protection thresholds.
Table 39. Programmable UVLO thresholds
UVLOVAL
VCCthOn
VCCthOff
ΔVBOOTthOn
ΔVBOOTthOff
0
1
6.9 V
6.3 V
10 V
6 V
5.5 V
8.8 V
10.4 V
9.2 V
The EN_TQREG bit sets if the torque regulation is performed through ADCIN voltage
(external) or the TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers (internal).
Table 40. External torque regulation enable
EN_TQREG
External torque regulation
0
1
Disabled
Enabled
The TSW parameter is used by the current control system and it sets the target switching
period.
Table 41. Switching period
TSW [4..0]
Switching period
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
4 µs (250 kHz)
4 µs (250 kHz)
8 µs (125 kHz)
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Table 41. Switching period (continued)
L6482
TSW [4..0]
Switching period
1
1
1
1
1
124 µs (8 kHz)
Any attempt to write the CONFIG register when the motor is running causes the command
to be ignored and the NOTPERF_CMD flag to rise (see Section 9.1.21).
The EN_PRED bit sets if the predictive current control method is enabled or not.
.
Table 42. Motor supply voltage compensation enable
EN_PRED
Predictive current control
0
1
Disabled
Enabled
Any attempt to write the CONFIG register when the motor is running causes the command
to be ignored and the NOTPERF_CMD flag to rise (Section 9.1.20).
9.1.21
STATUS
The STATUS register has the following structure:
Table 43. STATUS register
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
UVLO_AD
C
Unused
Unused
OCD
TH_SD
UVLO STCK_MOD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NOTPERF_CM
D
SW_EV
N
MOT_STATUS
DIR
SW_F
BUSY
HiZ
When the HiZ flag is high it indicates that the bridges are in high impedance state. Any
motion command causes the device to exit from High Z state (HardStop and SoftStop
included), unless error flags forcing a High Z state are active.
The UVLO flag is active low and is set by an undervoltage lockout or reset events (power-up
included).
The UVLO_ADC flag is active low and indicates an ADC undervoltage event.
The OCD flag is active low and indicates an overcurrent detection event.
The CMD_ERROR flag is active high and indicates that the command received by SPI can't
be performed or does not exist at all.
The SW_F reports the SW input status (low for open and high for closed).
The SW_EVN flag is active high and indicates a switch turn-on event (SW input falling
edge).
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TH_STATUS bits indicate the current device thermal status (Section 6.12):
Table 44. STATUS register TH_STATUS bits
TH_STATUS
Status
0
0
1
1
0
1
0
1
Normal
Warning
Bridge shutdown
Device shutdown
UVLO, UVLO_ADC, OCD, CMD_ERROR, SW_EVN and TH_STATUS bits are latched:
when the respective conditions make them active (low or high) they remain in that state until
a GetStatus command is sent to the IC.
The BUSY bit reflects the BUSY pin status. The BUSY flag is low when a constant speed,
positioning or motion command is under execution and is released (high) after the command
has been completed.
The STCK_MOD bit is an active high flag indicating that the device is working in Step-clock
mode. In this case the step-clock signal should be provided through the STCK input pin.
The DIR bit indicates the current motor direction:
Table 45. STATUS register DIR bit
DIR
Motor direction
1
0
Forward
Reverse
MOT_STATUS indicates the current motor status:
Table 46. STATUS register MOT_STATE bits
MOT_STATUS
Motor status
0
0
1
1
0
1
0
1
Stopped
Acceleration
Deceleration
Constant speed
Any attempt to write to the register causes the command to be ignored and the
NOTPERF_CMD to rise (Section 9.1.21).
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9.2
Application commands
The command summary is given in Table 47.
Table 47. Application commands
Command Mnemonic
Command binary code
[7..5] [4] [3] [2..1] [0]
Action
NOP
000
0
0
00
0
Nothing
SetParam(PARAM,VALUE) 000
[PARAM]
[PARAM]
Writes VALUE in PARAM register
GetParam(PARAM)
Run(DIR,SPD)
001
010
Returns the stored value in PARAM register
1
1
0
1
00 DIR Sets the target speed and the motor direction
Puts the device in Step-clock mode and imposes DIR
direction
StepClock(DIR)
010
00 DIR
00 DIR
Makes N_STEP (micro)steps in DIR direction
(not performable when motor is running)
Move(DIR,N_STEP)
GoTo(ABS_POS)
010
011
0
0
0
0
0
1
00
0
Brings motor in ABS_POS position (minimum path)
GoTo_DIR(DIR,ABS_POS) 011
00 DIR Brings motor in ABS_POS position forcing DIR direction
Performs a motion in DIR direction with speed SPD until
GoUntil(ACT,DIR,SPD)
ReleseSW(ACT, DIR)
100
100
0
1
ACT 01 DIR SW is closed, the ACT action is executed then a SoftStop
takes place
Performs a motion in DIR direction at minimum speed
ACT 01 DIR until the SW is released (open), the ACT action is
executed then a HardStop takes place
GoHome
GoMark
011
011
110
110
101
101
1
1
1
0
1
1
0
1
1
0
0
1
00
00
00
00
00
00
0
0
0
0
0
0
Brings the motor in HOME position
Brings the motor in MARK position
Resets the ABS_POS register (sets HOME position)
Device is reset to power-up conditions
Stops motor with a deceleration phase
Stops motor immediately
ResetPos
ResetDevice
SoftStop
HardStop
Puts the bridges in high impedance status after a
deceleration phase
SoftHiZ
101
0
0
00
0
HardHiZ
GetStatus
101
110
111
111
0
1
0
1
1
0
1
1
00
00
01
00
0
0
1
0
Puts the bridges in high impedance status immediately
Returns the status register value
RESERVED COMMAND
RESERVED
RESERVED
RESERVED COMMAND
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9.2.1
Command management
The host microcontroller can control motor motion and configure the L6482 through a
complete set of commands.
All commands are composed by a single byte. After the command byte, some bytes of
arguments should be needed (see Figure 25). Argument length can vary from 1 to 3 bytes.
Figure 25. Command with 3-byte argument
Argument byte 2
(MSB)
Argument byte 0
(LSB)
SDI
Command byte
Argument byte 1
(from host)
SDO
0x00
0x00
0x00
0x00
(to host)
AM15055v1
By default, the device returns an all zero response for any received byte, the only exceptions
are GetParam and GetStatus commands. When one of these commands is received, the
following response bytes represent the related register value (see Figure 26). Response
length can vary from 1 to 3 bytes.
Figure 26. Command with 3-byte response
SDI
Command byte
NOP
NOP
NOP
(from host)
Response byte 2
(MSB)
Response byte 0
(LSB)
SDO
0x00
Response byte 1
(to host)
AM15056v1
During response transmission, new commands can be sent. If a command requiring a
response is sent before the previous response is completed, the response transmission is
aborted and the new response is loaded into the output communication buffer (see
Figure 27).
Figure 27. Command response aborted
Command 1
(3 byte resp expected)
Command 2
(no resp. expected)
Command 3
(2 byte resp expected)
Command 4
(no resp. expected)
Command 5
(no resp. expected)
SDI
(from host)
Response byte 2
(MSB)
Response byte 1
(MSB)
Response byte 0
(LSB)
SDO
0x00
Response byte 1
(to host)
Command 1 response
is aborted
AM15057v1
When a byte that does not correspond to a command is sent to the IC it is ignored and the
WRONG_CMD flag in the STATUS register is raised (see Section 9.1.21).
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9.2.2
Nop
Table 48. Nop command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
From host
Nothing is performed.
9.2.3
SetParam (PARAM, VALUE)
Table 49. SetParam command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
PARAM
VALUE Byte 2 (if needed)
VALUE Byte 1 (if needed)
VALUE Byte 0
From host
The SetParam command sets the PARAM register value equal to VALUE; PARAM is the
respective register address listed in Table 11.
The command should be followed by the new register VALUE (most significant byte first).
The number of bytes composing the VALUE argument depends on the length of the target
register (see Table 11).
Some registers cannot be written (see Table 11); any attempt to write one of those registers
causes the command to be ignored and the WRONG_CMD flag to rise at the end of the
command byte, as if an unknown command code were sent (see Section 9.1.21).
Some registers can only be written in particular conditions (see Table 11); any attempt to
write one of those registers when the conditions are not satisfied causes the command to be
ignored and the NOTPERF_CMD flag to rise at the end of the last argument byte (see
Section 9.1.21).
Any attempt to set an inexistent register (wrong address value) causes the command to be
ignored and the WRONG_CMD flag to rise at the end of the command byte as if an
unknown command code were sent.
9.2.4
GetParam (PARAM)
Table 50. GetParam command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
PARAM
from host
to host
to host
to host
ANS Byte 2 (if needed)
ANS Byte 1 (if needed)
ANS Byte 0
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This command reads the current PARAM register value; PARAM is the respective register
address listed in Table 11.
The command response is the current value of the register (most significant byte first). The
number of bytes composing the command response depends on the length of the target
register (see Table 11).
The returned value is the register one at the moment of GetParam command decoding. If
register values change after this moment, the response is not updated accordingly.
All registers can be read anytime.
Any attempt to read an inexistent register (wrong address value) causes the command to be
ignored and the WRONG_CMD flag to rise at the end of the command byte as if an
unknown command code were sent.
9.2.5
Run (DIR, SPD)
Table 51. Run command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
1
0
0
0
DIR
from host
from host
from host
from host
X
X
X
X
SPD (Byte 2)
SPD (Byte 1)
SPD (Byte 0)
The Run command produces a motion at SPD speed; the direction is selected by the DIR
bit: '1' forward or '0' reverse. The SPD value is expressed in step/tick (format unsigned fixed
point 0.28) that is the same format as the SPEED register (Section 9.1.4).
Note:
The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED,
otherwise the Run command is executed at MAX_SPEED or MIN_SPEED respectively.
This command keeps the BUSY flag low until the target speed is reached.
This command can be given anytime and is immediately executed.
9.2.6
StepClock (DIR)
Table 52. StepClock command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
1
1
0
0
DIR
from host
The StepClock command switches the device in Step-clock mode (Section 6.7.5) and
imposes the forward (DIR = '1') or reverse (DIR = '0') direction.
When the device is in Step-clock mode, the SCK_MOD flag in the STATUS register is raised
and the motor is always considered stopped (Section 6.7.5 and 9.1.21).
The device exits Step-clock mode when a constant speed, absolute positioning or motion
command is sent through SPI. Motion direction is imposed by the respective StepClock
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command argument and can by changed by a new StepClock command without exiting
Step-clock mode.
Events that cause bridges to be forced into high impedance state (overtemperature,
overcurrent, etc.) do not cause the device to leave Step-clock mode.
The StepClock command does not force the BUSY flag low. This command can only be
given when the motor is stopped. If a motion is in progress, the motor should be stopped
and it is then possible to send a StepClock command.
Any attempt to perform a StepClock command when the motor is running causes the
command to be ignored and the NOTPERF_CMD flag to rise (Section 9.1.21).
9.2.7
Move (DIR, N_STEP)
Table 53. Move command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
0
0
DIR
from host
from host
from host
from host
X
X
N_STEP (Byte 2)
N_STEP (Byte 1)
N_STEP (Byte 0)
The move command produces a motion of N_STEP microsteps; the direction is selected by
the DIR bit ('1' forward or '0' reverse).
The N_STEP value is always in agreement with the selected step mode; the parameter
value unit is equal to the selected step mode (full, half, quarter, etc.).
This command keeps the BUSY flag low until the target number of steps is performed. This
command can only be performed when the motor is stopped. If a motion is in progress the
motor must be stopped and it is then possible to perform a move command.
Any attempt to perform a move command when the motor is running causes the command
to be ignored and the NOTPERF_CMD flag to rise (Section 9.1.21).
9.2.8
GoTo (ABS_POS)
Table 54. GoTo command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
0
0
0
0
0
from host
from host
from host
from host
X
X
ABS_POS (Byte 2)
ABS_POS (Byte 1)
ABS_POS (Byte 0)
The GoTo command produces a motion to the ABS_POS absolute position through the
shortest path. The ABS_POS value is always in agreement with the selected step mode; the
parameter value unit is equal to the selected step mode (full, half, quarter, etc.).
The GoTo command keeps the BUSY flag low until the target position is reached.
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This command can be given only when the previous motion command has been completed
(BUSY flag released).
Any attempt to perform a GoTo command when a previous command is under execution
(BUSY low) causes the command to be ignored and the NOTPERF_CMD flag to rise
(Section 9.1.21).
9.2.9
GoTo_DIR (DIR, ABS_POS)
Table 55. GoTo_DIR command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
0
1
0
0
DIR
from host
from host
from host
from host
X
X
ABS_POS (Byte 2)
ABS_POS (Byte 1)
ABS_POS (Byte 0)
The GoTo_DIR command produces a motion to the ABS_POS absolute position imposing a
forward (DIR = '1') or a reverse (DIR = '0') rotation. The ABS_POS value is always in
agreement with the selected step mode; the parameter value unit is equal to the selected
step mode (full, half, quarter, etc.).
The GoTo_DIR command keeps the BUSY flag low until the target speed is reached. This
command can be given only when the previous motion command has been completed
(BUSY flag released).
Any attempt to perform a GoTo_DIR command when a previous command is under
execution (BUSY low) causes the command to be ignored and the NOTPERF_CMD flag to
rise (Section 9.1.21).
9.2.10
GoUntil (ACT, DIR, SPD)
Table 56. GoUntil command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
0
ACT
0
1
DIR
from host
from host
from host
from host
X
X
X
X
SPD (Byte 2)
SPD (Byte 1)
SPD (Byte 0)
The GoUntil command produces a motion at SPD speed imposing a forward (DIR = '1') or a
reverse (DIR = '0') direction. When an external switch turn-on event occurs (Section 6.14),
the ABS_POS register is reset (if ACT = '0') or the ABS_POS register value is copied into
the MARK register (if ACT = '1'); the system then performs a SoftStop command.
The SPD value is expressed in step/tick (format unsigned fixed point 0.28) that is the same
format as the SPEED register (Section 9.1.4).
The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED,
otherwise the target speed is imposed at MAX_SPEED or MIN_SPEED respectively.
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If the SW_MODE bit of the CONFIG register is set low, the external switch turn-on event
causes a HardStop interrupt instead of the SoftStop one (Section 6.14 and Section 9.1.20).
This command keeps the BUSY flag low until the switch turn-on event occurs and the motor
is stopped. This command can be given anytime and is immediately executed.
9.2.11
ReleaseSW (ACT, DIR)
Table 57. ReleaseSW command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
1
ACT
0
1
DIR
from host
The ReleaseSW command produces a motion at minimum speed imposing a forward (DIR =
'1') or reverse (DIR = '0') rotation. When SW is released (opened) the ABS_POS register is
reset (ACT = '0') or the ABS_POS register value is copied into the MARK register (ACT =
'1'); the system then performs a HardStop command.
Note that, resetting the ABS_POS register is equivalent to setting the HOME position.
If the minimum speed value is less than 5 step/s or low speed optimization is enabled, the
motion is performed at 5 step/s.
The ReleaseSW command keeps the BUSY flag low until the switch input is released and
the motor is stopped.
9.2.12
GoHome
Table 58. GoHome command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
1
0
0
0
0
from host
The GoHome command produces a motion to the HOME position (zero position) via the
shortest path.
Note that, this command is equivalent to the “GoTo(0…0)” command. If a motor direction is
mandatory, the GoTo_DIR command must be used (Section 9.2.9).
The GoHome command keeps the BUSY flag low until the home position is reached. This
command can be given only when the previous motion command has been completed. Any
attempt to perform a GoHome command when a previous command is under execution
(BUSY low) causes the command to be ignored and the NOTPERF_CMD to rise
(Section 9.1.21).
9.2.13
GoMark
Table 59. GoMark command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
1
1
0
0
0
from host
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The GoMark command produces a motion to the MARK position performing the minimum
path.
Note that, this command is equivalent to the “GoTo (MARK)” command. If a motor direction
is mandatory, the GoTo_DIR command must be used.
The GoMark command keeps the BUSY flag low until the MARK position is reached. This
command can be given only when the previous motion command has been completed
(BUSY flag released).
Any attempt to perform a GoMark command when a previous command is under execution
(BUSY low) causes the command to be ignored and the NOTPERF_CMD flag to rise
(Section 9.1.21).
9.2.14
ResetPos
Table 60. ResetPos command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
1
0
0
0
from host
The ResetPos command resets the ABS_POS register to zero. The zero position is also
defined as the HOME position (Section 6.5).
9.2.15
ResetDevice
Table 61. ResetDevice command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
0
0
0
0
0
from host
The ResetDevice command resets the device to power-up conditions (Section 6.1).
Note:
At power-up the power bridges are disabled.
9.2.16
SoftStop
Table 62. SoftStop command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
1
0
0
0
0
from host
The SoftStop command causes an immediate deceleration to zero speed and a consequent
motor stop; the deceleration value used is the one stored in the DEC register
(Section 9.1.6).
When the motor is in high impedance state, a SoftStop command forces the bridges to exit
from high impedance state; no motion is performed.
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This command can be given anytime and is immediately executed. This command keeps
the BUSY flag low until the motor is stopped.
9.2.17
HardStop
Table 63. HardStop command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
1
1
0
0
0
from host
The HardStop command causes an immediate motor stop with infinite deceleration.
When the motor is in high impedance state, a HardStop command forces the bridges to exit
high impedance state; no motion is performed.
This command can be given anytime and is immediately executed. This command keeps
the BUSY flag low until the motor is stopped.
9.2.18
SoftHiZ
Table 64. SoftHiZ command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
0
0
0
0
from host
The SoftHiZ command disables the power bridges (high impedance state) after a
deceleration to zero; the deceleration value used is the one stored in the DEC register
(Section 9.1.6). When bridges are disabled, the HiZ flag is raised.
When the motor is stopped, a SoftHiZ command forces the bridges to enter high impedance
state.
This command can be given anytime and is immediately executed. This command keeps
the BUSY flag low until the motor is stopped.
9.2.19
HardHiZ
Table 65. HardHiZ command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
0
0
from host
The HardHiZ command immediately disables the power bridges (high impedance state) and
raises the HiZ flag.
When the motor is stopped, a HardHiZ command forces the bridges to enter high
impedance state.
This command can be given anytime and is immediately executed.
This command keeps the BUSY flag low until the motor is stopped.
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9.2.20
GetStatus
Table 66. GetStatus command structure
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
0
0
0
0
from host
STATUS MSByte
STATUS LSByte
to host
to host
The GetStatus command returns the Status register value.
The GetStatus command resets the STATUS register warning flags. The command forces
the system to exit from any error state. The GetStatus command DOES NOT reset the HiZ
flag.
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Package mechanical data
L6482
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 67. HTSSOP38 mechanical data
mm
Symbol
Min.
Typ.
Max.
A
A1
A2
b
-
1.1
0.15
0.95
0.27
0.20
9.80
4.50
-
0.05
0.85
0.17
0.09
9.60
4.30
-
-
0.9
-
c
-
D
9.70
4.40
0.50
6.40
0.60
6.50
3.20
-
E1
e
E
-
-
L
0.50
6.40
3.10
0°
0.70
6.60
3.30
8°
P
P1
∅
Figure 28. HTSSOP38 package dimensions
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Package mechanical data
Figure 29. HTSSOP38 footprint
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Revision history
L6482
11
Revision history
Table 68. Document revision history
Date
Revision
Changes
08-Oct-2012
1
Initial release.
Changed the title.
Inserted footnote in Table 2 and Table 4
Removed Tj parameter in Table 3.
Updated Section 9.1.10 and Section 9.1.15.
Updated Table 17.
19-Dec-2012
2
Minor text changes.
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