L6591TR [STMICROELECTRONICS]
PWM controller for ZVS half-bridge; PWM控制器ZVS半桥
| 型号： | L6591TR |
| 厂家： | 
ST |
| 描述： | PWM controller for ZVS half-bridge |
| 文件： | 总32页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6591
PWM controller for ZVS half-bridge
Features
■ Complementary PWM control for soft-switched
half-bridge with programmable dead-time
■ Up to 500 kHz operating frequency
■ On-board high-voltage start-up
■ Advanced light load management
■ Adaptive UVLO
SO16 narrow
■ 600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dV/dt
immunity
■ Pulse-by-pulse OCP
■ OLP (latched or autorestart)
■ Transformer saturation detection
■ Interface with PFC controller
■ Latched disable input
■ SO16N package
Applications
■ High power AC-DC adapter/charger
■ Desktop PC, entry-level server
■ Telecom SMPS
■ Input for power-on sequencing or brownout
protection
■ Programmable soft-start
■ 4 % precision external reference
Figure 1.
Typical application circuit
HV
VCC
9
16
5
2
CLK
OSC
DIS
TIMING
25 V
Vref
HV generator ON/O FFand
adaptive UV LOmanagement
VREG
6
VREF
BOOT
Vcc_OK
Low
UVLO
R
Synchronous
bootstrap diode
+
S
Q
4.5V
1.5V
-
DIS
15
HICCUP
-
BLANKI NG
+
S
Q
14
PWM _CT L
+
ISEN
LEVEL
SHIFTER
R
HVG
3
8
PWM
13
-
Vc c_O K
DIS
FGND
SHUT DO WN
R
PF C_STO P
Q
V CC
S
OCP2
LI NE_ OK
OCP2
DI S
VREG
BURST- M O DE CT RL
10
11
0.32mA
Ilimre f
0.8V max.
+
-
+
OCP
-
LV G
GND
1.5V
Low
UV LO
LI NE_OK
-
1.75V
1
-
LINE
+
3R
+
SOFT-START
R
15µA
2.0V
4
7
SS
COMP
June 2008
Rev 1
1/32
www.st.com
32
Contents
L6591
Contents
1
2
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
High-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PWM comparator, PWM latch and hiccup-mode OCP . . . . . . . . . . . . . . . 17
Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Oscillator and dead-time programming . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 23
6
7
8
9
Summary of L6591 power management functions . . . . . . . . . . . . . . . 25
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
L6591
Device description
1
Device description
The L6591 is a double-ended PWM controller specific for the soft-switched half-bridge
topology. It provides complementary PWM control, where the high-side switch is driven ON
for a duty cycle D and the low-side switch for a duty cycle 1-D, with D 50 %. An externally
programmable dead-time inserted between the turn-off of one switch and the turn-on of the
other one guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage
floating structure able to withstand more than 600 V with a synchronous-driven high-voltage
DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the designer to set the operating frequency of the converter by means of an
externally programmable oscillator: the maximum duty cycle is digitally clipped at 50 % by a
T-flip-flop, so that the operating frequency will be half that of the oscillator.
At very light load the IC enters a controlled burst-mode operation that, along with the built-in
non-dissipative high-voltage start-up circuit and the low quiescent current, helps keep low
the consumption from the mains and be compliant with energy saving recommendations.
To allow compliance with these standards in two-stage power-factor-corrected systems as
well, an interface with the PFC controller is provided that enables to switch off the pre-
regulator between one burst and the following one.
An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the
self-supply voltage with the output load, due to transformer's parasitic.
IC's protection functions include: not-latched input undervoltage (brownout), a first-level
OCP with delayed shutdown able to protect the system during overload and short circuit
conditions (either auto-restart or latch mode can be selected) and a second-level OCP that
latches off the IC when the transformer saturates or one of the secondary diodes fails short.
Finally, a latched disable function allows easy implementation of OTP or OVP.
Programmable soft-start and digital leading-edge blanking on current sense input pin
complete the equipment of the IC.
Figure 2.
Typical system block diagram
PFC PRE-REGULATOR
ZVS HALF-BRIDGE
Voutdc
inac
V
PW M is turned off in case of PFC's
anomalous operation, for safety
L6561/2
or
L6563
L6591
PFC can be turned off at light
load to ease compliance with
energy saving regulations.
3/32
Pin settings
L6591
2
Pin settings
2.1
Connection
Figure 3.
Pin connection (top view)
LINE
DIS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HVSTART
BOOT
HVG
ISEN
SS
FGND
N.C.
OSC
VREF
GND
COMP
PFC_STOP
LVG
Vcc
2.2
Functions
Table 1.
Pin N.
Pin functions
Name
Function
Line sensing input. The pin is to be connected to the high-voltage input bus
with a resistor divider. A voltage below 1.25 V shuts down the IC, lowers its
consumption and discharges the soft-start capacitor. IC’s operation is re-
enabled as the voltage exceeds 1.25 V. The comparator is provided with
current hysteresis: an internal 15 µA current generator is ON as long as the
voltage applied at the pin is below 1.25 V and is OFF if this value is
exceeded. Bypass the pin with a capacitor to GND (#11) to reduce noise
pick-up. The pin is intended for either power-on sequencing in systems with
PFC, or brownout protection. Tie to Vcc (#9) with a 220 to 330 kW resistor if
the function is not used.
1
2
LINE
Latched device shutdown. Internally the pin connects a comparator that,
when the voltage on the pin exceeds 4.5 V, shuts the IC down and brings its
consumption to a value barely higher than before start-up. The information
is latched and it is necessary to recycle the input power to restart the IC: the
latch is removed as the voltage on the Vcc pin (#9) goes below the UVLO
threshold. Connect the pin to GND (#11) if the function is not used.
DIS
4/32
L6591
Pin settings
Table 1.
Pin N.
Pin functions (continued)
Name
Function
Current sense (PWM comparator) input. The voltage on this pin is internally
compared with an internal reference derived from the voltage on pin COMP
and when they are equal the high-side gate drive output (previously
asserted high by the clock signal generated by the oscillator) is driven low to
turn off the upper power MOSFET; the lower MOSFET is turned on after a
delay programmed by the timing capacitor at pin OSC (#5). The pin is
equipped with 200 ns blanking time for improved noise immunity. A second
comparator referenced at 0.8 V turns off the upper MOSFET if the voltage
at the pin exceeds the threshold, overriding the PWM comparator (pulse-by-
pulse OCP). A third comparison level located at 1.5 V shuts the device
down and brings its consumption almost to a “before start-up” level (hiccup-
mode OCP) to prevent uncontrolled current rise. A logic circuit improves
sensitivity to temporary disturbances.
3
ISEN
Soft-start. An internal 20 µA generator charges an external capacitor
connected between the pin and GND (#11) generating a voltage ramp.
During the ramp, the internal reference for pulse-by-pulse OCP (see pin #3,
ISEN) rises linearly starting from zero to its final value, thus causing the
duty cycle of the upper MOSFET to rise starting from zero as well, and all
the functions monitoring pin COMP (#7) are disabled. The same capacitor
is used to delay IC’s shutdown (latch-off or auto-restart mode selectable)
after detecting an overcurrent condition. The SS capacitor is quickly
discharged as the chip goes into UVLO.
4
SS
Oscillator pin. A resistor to VREF (#6) and a capacitor from the pin to GND
(#11) define the oscillator frequency. The maximum duty cycle is limited
below 50 % by an internal T-flip-flop. As a result, the switching frequency will
be half that of the oscillator. The capacitor value defines the dead-time
separating the conduction state of either MOSFET. This capacitor should
not be lower than 220 pF.
5
6
OSC
Voltage reference. An internal generator furnishes an accurate voltage
reference (5 V 4 %, all inclusive) that can be used to supply up to 5 mA to
an external circuit. A small film capacitor (0.1 µF typ.), connected between
this pin and GND (#11) is recommended to ensure the stability of the
generator and to prevent noise from affecting the reference.
VREF
Control input for PWM regulation. The pin is to be driven by the
phototransistor (emitter-grounded) of an octocoupler to modulate the
voltage by modulating the current sunk from (sourced by) the pin (0.4 mA
typ.). It is recommended to place a small filter capacitor between the pin
and GND (#11), as close to the IC as possible to reduce switching noise
pick up, to set a pole in the output-to-control transfer function. A voltage
lower than 1.75 V shuts down the IC and reduces its current consumption.
The chip restarts as the voltage exceeds 1.8 V. This function realizes burst-
mode operation at light load.
7
COMP
Open-drain ON/OFF control of PFC controller. This pin is intended for
temporarily stopping the PFC controller at light load in systems comprising
a PFC pre-regulator, during burst-mode operation (see pin COMP, #7). The
pin, normally open, goes low if the voltage on COMP is lower than 1.75 V
and opens when the voltage on pin COMP exceeds 1.8V. Whenever the IC
is shut down (SS > 5 V, DIS>4.5, ISEN >1.5 V) the pin is low as well,
provided the supply voltage of the IC is above the restart threshold (typ. 5
V). It is open during UVLO. Leave the pin open if not used
8
PFC_STOP
5/32
Pin settings
L6591
Table 1.
Pin N.
Pin functions (continued)
Name
Function
Supply voltage of both the signal part of the IC and the low-side gate driver.
The internal high voltage generator charges an electrolytic capacitor
connected between this pin and GND (#11) as long as the voltage on the
pin is below the start-up threshold of the IC, after that it is disabled and the
chip turns on. Sometimes a small bypass capacitor (0.1 µF typ.) to GND
might be useful to get a clean bias voltage for the signal part of the IC. The
minimum operating voltage (UVLO) is adapted to the loading conditions of
the converter to ease burst-mode operation, during which the available
supply voltage for the IC drops.
9
Vcc
Low-side gate-drive output. The driver is capable of 0.3 A min. source and
0.8A min. sink peak current to drive the gate of the lower MOSFET of the
half-bridge leg. The pin is actively pulled to GND (#11) during UVLO.
10
11
LVG
Chip ground. Current return for both the low-side gate-drive current and the
bias current of the IC. All of the ground connections of the bias components
should be tied to a track going to this pin and kept separate from any pulsed
current return.
GND
High-voltage spacer. The pin is not connected internally to isolate the group
of high-voltage pins and comply with safety regulations (creepage distance)
on the PCB.
12
13
N.C.
High-side gate-drive floating ground. Current return for the high-side gate-
drive current. Layout carefully the connection of this pin to avoid too large
spikes below ground.
FGND
High-side floating gate-drive output. The driver is capable of 0.3 A min.
source and 0.8 A min. sink peak current to drive the gate of the upper
MOSFET of the half-bridge leg. A pull-down resistor between this pin and
pin 13 (FGND) makes sure that the gate is never floating during UVLO.
14
15
HVG
High-side gate-drive floating supply voltage. The bootstrap capacitor
connected between this pin and pin 13 (FGND) is fed by an internal
synchronous bootstrap diode driven in-phase with the low-side gate-drive.
This patented structure can replace the normally used external diode.
BOOT
High-voltage start-up. The pin is to be connected directly to the rectified
mains voltage. A 0.8 mA internal current source charges the capacitor
connected between pin Vcc (#9) and GND (#11) until the voltage on the Vcc
16
HVSTART pin reaches the start-up threshold. Normally it is re-enabled when the
voltage on the Vcc pin falls below 5 V, except under latched shutdown
conditions, in which case it is re-enabled as the Vcc voltage falls 1 V below
the start-up threshold to keep the latch active.
6/32
L6591
Electrical data
3
Electrical data
3.1
Maximum ratings
Table 2.
Symbol
Absolute maximum ratings
Pin
Parameter
Value
Unit
VHVSTART
IHVS
16
16
15
13
13
9
Voltage range (referred to ground)
Input current
-0.3 to 700
Self-limited
-1 to 618
-3 to VBOOT -18
50
V
A
VBOOT
VFGND
dVFGND/dt
VCC
Floating supply voltage
Floating ground voltage
Floating ground slew rate
IC supply voltage (Icc = 20 mA)
V
V
V/ns
V
Self-limited
Self-limited
Self-limited
Self-limited
-0.3 to 7
I
HVG, ILVG
10, 14 Gate-drives peak current
A
IPFC_STOP
VLINEmax
---
8
1
Max. sink current (VPFC_STOP = 25 V)
Maximum pin voltage (Ipin ≤ 1 mA)
A
V
2 to 7 Analog inputs and outputs
V
ISEN
PTOT
3
Current sense input
-3 to 7
V
Power dissipation @ TA = 50 °C
Junction temperature operating range
Storage temperature
0.75
W
°C
°C
TJ
-40 to 150
-55 to 150
TSTG
3.2
Thermal data
Table 3.
Symbol
RthJA
Thermal data
Parameter
Value
Unit
Thermal resistance junction to ambient (1)
120
°C/W
1. Value depending on PCB copper area and thickness.
7/32
Electrical characteristics
L6591
4
Electrical characteristics
Table 4.
Electrical characteristics
(T = 0 to 105 °C, Vcc = 15 V, V
= 12 V, C
= C
= 1 nF; R = 22 kΩ,
LVG T
J
BOOT
HVG
C = 330 pF; unless otherwise specified)
T
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
IC supply voltage
VCOMP > VCOMPL
11.3
9.2
13
22
22
Operating range after
turn-on
Vcc
V
V
V
VCOMP = VCOMPL
(1)
VccOn Turn-on threshold
VccOff Turn-off threshold
14
10.5
8.7
3.5
25
15
(1)
V
> VCOMPL
9.7
8.2
3.0
22
11.3
9.2
COMP
(1) VCOMP = VCOMPL
VCOMP > VCOMPL
Icc = 15 mA
Hys
VZ
Hysteresis
V
V
Vcc clamp voltage
28
Supply current
Before turn-on,
Vcc = 12.5 V
Istart-up Start-up current
190
250
µA
Iq
Quiescent current
After turn-on
2.8
5.3
3.5
8
mA
mA
Icc
Operating supply current
V
DIS > 4.5 V,
0.35
mA
VISEN > 1.5 V
Shutdown quiescent
current
Iqdis
V
COMP = 1.64 V
2.2
mA
mA
VLINE < 1.44 V
0.35
High-side floating gate-drive supply
VBOOT Operating supply voltage
IqBOOT Quiescent current
Referred to FGND pin
VFGND = 0
17
V
500
125
800
µA
VFGND = VBOOT
VHVG = 600 V
=
ILK
High-voltage leakage
10
µA
Synchronous bootstrap
diode on-resistance
RDS(on)
VLVG = HIGH
Ω
High-voltage start-up generator
VHV Breakdown voltage
IHV < 100 µA
IVcc < 100 µA
700
60
V
V
VHVstart Start voltage
75
90
1
VHV > VHvstart
Vcc> 3V
,
,
Icharge Vcc charge current
0.55
0.75
mA
VHV > VHvstart
Vcc> 3 V
1.6
IHV, ON ON-state current
mA
V
HV > VHvstart, Vcc = 0
0.8
40
IHV, OFF Leakage current (OFF-state) VHV = 400 V
µA
8/32
L6591
Electrical characteristics
Table 4.
Symbol
Electrical characteristics (continued)
(T = 0 to 105 °C, Vcc = 15 V, V = 12 V, C
= C
= 1 nF; R = 22 kΩ,
T
J
BOOT
HVG
LVG
C = 330 pF; unless otherwise specified)
T
Parameter
Test condition
Min
Typ
Max
Unit
(1)
VCCrestart HV generator restart voltage
4.4
5
5.6
V
V
(1) After DIS tripping
12.2
13.2
14.2
Reference voltage
(2) TJ = 25 °C;
IREF = 1 mA
VREF
Output voltage
4.9
5
5.1
V
Vcc= 9.2 to 22 V,
IREF = 1 to 5 mA
VREF
IREF
Total variation
4.8
10
5.2
30
V
mA
V
Short circuit current
Sink capability in UVLO
VREF = 0
Vcc = 6 V;
Isink = 0.5 mA
0.2
0.5
Current sense comparator
IISEN
tLEB
Input bias current
VISEN = 0
-1
µA
After VHVG low-to-high
transition
Leading edge blanking
200
ns
td(H-L) Delay to output
Gain
170
4.2
ns
V/V
V
3.8
0.76
1.4
4
(2)
VISENx Maximum signal
VISENdis Hiccup-mode OCP level
V
= 5 V
0.8
1.5
0.84
1.65
COMP
(2)
V
PWM control and burst-mode control
VCOMPH Maximum level
ICOMP = 0
5.5
V
µA
kΩ
V
ICOMP Source current
VCOMP = 2 V
240
320
25
400
1.82
50
RCOMP Dynamic resistance
VCOMPBon Burst-mode on threshold
VCOMP = 2 to 4 V
(2)
V
falling
1.68
45
1.75
70
COMP
Hys
Burst-mode hysteresis
Maximum duty cycle
V
COMP rising
mV
%
Dmax
VCOMP = 5 V
Adaptive UVLO
(2)
VCOMPL UVLO shift threshold
Line sensing
1.9
2
2.1
V
Vth
Threshold voltage
Current hysteresis
Voltage rising or falling
Vcc > 5 V
1.22
13.2
2.8
1.25
14.7
3
1.28
16.2
V
µA
V
IHys
Vclamp Clamp level
ILINE = 1 mA
9/32
Electrical characteristics
Table 4.
L6591
Electrical characteristics (continued)
(T = 0 to 105 °C, Vcc = 15 V, V = 12 V, C
= C
= 1 nF; R = 22 kΩ,
T
J
BOOT
HVG
LVG
C = 330 pF; unless otherwise specified)
T
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
DIS function
IOTP
Vth
Input bias current
Disable threshold
VDIS = 0 to Vth
-1
µA
4.275
4.5
4.725
V
Oscillator and dead-time programming
fosc
Oscillation frequency
TJ = 25 °C
170
168
180
180
3
190
192
kHz
kHz
V
Vcc = 9.2 to 22 V
(2)
Vpk
Vvy
Oscillator peak voltage
Oscillator valley voltage
2.85
0.75
3.15
1.05
(2)
0.9
0.42
V
Dead-time
(VHVG high-to-low to VLVG
low-to-high transition)
CT = 1 nF
CT = 1 nF
1.0
0.42
1.0
Tdead
µs
Dead-time (VLVG high-to-low
to VHVG low-to-high
transition)
Soft-start
TJ = 25 °C, VSS < 1.5 V,
VCOMP = 4 V
14
17
20
ISSC
Charge current
µA
TJ = 25 °C, VSS > 1.5 V,
VCOMP = VCOMPH
3.0
3.0
4.2
5.4
5.4
ISsdis
Discharge current
VSS > 1.5 V
4.2
2
µA
V
VSsclamp High saturation voltage
VSSDIS Disable level
VCOMP = 4 V
(2)
V
= VCOMPH
4.85
5
5.15
V
COMP
VSSLAT Latch-off level
VCOMP = VCOMPH
6.4
V
PFC_STOP function
V
PFC_STOP = Vcc,
VCOMP = 2 V
PFC_STOP = 2 mA
VCOMP = 1.5 V
Ileak
High level leakage current
Low saturation level
1
µA
I
VL
0.1
V
Low-side gate driver (voltages referred to GND)
VLVGL Output low voltage
VLVGH Output high voltage
Isourcepk Peak source current (3)
Isinkpk Peak sink current (3)
Isink = 200 mA
Isource = 5 mA
1.0
V
V
12.8
-0.3
0.8
13.3
40
A
A
tf
Fall time
ns
10/32
L6591
Electrical characteristics
Table 4.
Electrical characteristics (continued)
(T = 0 to 105 °C, Vcc = 15 V, V = 12 V, C
= C
= 1 nF; R = 22 kΩ,
T
J
BOOT
HVG
LVG
C = 330 pF; unless otherwise specified)
T
Symbol
Parameter
Rise time
Test condition
Min
Typ
Max
Unit
tr
80
ns
Vcc = 0 to VccOn
Isink = 1 mA
,
UVLO saturation
1.1
V
High-side gate driver (voltages referred to FGND)
VHVGL Output low voltage
VHVGH Output high voltage
Isourcepk Peak source current (3)
Isinkpk Peak sink current (3)
Isink = 200 mA
Isource = 5 mA
1.5
V
V
11
-0.3
0.8
11.9
A
A
tf
Fall time
40
80
25
ns
ns
kΩ
tr
Rise time
Pull-down resistor
1. Parameters in tracking each other
2. Parameters in tracking each other
3. Parameters guaranteed by design
11/32
Application information
L6591
5
Application information
The L6591 is an advanced current-mode PWM controller specific for fixed-frequency, peak-
current-mode-controlled ZVS half-bridge converters. In these converters the switches
(MOSFET’s) are controlled with complementary duty cycle: the high-side MOSFET is driven
ON for a duty cycle D and the low-side MOSFET for a duty cycle 1-D. For a proper operation
the maximum allowed duty cycle must be limited below 50 %.
An externally programmable dead-time T inserted between the turn-off of one MOSFET
D
and the turn-on of the other one ensures soft-switching and enables high-frequency
operation with high efficiency and low EMI emissions. See Section 5.6: Oscillator and dead-
time programming on page 19 section for more information on how to program T .
D
The device is able to operate in different modes (Figure 4), depending on the converter’s
load conditions:
1. Fixed frequency at heavy load. A relaxation oscillator, externally programmable with a
capacitor and a resistor generates a sawtooth and releases clock pulses during the
falling edges of the sawtooth. In this region the low-side MOSFET is turned off by the
even pulses of the clock signal and the high-side MOSFET is turned on after a delay;
the high-side MOSFET is turned off and, after a delay, the low-side MOSFET is turned
on in response to the control loop.
2. Burst-mode control with no or very light load. When the load is extremely light or
disconnected, the converter will enter a controlled on/off operation with fixed duty cycle,
where a series of few switching cycles are spaced out by long periods where both
MOSFET’s are in OFF-state. A load decrease will be then translated into a frequency
reduction, which can go down even to few hundred hertz, thus minimizing all
frequency-related losses and making it easier to comply with energy saving
regulations. Being the peak current very low, no issue of audible noise arises.
Figure 4.
Multi-mode operation
12/32
L6591
Application information
5.1
High-voltage start-up generator
Figure 5 shows the internal schematic of the high-voltage start-up generator (HV generator).
It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 MW resistor,
with a temperature-compensated current generator connected to its source.
With reference to the timing diagram of Figure 6, when power is first applied to the converter
the voltage on the bulk capacitor (Vin) builds up and, as it reaches about 80 V, the HV
generator is enabled to operate (HV_EN is pulled high) and draws about 1 mA. This current,
diminished by the IC consumption, charges the bypass capacitor connected between pin
Vcc (9) and ground and makes its voltage rise almost linearly.
As the Vcc voltage reaches the start-up threshold (13.5 V typ.) the IC starts operating and
the HV generator is cut off by the Vcc_OK signal asserted high. The IC is powered by the
energy stored in the Vcc capacitor until the self-supply circuit develops a voltage high
enough to sustain the operation. The residual consumption of this circuit is just the one on
the 15 MW resistor (≈10 mW at 400 Vdc), typically 50-70 times lower, under the same
conditions, as compared to a standard start-up circuit made with an external dropping
resistor.
Figure 5.
High-voltage start-up generator: internal schematic
HVSTART
16
L6591
15 MΩ
Vcc_OK
HV_EN
IHV
9
Vcc
CONTROL
11
Icharge
GN D
13/32
Application information
Figure 6.
L6591
Timing diagram: normal power-up and power-down sequences
Vin
VHstart
Vcc
t
regulation is lost here
Vccon
Vccoff
Vcc re s ta r t
t
PFC_STOP
HVG, LVG
HV_EN
t
t
t
t
Vcc_OK
I
charge
0.75 mA
Power-on
Normal
Power-off
operation
At converter power-down the system will lose regulation as soon as the input voltage is so
low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop
and stop IC’s activity as it falls below the UVLO threshold (10.5 V typ.). The Vcc_OK signal
is de-asserted as the Vcc voltage goes below a threshold Vcc
located at about 5 V. The
rest
HV generator can now restart but, if Vin < Vin
, as shown in Figure 6, HV_EN is de-
start
asserted too and the HV generator is disabled. This prevents converter’s restart attempts
and ensures monotonic output voltage decay at power-down.
The low restart threshold Vcc
ensures that, during short circuits, the restart attempts of
rest
the L6591 will have a very low repetition rate, as shown in the timing diagram of Figure 7,
and that the converter will work safely with extremely low power throughput.
The restart threshold of the HV generator is changed when any latched disable function of
the IC is invoked to ensure a real latch-off. For more details see “Latched shutdown” section.
14/32
L6591
Application information
Figure 7.
Timing diagram showing short-circuit behavior
(SS pin clamped below 5 V)
Vcc
LVG ,HVG
Vcc_OK
5.2
Operation at no load or very light load
When the PWM control voltage at pin COMP falls below a threshold located at 1.75 V, the IC
is disabled with both the high-side and the low-side MOSFET kept in OFF-state, the
oscillator stopped and the quiescent consumption very much reduced to minimize Vcc
capacitor discharge.
The control voltage now will increase as a result of the feedback reaction to the energy
delivery stop and, as it exceeds 1.82 V, the IC will restart switching. After a while, the control
voltage will go down again in response to the energy burst and stop the IC. In this way the
converter will work in a burst-mode fashion with a nearly constant peak current. A further
load decrease will then cause a frequency reduction, which can go down even to few
hundred hertz, thus minimizing all frequency-related losses and making it easier to comply
with energy saving regulations. The timing diagram of Figure 8 illustrates this kind of
operation, showing the most significant signals.
If it is necessary to decrease the intervention threshold of the burst-mode operation, this can
be done by adding a small DC offset on the current sense pin as shown in Figure 9.
Note: The offset reduces the available dynamics of the current signal; thereby, the value of
the sense resistor must be determined taking this offset into account.
15/32
Application information
L6591
Figure 8.
Load-dependent operating modes: timing diagram
COMP
1.82V
1.75V
t
fosc
t
t
LVG, HVG
PF C_STO P
PFC
GATE-DR IVE
Fix. Freq. Mode
Burst-mode
Fix. Freq. Mode
Figure 9.
Addition of an offset to the current sense lowers the burst-mode
operation threshold
R
V
= Vref
o
R + Rc
Vref
6
LVG
10
4
Rc
L6591
R
11
ISEN
Rs
GND
To help the designer meet energy saving requirements even in power-factor-corrected
systems, where a PFC pre-regulator precedes the DC-DC converter, the L6591 allows that
the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the
no-load consumption of this stage (0.5÷1 W). There is no compliance issue in that because
EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is
envisaged when the converter operates with light or no load.
To do so, the L6591 provides the PFC_STOP (#8) pin: it is an open collector output,
normally open, that is asserted low when the IC is idle during burst-mode operation. This
signal will be externally used for switching off the PFC controller and the pre-regulator as
shown in Figure 10. When the L6591 is in UVLO the pin is kept open, to let the PFC
controller starts first.
16/32
L6591
Application information
Figure 10. How the L6591 can switch off a PFC controller at light load
ZCD
L6591
Vref
8
PFC_STOP
5.6 kΩ
L6562
6
47 kΩ
BC547
L6591
BC547
8
PFC_STOP
PFC_OK
(AC_OK)
L6563
5.3
5.4
PWM control block
The device is specific for secondary feedback. Typically, there is a TL431 at the secondary
side and an optocoupler that transfers output voltage information to the PWM control at the
primary side, crossing the isolation barrier. The PWM control input (pin #7, COMP) is driven
directly by the phototransistor’s collector (the emitter is grounded) to modulate the duty
cycle. It is recommended to place a small filter capacitor between the pin and GND (#11), as
close to the IC as possible to reduce switching noise pick up, to set a pole in the output-to-
control transfer function.
PWM comparator, PWM latch and hiccup-mode OCP
The PWM comparator senses the voltage across the current sense resistor (Rs) and, by
comparing it with the programming signal derived by the voltage on pin COMP (#7),
determines the exact time when the high-side MOSFET is to be switched off. The PWM
latch avoids spurious switching, which might be caused by the noise generated (“double-
pulse suppression”).
A second comparator senses the voltage on the current sense input and shuts the IC down
if the voltage at the pin exceeds 1.5 V. Such an anomalous condition is typically generated
by either a short circuit of one of the secondary rectifiers or a shorted secondary winding or
a saturated transformer. This condition is latched as long as the IC is supplied; hence if the
IC is supplied by an external source it is necessary to disconnect the source to restart the
IC.
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped the protection circuit enters a “warning state”. If in the
next switching cycle the comparator is not tripped, a temporary disturbance is assumed and
the protection logic will be reset in its idle state; if the comparator will be tripped again a real
malfunction is assumed and the L6591 will be stopped.
If the device is self-supplied no energy is coming from the self-supply circuit, then the
voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time,
which clears the latch. The internal start-up generator is still off, then the Vcc voltage still
needs to go below its restart voltage before the Vcc capacitor is charged again and the IC
restarted. Ultimately, either of the above mentioned failures will result in a low-frequency
intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.
The timing diagram of Figure 11 illustrates this operation.
17/32
Application information
Figure 11. Hiccup-mode OCP: timing diagram (device self-supplied)
L6591
Sec ondary diode is s horted here
Vcc
Vccon
Vccoff
Vc c
resta rt
t
VC S
1.5 V
t
LVG, HV G
OCP latch
t
t
Vcc_OK
PFC_S top
t
t
5.5
Latched shutdown
The L6591 is equipped with a comparator having the non-inverting input externally available
at the pin DIS (#2) and with the inverting input internally referenced to 4.5 V. As the voltage
on the pin exceeds the internal threshold, the IC is immediately shut down and its
consumption reduced at a low value.
The information is latched and it is necessary to let the voltage on the Vcc pin go below the
UVLO threshold to reset the latch and restart the IC. To keep the latch supplied as long as
the converter is connected to the input source, the HV generator is activated periodically so
that Vcc oscillates between the start-up threshold V
and V
– 1 V. It is then
ccON
ccON
necessary to disconnect the converter from the input source to restart the IC. This operation
is shown in the timing diagram of Figure 12. Activating the HV generator in this way cuts its
power dissipation approximately by three (as compared to the case of continuous
conduction) and keeps peak silicon temperature close to the average value.
18/32
L6591
Application information
Figure 12. Operation after latched disable activation: timing diagram
DIS
4.5V
V cc
t
Vccon
Vccon - 1
Disable latch is reset here
HV generatoris turned on
Vcco ff
Vccre sta rt
LVG, HVG
t
t
HV gen erator tu rn-on i s disabl ed here
Inpu t sou rce i s re moved he re
P FC_STOP
Vin
VHsta rt
t
This function is useful to implement a latched over temperature protection very easily by
biasing the pin with a divider from VREF, where the upper resistor is an NTC physically
located close to a heating element like the MOSFET, or the secondary diode or the
transformer. An OVP can be implemented as well, e.g. by sensing the output voltage and
transferring an overvoltage condition via an optocoupler.
5.6
Oscillator and dead-time programming
The oscillator is programmed externally by means of a resistor-capacitor network (R , C )
T
T
connected from pin OSC (#5) to VREF (#6) and to ground respectively. Once chosen the
oscillator frequency and the dead-time duration needed, the values of RT and CT can be
calculated as:
Equation 1
1150
Td −125 ⋅10−9
RT = 50 +
fosc
(
)
Equation 2
1
RT −1200
CT = 1.39⋅
⋅
fosc RT
After having selected the commercial values for R and C , the oscillator frequency (f )
osc
(
RT − 50
)
T
T
can be verified with good approximation using the following formula:
19/32
Application information
Equation 3
L6591
1.39
fosc
≈
(CT (RT +1150))
During the negative-going ramp of the sawtooth a clock pulse is released. A T flip-flop, along
with a logic circuit, separates the odd and the even clock pulses. The even ones turn off the
low-side MOSFET first and, after a dead time Td, turn on the high-side MOSFET. Normally,
the high-side MOSFET is turned off (and the low-side MOSFET turned on after the dead
time Td) in response to the control loop; in case of overload it will be the overcurrent
comparator to do the job or, in case of open control loop, the odd clock pulses will limit the
maximum ON-time within one oscillator cycle. In this way, the maximum duty cycle will be
limited right below 50 % and the operating frequency of the converter will be half that of the
oscillator. Precisely, with reference to the waveforms in Figure 15, where Tsw= 2/fosc, the
maximum achievable duty cycle is:
Equation 4
TSW
− Td
Td
2
TSW
Dmax
=
= 0.5 −
= 0.5
(
1− Td fosc
)
TSW
At start-up the first clock pulse will turn on the low-side MOSFET for 10 oscillator cycles to
charge the bootstrap capacitor and then the high-side MOSFET will switch on. When the IC
resumes switching during burst-mode operation the first clock pulse will turn-on the low-side
MOSFET first to charge the bootstrap capacitor, and just after the second clock pulse the
high-side MOSFET will switch-on. In this way the bootstrap capacitor will always be charged
and ready to supply the high-side floating driver. The oscillator waveforms are illustrated in
Figure 15 as well.
The dead-time Td equals the duration of the negative-going ramp of the oscillator sawtooth
plus an internal delay of 125 ns; hence it depends on the timing capacitor CT and the
resistor RT and is given by the approximate relationship:
Equation 5
2.1
Td = CT
+125 ⋅10−9
3.05
RT
2.54 ⋅10−3
−
There is an internal 325 ns limit to the minimum Td value, to make sure that no hazardous
condition of shoot-through can be generated, however it is recommended not to use
capacitor values lower than 220 pF.
20/32
L6591
Application information
Figure 13. Oscillator waveforms and their relationship with gate-driving signals
OSC
t
Clock
t
HVG
t
LVG
T
T
T
d
d
T
d
on
t
T
sw
5.7
Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the self-supply system under these conditions falls considerably as
compared even to a few mA load. This very often causes the IC's supply voltage Vcc to drop
and go below the UVLO threshold of the controller so that the operation becomes
intermittent, which is undesired. A low UVLO threshold would be helpful but it could be an
issue to drive the MOSFETS with a sufficient gate-drive voltage at heavy load during power
off.
To help the designer overcome this problem, the L6591, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at pin COMP falls below a threshold VCOMPL internally fixed, so as to provide
more headroom. To prevent any malfunctioning during transients from minimum to
maximum load the normal (higher) UVLO threshold is re-established when the voltage at pin
COMP exceeds VCOMPL (with some mV hysteresis) and Vcc has exceeded the normal
UVLO threshold (see Figure 16). The normal UVLO threshold ensures that under heavy
load conditions the MOSFETS will be driven with an appropriate gate voltage.
Figure 14. Adaptive UVLO block
VCO MP
Vcc
9
V
COMPO
+
V
COMPL
-
R
S
7
COMP
-
Vcc
t
UVLO
Q
+
-
+
SW
V
V
COMPL
CC OFF1
CC OFF2
(*) V
PFC_ STOP
logic
V
V
CC OFF2 (*)
CC OFF1
t
t
L6591
Q
8
PFC_STOP
(*) VCC OF F2 < VCC OFF1 is selected when Q is high
21/32
Application information
L6591
5.8
Line sensing function
This function basically stops the IC as the input voltage to the converter falls below the
specified range and lets it restart as the voltage goes back within the range. The sensed
voltage can be either the rectified and filtered mains voltage, in which case the function will
act as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output
voltage of the PFC stage, in which case the function will serve as a power-on and power-off
sequencing.
L6591 shutdown upon input under voltage is accomplished by means of an internal
comparator, as shown in the block diagram of Figure 17, whose non-inverting input is
available at the LINE pin (#1). The comparator is internally referenced to 1.25 V and
disables the IC if the voltage applied at the LINE pin is below the internal reference. Under
these conditions the soft-start discharged, the pin PFC_STOP is open and the consumption
of the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the
reference. The comparator is provided with current hysteresis instead of a more usual
voltage hysteresis: an internal 15 µA current sink is ON as long as the voltage applied at the
LINE pin is below the reference and is OFF if the voltage is above the reference.
Figure 15. Line sensing function: internal block diagram and timing diagram
HV Input bus
VinON
VinOFF
LINE
t
1.25V
HV Input bus
t
Vcc
Vin OK
9
t
IHYS
R
H
15µA
1
LINE
+
-
Vin OK
t
15µA
Vcc
1.25V
3V
R
L
t
t
t
L6591
LVG, HVG
Vout
This approach provides an additional degree of freedom: it is possible to set the ON
threshold and the OFF threshold separately by properly choosing the resistors of the
external divider (see below). With voltage hysteresis, instead, fixing one threshold
automatically fixes the other one depending on the built-in hysteresis of the comparator.
With reference to Figure 17, the following relationships can be established for the ON
(VinON) and OFF (VinOFF) thresholds of the input voltage:
22/32
L6591
Application information
Equation 6
VinON −1.25
VinOFF −1.25
1.25
RL
1.25
RL
= 15 ⋅10−6
+
=
RH
RH
Which, solved for RH and RL, yield:
Equation 7
VinON − VinOFF
15 ⋅10−6
1.25
H VinOFF −1.25
RH =
;
RL = R
While the line undervoltage is active the start-up generator keeps on working but there is no
PWM activity, thus the Vcc voltage continuously oscillates between the start-up and the
UVLO thresholds, as shown in the timing diagram of Figure 17.
The LINE pin, while the device is operating, is a high impedance input connected to high
value resistors, thus it is prone to pick up noise, which might alter the OFF threshold or give
origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin to
ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind. If
the function is not used the pin has to be connected to the VREF pin (#6) through a resistor
in the range of 10 to 100 kΩ.
5.9
Soft-start and delayed latched shutdown upon overcurrent
At device start-up, a capacitor (Css) connected between the SS pin (#4) and ground is
charged by an internal current generator, ISS1, from zero up to about 2 V where it is
clamped. During this ramp, the overcurrent setpoint progressively raises from zero the final
value (0.8 V). The time needed for the overcurrent setpoint to reach its steady state value,
referred to as soft-start time, is approximately:
Equation 8
CSS
TSS = 0.8
ISS1
During the ramp, the MOSFET duty cycle increases progressively, hence controlling the
start-up inrush current. Furthermore, all the functions that monitor the voltage on pin COMP
are disabled.
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open-loop condition for the feedback system. This condition very often
occurs at start-up, but may be also caused by either a control loop failure or a converter
overload/short circuit.
23/32
Application information
Figure 16. Soft-start pin operation under different operating conditions
L6591
While in case of feedback loop failure the system must be stopped quickly to prevent the
output voltage from reaching too high values, an overload or a short circuit does not
generally need such fast intervention. The L6591 makes it easier to handle such conditions:
the 2 V clamp on the SS pin is removed and a second internal current generator ISS2 = ISS1
/4 keeps on charging Css. If the voltage reaches 5 V the IC will be disabled, if it is allowed to
reach 2 VBE over 5 V, the IC will be latched off. In the former case the resulting behavior will
be identical to that under short circuit illustrated in Figure 11; in the latter case the result will
be identical to that of Figure 12. The time delay before stopping switching upon overload is:
Equation 9
CSS
Tdelay = 12
ISS1
If the overload disappears before the SS voltage reaches 5 V the ISS2 generator will be
turned off and the voltage gradually brought back down to 2 V. A diode, with the anode to the
SS pin and the cathode connected to the VREF pin (#6) allows the designer to select either
an auto-restart mode or a latch-mode behavior upon overload.
If latch-mode behavior is desired also for converter’s short circuit, make sure that the supply
voltage of the IC never falls below the UVLO threshold before activating the latch. Figure 18
shows soft-start pin behavior under different operating conditions.
Figure 17 shows a typical high-power adapter application that uses the L6591 in conjunction
with the L6563 PFC controller.
24/32
L6591
Summary of L6591 power management functions
6
Summary of L6591 power management functions
It has been seen that the device is provided with a number of power management functions:
different operating mode upon loading conditions, protection functions, as well as interaction
with the PFC pre-regulator. To help the designer familiarize with these functions, in the
following tables all of theme are summarized with their respective activation mechanism and
the resulting status of the most important pins. This can be useful not only for a correct use
of the IC but also for diagnostic purposes: especially at prototyping/debugging stage, it is
quite common to bump into unwanted activation of some function, and these tables can be
used as a sort of quick troubleshooting guide.
Table 5.
Feature
Light load management
Vcc
IC
Consumption
[mA]
Description Caused by
restart
[V]
PFC_STOP
SS
OSC
behavior
Controlled
ON-OFF
operation for
low power
consumption
at light load
2 mA max
when
Active (low)
when
Stopped
when
Pulse
skipping
operation
VCOMP
VCOMPBon
<
No
Burst mode
N.A.
N.A.
VCOMP
<
VCOMP
<
change VCOMP
<
VCOMPBon
VCOMPBon
VCOMPBon
Extended
Vcc range at
light load
UVLO
threshold
reduction
Adaptive
UVLO
VCOMP
VCOMPL
<
No
change
N.A.
No change
Run
Table 6.
Protections
Vcc
restart
[V]
IC
IC Iq VREF
VCOMP OSC
Protection Description Caused by
SS
PFC_STOP
behavior
[mA]
[V]
[V]
[V]
VCOMP
VCOMPH
VSS
VSSDIS
=
Output
overload
protection
Auto
OLP
5
13
5
1.2
5
N.A.
0
Stop Active (low)
Stop Active (low)
Stop Active (low)
Stop Active (low)
>
restart (1)
VCOMP
=
VCOMPH
0.35
max
Latched
0
5
0
N.A.
N.A.
N.A.
0
0
0
VSS
>
VSSLAT
VCOMP
=
Output short
circuit
protection
Shortcircuit
protection
VCOMPH
Auto
1.2
VSS
>
restart (1)
VSSDIS
VCOMP
=
VCOMPH
0.35
max
Latched
13
VSS
>
VSSLAT
25/32
Summary of L6591 power management functions
Table 6. Protections (continued)
L6591
Vcc
restart
[V]
IC
IC Iq VREF
VCOMP OSC
Protection Description Caused by
SS
PFC_STOP
behavior
[mA]
[V]
[V]
[V]
Transformer
saturation or
shorted
secondary
diode
protection
VISEN
>
1.5 V for 2
consecutive
switching
cycles
Latched
0.35
max
2
nd OCP
5
0
0
0
Stop Active (low)
Stop Active (low)
(2)
Externally
programmabl
e latched
VDIS
4.5 V
>
0.35
max
DISABLE
Latched
13
5
0
0
0
0
0
0
protection
Mains
VLINE
1.25 V
<
Auto
restart
0.35
max
Not active
Stop
Brownout undervoltage
protection
(high Z)
1. Use one external diode from SS (#14) to VREF (#10), cathode to VREF.
2. The condition is latched as long as the IC is supplied; the HV generator is not invoked.
3. All values are typical unless otherwise specified.
It is worth reminding that “auto-restart” means that the device will work intermittently as long
as the condition that is activating the function is not removed; “Latched” means that the
device is stopped as long as the unit is connected to the input power source and the unit
must be disconnected for some time from the source in order for the device (and the unit) to
restart.
26/32
L6591
Summary of L6591 power management functions
Figure 17. L6591 typical application: 180 W, WRM, power-factor-corrected AC-DC adapter
D1
R9A
1M
R11A
2M
R1A
2M
T1
STTH1L06
R3
33
C2
10nF
BD1
R4 C3
4. 7k 1µF
R9B
1M
R11B
2M
DZ1
15V
FBI6K5F1
F1 T4A
LF1-A
LF2 - A
LF2 - B
R1B
2M
R2
68k
CX1
CX2
Vin = 88
to 264 V ac
C1
Q1
0.47 F
0. 68 F
11
6
7
9
C9
150 µF
45 0 V
STP20NM50
0.47 F
630V
R7 10
3
IC1
L6563
5
LF1-B
13
4
NTC1 10
8
12
14
10
C4
R6 100k
3. 3n F
R2
33 k
R8 A, B
0.27
R1 0
9.53k
R12
21 k
C6
470nF
C8
10nF
C5
220n
R5 C7
330k 1n F
D2
1N4148
R13
47
C12
C10
10 n
C11
220n
Q2
TBD
47 F
25 V
R14
TBD
D6
TBD
L1
TBD
Vout
+18V/ 10A
R15
TBD
T2
C14
TBD
PFC_STOP
LI NE
HVSTART
16
Vcc
D3
1N4148
BOOT
15
8
1
9
C13
C21
TBD
C22
T2B
10 0n
HVG
TBD
14
13
GN D_ OU T
FGND
D4 1N4148 R16 TBD
R17 TBD
C23
TBD
LVG
Q3
TB D
10
3
IC2
ISEN
D7
TBD
L6591
R18
TB D
R1 9
TBD
11
R22
TBD
DZ2
18V
OC1
GND
1
2
2
6
5
4
7
4
3
COMP
DIS
VREF
OSC
SS
R23
1.2 k
OC2A
1
2
1/ 2 PC8 17 A
3
4
D5
1N 41 4 8
(optional)
PC817A
R2 4
TBD
R21
TBD
1/2
PC817A
OC 2 B
R25
TBD
C24
NTC1
TBD
TBD
IC3
TL431
C15
TBD
R20
TBD
C16
10 0 n F
C17
TBD
C18
TBD
C19
TBD
C20
TBD
R26
TBD
R27
TBD
27/32
Package mechanical data
L6591
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
28/32
L6591
Package mechanical data
Figure 18. SO16N package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.069
A
a1
a2
b
1.75
0.1
0.25 0.004
1.6
0.009
0.063
0.35
0.19
0.46 0.014
0.25 0.007
0.018
b1
C
0.010
0.5
0.020
c1
45°
(typ.)
0.386
(1)
D
9.8
5.8
10
0.394
E
e
6.2
0.228
0.244
0.050
1.27
8.89
e3
0.350
(1)
F
3.8
4.0
0.150
0.157
G
L
4.60
0.4
5.30 0.181
1.27 0.150
0.62
0.208
0.050
0.024
M
S
8 ° (max.)
SO16N
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
29/32
Order codes
L6591
8
Order codes
Table 7.
Order codes
Order codes
Package
Packaging
L6591
SO16N
SO16N
Tube
L6591TR
Tape and reel
30/32
L6591
Revision history
9
Revision history
Table 8.
Date
19-Jun-2008
Document revision history
Revision
Changes
1
Initial release
31/32
L6591
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