L6926013TR [STMICROELECTRONICS]
HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATOR; 高效率单片同步降压稳压器
| 型号： | L6926013TR |
| 厂家： | 
ST |
| 描述： | HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATOR |
| 文件： | 总11页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6926
HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS
STEP DOWN REGULATOR
Figure 1. Packages
1 FEATURES
■ 2V TO 5.5V BATTERY INPUT RANGE
■ HIGH EFFICIENCY: UP TO 95%
■ INTERNAL SYNCHRONOUS SWITCH
■ NO EXTERNAL SCHOTTKY REQUIRED
■ EXTREMELY LOW QUIESCENT CURRENT
■ 1µA MAX SHUTDOWN SUPPLY CURRENT
■ 800mA MAX OUTPUT CURRENT
VFSON8 (3x4.9x1mm)
MSOP8
Table 1. Order Codes
Part Number
L6926
Package
MSOP8 in Tube
■
ADJUSTABLE OUTPUT VOLTAGE FROM 0.6V
■ LOW DROP-OUT OPERATION: UP TO100%
DUTY CYCLE
L6926013TR
L6926D1
MSOP8 in Tape & Reel
VFSON-8 in Tube
■ SELECTABLE LOW NOISE/LOW
CONSUMPTION MODE AT LIGHT LOAD
■ POWER GOOD SIGNAL
L6926D1013TR
VFSON8 in Tape & Reel
■ ±1% OUTPUT VOLTAGE ACCURACY
■ CURRENT-MODE CONTROL
■ 600kHz SWITCHING FREQUENCY
■ EXTERNALLY SYNCHRONIZABLE FROM
500kHz TO 1.4MHz
3 DESCRIPTION
The device is dc-dc monolithic regulator specifically
designed to provide extremely high efficiency.
L6926 supply voltage can be as low as 2V allowing
its use in single Li-ion cell supplied applications. Out-
put voltage can be selected by an external divider
down to 0.6V. Duty Cycle can saturate to 100% al-
lowing low drop-out operation. The device is based
on a 600kHz fixed-frequency, current mode-architec-
ture. Low Consumption Mode operation can be se-
lected at light load conditions, allowing switching
losses to be reduced. L6926 is externally synchroni-
zable with a clock which makes it useful in noise-sen-
sitive applications. Other features like Powergood,
Overvoltage protection, Shortcircuit protection and
Thermal Shutdown (150°C) are also present.
■ OVP
■ SHORT CIRCUIT PROTECTION
2 APPLICATIONS
■ BATTERY-POWERED EQUIPMENTS
■ PORTABLE INSTRUMENTS
■ CELLULAR PHONES
■ PDAs AND HAND HELD TERMINALS
■ DSC
■ GPS
Figure 2. Application Test Circuit
L 6.8µH
VOUT=1.8V
5
VIN=2V to 5.5V
SYNC
VCC
LX
R3
500K
R2
C4
7
6
1
200K
10µF
6.3V
C1
10µF
6.3V
RUN
8
PGOOD
VFB
3
2
4
R1
100K
COMP
GND
C2
220pF
D01IN1305
Rev. 4
1/11
November 2004
L6926
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
V
V
V
V
V
V
V
Input voltage
-0.3 to 6
6
5
1
3
2
8
7
Output switching voltage
Shutdown
-1 to V
V
CC
-0.3 to V
-0.3 to V
-0.3 to V
-0.3 to V
-0.3 to V
0.45
V
CC
CC
CC
CC
CC
Feedback voltage
V
Error amplifier output voltage
PGOOD
V
V
Synchronization mode selector
Power dissipation at Tamb=70°C
Junction operating temperature range
Storage temperature range
V
Ptot
Tj
W
°C
°C
V
-40 to 150
-65 to 150
±1000
Tstg
LX Pin
Other pins
Maximum Withstanding Voltage Range Test Condition: CDF-
AEC-Q100-002- “Human Body Model” Acceptance Criteria:
“Normal Performance’
±2000
V
Figure 3. Pin Connection
RUN
COMP
VFB
1
2
3
4
8
7
6
5
PGOOD
SYNC
VCC
GND
LX
D01IN1239AMOD
Table 3. Thermal Data
Symbol
Parameter
Value
Unit
R
Thermal Resistance Junction to Ambient
180
°C/W
th j-amb
Table 4. Pin Functions
N
Name
Description
1
RUN
Shutdown input. When connected to a low level (lower than 0.4V) the device stops working.
When high (higher than 1.3V) the device is enabled.
2
3
COMP
VFB
Error amplifier output. A compensation network has to be connected to this pin. Usually a
220pF capacitor is enough to guarantee the loop stability.
Error amplifier inverting input. The output voltage can be adjusted from 0.6V up to the input
voltage by connecting this pin to an external resistor divider.
4
5
6
GND
LX
Ground.
Switch output node. This pin is internally connected to the drain of the internal switches.
VCC
Input voltage. The start up input voltage is 2.2V (typ) while the operating input voltage range is
from 2V to 5.5V. An internal UVLO circuit realizes a 100mV (typ.) hysteresis.
2/11
L6926
7
8
SYNC
Operating mode selector input. When high (higher than 1.3V) the Low Consumption Mode is
selected. When low (lower than 0.5V) the Low Noise Mode is selected. If connected with an
appropriate external synchronization signal (from 500KHz up to 1.4MHz) the internal
synchronization circuit is activated and the device works at the same switching frequency.
PGOOD
Power good comparator output. It is an open drain output. A pull-up resistor should be
connected between PGOOD and VOUT (or VCC depending on the requirements). The pin is
forced low when the output voltage is lower than 90% of the regulated output voltage and goes
high when the output voltage is greater than 90% of the regulated output voltage. If not used the
pin can be left floating.
Table 5. Electrical Characteristics (T = 25°C, V = 3.6V unless otherwise specified)
j
CC
Symbol
Parameter
Operating input voltage
Turn On threshold
Turn Off threshold
Hysteresis
Test Condition
Min
Typ
Max
Unit
V
V
After Turn on
2
5.5
cc
V
2.2
V
cc ON
V
2
V
cc OFF
V
100
240
215
1.2
mV
mΩ
mΩ
A
cc hys
R
R
High side Ron
V
V
V
V
= 3.6V, I =100mA
lx
p
n
cc
cc
cc
cc
Low side Ron
= 3.6V, I =100mA
lx
I
Peak current limit
Valley current limit
Output voltage range
Oscillator frequency
Sync mode clock (*)
= 3.6V
= 3.6V
lim
1.4
A
V
out
V
fb
Vcc
V
f
600
KHz
KHz
osc
f
500
1400
sync
DC CHARACTERISTICS
I
Quiescent current (low noise
mode)
V
0.6V
= 0V, no load, V >
FB
230
25
µA
µA
q
sync
Quiescent current (low
cunsumption mode)
V
= V , no load, V
sync cc FB
> 0.6V
I
Shutdown current
RUN to GND, V = 5.5V
0.2
1
µA
µA
sh
cc
I
LX leakage current (*)
RUN to GND, V = 5.5V,
LX
lx
V
= 5.5V
cc
RUN to GND, V = 0V,
1
µA
LX
V
= 5.5V
cc
ERROR AMPLIFIER CHARACTERISTICS
V
Voltage feedback
0.593
0.4
0.6
25
0.607
1.3
V
fb
I
fb
Feedback input current (*)
V
FB
= 0.6V
nA
RUN
V
RUN threshold high
RUN threshold low
RUN input current (*)
V
V
run_H
V
run_L
I
25
nA
run
SYNC/MODE FUNCTION
V
Sync mode threshold high
Sync mode threshold low
1.3
V
V
sync_H
V
0.5
sync_L
PGOOD SECTION
3/11
L6926
V
Power Good Threshold
Power Good Hysteresis
Power Good Low Voltage
V
= V
= V
90
4
%Vout
%Vout
V
PGOOD
OUT
fb
fb
∆V
V
OUT
PGOOD
V
Run to GND
0.4
Pgood(low)
I
Power Good Leakage Current
(*)
V
= 3.6V
50
10
nA
LK-PGOOD
PGOOD
PROTECTIONS
HOVP
Hard overvoltage threshold
V
OUT
= V
%Vout
fb
(*) Guaranteed by design
4 OPERATION DESCRIPTION
The main loop uses slope compensated PWM current mode architecture. Each cycle the high side MOSFET
is turned on, triggered by the oscillator, so that the current flowing through it (the same as the inductor current)
increases. When this current reaches the threshold (set by the output of the error amplifier E/A), the peak current
limit comparator PEAK_CL turns off the high side MOSFET and turns on the low side one until the next clock
cycle begins or the current flowing through it goes down to zero (ZERO CROSSING comparator). The peak in-
ductor current required to trigger PEAK_CL depends on the slope compensation signal and on the output of the
error amplifier.
In particular, the error amplifier output depends on the VFB pin voltage. When the output current increases, the
output capacitor is discharged and so the VFB pin decreases. This produces increase of the error amplifier out-
put, so allowing a higher value for the peak inductor current. For the same reason, when due to a load transient
the output current decreases, the error amplifier output goes low, so reducing the peak inductor current to meet
the new load requirements.
The slope compensation signal allows the loop stability also in high duty cycle conditions (see related section)
Figure 4. Device Block Diagram
RUN
VCC
SYNC
POWER
SENSE
PMOS
OSCILLATOR
GND
PMOS
LOW
NOISE/
COMP
FB
SLOP E
CONSUMPTION
GND
LOOP
PEAK
CL
E/A
CONTROL
VREF
0.6V
LX
DRIVER
OVP
PGOOD
ZERO
SENSE
NMOS
POWER
NMOS
Vcc
Vcc
CROSSING
VREF
0.9V
GND
PGOOD
VALLEY
CL
GND
4.1 Modes of Operation
Depending on the SYNC pin value the device can operate in low consumption or low noise mode. If the SYNC
pin is high (higher than 1.3V) the low consumption mode is selected while the low noise mode is selected if the
SYNC pin is low (lower than 0.5V).
4.1.1 Low Consumption Mode
4/11
L6926
In this mode of operation, at light load, the device operates discontinuously based on the COMP pin voltage, in
order to keep the efficiency very high also in these conditions. While the device is not switching the load dis-
charges the output capacitor and the output voltage goes down. When the feedback voltage goes lower than
the internal reference, the COMP pin voltage increases and when an internal threshold is reached, the device
starts to switch. In these conditions the peak current limit is set approximately in the range of 200mA-400mA,
depending on the slope compensation (see related section).
Once the device starts to switch the output capacitor is recharged. The feedback pin increases and, when it
reaches a value slightly higher than the reference voltage, the output of the error amplifier goes down until a
clamp is activated. At this point, the device stops to switch. In this phase, most of the internal circuitries are off,
so reducing the device consumption down to a typical value of 25µA.
4.1.2 Low Noise Mode
If for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode
can be selected. In low noise mode, the efficiency is a little bit lower compared with the low consumption mode
in very light load conditions but for medium-high load currents the efficiency values are very similar.
Basically, the device switches with its internal free running frequency of 600KHz. Obviously, in very light load
conditions, the device could skip some cycles in order to keep the output voltage in regulation.
4.1.3 Synchronization
The device can also be synchronized with an external signal from 500KHz up to 1.4MHz.
In this case the low noise mode is automatically selected. The device will eventually skip some cycles in very
light load conditions.
The internal synchronization circuit is inhibited in shortcircuit and overvoltage conditions in order to keep the
protections effective (see relative sections).
4.2 Short Circuit Protection
During the device operation, the inductor current increases during the high side turn on phase and decrease
during the high side turn off phase based on the following equations:
(VIN – V
)
∆ION = -----------------------O----U---T---- ⋅ TON
L
(VOUT
)
∆IOFF = ------------------- ⋅ TOFF
L
In strong overcurrent or shortcircuit conditions the VOUT can be very close to zero. In this case ∆ION increases
and
∆
IOFF decreases. When the inductor peak current reaches the current limit, the high side mosfet turns off
ION
and so the TON is reduced down to the minimum value (250ns typ.) in order to reduce as much as possible
∆
.
Anyway, if VOUT is low enough it can be that the inductor peak current further increases because during the
TOFF the current decays very slowly.
Due to this reason a second protection that fixes the maximum inductor valley current has been introduced. This
protection doesn't allow the high side MOSFET to turn on if the current flowing through the inductor is higher
that a specified threshold (valley current limit). Basically the TOFF is increased as much as required to bring the
inductor current down to this threshold.
So, the maximum peak current in worst case conditions will be:
VIN
IPEAK = IVALLEY + -------- ⋅ TON_MIN
L
Where IPEAK is the valley current limit (1.4A typ.) and TON_MIN is the minimum TON of the high side MOSFET.
4.3 Slope Compensation
5/11
L6926
In current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulse-
by-pulse instability (the so called sub harmonic oscillation) can occur.
To allow loop stability also in these conditions a slope compensation is present. This is realized by reducing the
current flowing through the inductor necessary to trigger the COMP comparator (with a fixed value for the COMP
pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage
(due to the increased current ripple across the inductor), so the slope compensation effect increases as the input
voltage increases.
From an application point of view, the final effect is that the peak current limit depends both on the duty cycle (if
higher than approximately 40%) and on the input voltage.
4.4 Loop Stability
Since the device is realized with a current mode architecture, the loop stability is usually not a big issue. For
most of the application a 220pF connected between the COMP pin and ground is enough to guarantee the sta-
bility. In case very low ESR capacitors are used for the output filter, such as multilayer ceramic capacitors, the
zero introduced by the capacitor itself can shift at very high frequency and the transient loop response could be
affected. Adding a series resistor to the 220pF capacitor can solve this problem.
The right value for the resistor (in the range of 50K) can be determined by checking the load transient response
of the device. Basically, the output voltage has to be checked at the scope after the load steps required by the
application. In case of stability problems, the output voltage could oscillates before to reach the regulated value
after a load step.
5 ADDITIONAL FEATURES AND PROTECTIONS
5.1 DROPOUT Operation
The Li-Ion battery voltage ranges from approximately 3V and 4.1V-4.2V (depending on the anode material). In
case the regulated output voltage is from 2.5V and 3.3V, it can be that, close to the end of the battery life, the
battery voltage goes down to the regulated one. In this case the device stops to switch, working at 100% of duty
cycle, so minimizing the dropout voltage and the device losses.
5.2 PGOOD (Power Good Output)
A power good output signal is available. The VFB pin is internally connected to a comparator with a threshold
set at 90% of the of reference voltage (0.6V). Since the output voltage is connected to the VFB pin by a resistor
divider, when the output voltage goes lower than the regulated value, the VFB pin voltage goes lower than 90%
of the internal reference value. The internal comparator is triggered and the PGOOD pin is pulled down.
The pin is an open drain output and so, a pull up resistor should be connected to him.
If the feature is not required, the pin can be left floating.
5.3 ADJUSTABLE OUTPUT VOLTAGE
The output voltage can be adjusted by an external resistor divider from a minimum value of 0.6V up to the input
voltage. The output voltage value is given by:
R2
VOUT = 0.6 ⋅ 1 + ------
R1
5.4 OVP (Overvoltage Protection)
The device has an internal overvoltage protection circuit to protect the load.
If the voltage at the feedback pin goes higher than an internal threshold set 10% (typ) higher than the reference
voltage, the low side power mosfet is turned on until the feedback voltage goes lower than the reference one.
During the overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also
6/11
L6926
able to sink current.
5.5 THERMAL SHUTDOWN
The device has also a thermal shutdown protection activated when the junction temperature reaches 150°C. In
this case both the high side MOSFET and the low side one are turned off. Once the junction temperature goes
back lower than 95°C, the device restarts the normal operation.
7/11
L6926
Figure 5. MSOP8 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.043
A
A1
A2
b
1.10
0.050
0.150 0.002
0.006
0.750 0.850 0.950 0.03 0.033 0.037
0.250
0.130
0.400 0.010
0.230 0.005
0.016
0.009
c
D (1) 2.900 3.000 3.100 0.114 0.118 0.122
4.650 4.900 5.150 0.183 0.193 0.20
E1 (1) 2.900 3.000 3.100 0.114 0.118 0.122
E
e
L
0.650
0.400 0.550 0.700 0.016 0.022 0.028
0.950 0.037
0.026
L1
k
0˚ (min.) 6˚ (max.)
0.100
aaa
0.004
MSOP8
(Body 3mm)
Note: 1. D and F does not include mold flash or protrusions.
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
8/11
L6926
Figure 6. VFSON8 Mechanical Data & Package Dimensions
mm
inch
OUTLINE AND
DIM.
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
TYP. MAX.
A
A1
b
0.80
0.85
1.00 0.031 0.034 0.039
0.05
0.0019
0.25
2.85
2.20
4.75
3.00
0.30
3.00
2.30
4.90
3.10
0.65
0.35 0.0098 0.012 0.0137
3.15 0.1122 0.118 0.1240
2.40 0.0866 0.0905 0.0944
5.05 0.1870 0.1929 0.1988
3.20 0.1181 0.1220 0.1259
0.0255
D
D2
E
E2
e
L
0.45
0.65 0.0177
0.05
0.0255
0.0019
VFSON8 (3x4.9x1.0mm, Pitch 0.65)
Very thin Fine pitch Small Outline No lead
ddd
7575057 A
9/11
L6926
Table 6. Revision History
Date
Revision
Description of Changes
First Issue in EDOCS dms.
January 2004
2
3
September 2004
Changed the style look & feel.
Add. new package VFSON8.
Add. V8 and V7 parameter in the Table 2 - Absolute Maximum Ratings.
November 2004
4
Update Order Codes
10/11
L6926
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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11/11
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