L6986H5V_技术文档

L6986H

Datasheet

38 V, 2 A synchronous step-down switching regulator with 30 μA quiescent current

Features

•

2 A DC output current

4 V to 38 V operating input voltage

Low consumption mode or low noise mode

30 µA I_Qat light-load (LCM V_OUT= 3.3 V)

8 µA I_Q-SHTDWN

Adjustable f_SW(250 kHz - 2 MHz)

Fixed output voltage (3.3 V and 5 V) or adjustable from 0.85 V to V_IN

Embedded output voltage supervisor

Synchronization

Adjustable soft-start time

Internal current limiting

Overvoltage protection

Output voltage sequencing

Peak current mode architecture

R_{DS(on) HS}= 180 mΩ, R_{DS(on) LS}= 150 mΩ

Thermal shutdown

Applications

Product status link

•

Designed for 12 V and 24 V buses

L6986H

Programmable logic controllers (PLCs)

Decentralized intelligent nodes

Sensors and low noise applications (LNM)

Description

The L6986H is a step-down monolithic switching regulator able to deliver up to 2 A

DC. The output voltage adjustability ranges from 0.85 V to VIN. Thanks to the P-

channel MOSFET high-side power element, the device features 100% duty cycle

operation. The wide input voltage range meets the specification for the 5 V, 12 V and

24 V power supplies.

The “low consumption mode” (LCM) is designed for applications active during idle

mode, so it maximizes the efficiency at light-load with controlled output voltage ripple.

The “low noise mode” (LNM) makes the switching frequency constant and minimizes

the output voltage ripple overload current range, meeting the low noise application

specifications. The output voltage supervisor manages the reset phase for any digital

load (µC, FPGA). The RST open collector output can also implement output voltage

sequencing during the power-up phase. The synchronous rectification, designed for

high efficiency at medium - heavy load, and the high switching frequency capability

make the size of the application compact. Pulse by pulse current sensing on both

power elements implements an effective constant current protection.

DS12905 - Rev 2 - February 2020

www.st.com

For further information contact your local STMicroelectronics sales office.

L6986H

Application schematic

1

Application schematic

Figure 1. Application schematic

uC RST

4

15

2

1

SYNCH

VIN

RST

16

VIN

VBIAS

13

14

VOUT

VCC

FSW

MLF

LX

10uH

75k

5

10uF

1uF

240k

82k

L6986H

6

9

7

FB

3

SS/INH

DELAY

EP

20uF

8

COMP

PGND

12

PGND

SGND

10

470nF 68nF

10nF

330p

2.2p

17

11

signal GND

power GND

GND

DS12905 - Rev 2

page 2/68

L6986H

Pin settings

2

Pin settings

2.1

Pin connection

Figure 2. Pin connection (top view)

RST

VCC

1

2

3

16

15

14

VBIAS

VIN

LX

SS/INH

EXPOSED

PAD TO

SYNCH/ISKIP

4

13

LX

SGND+PGND

PGND

SGND

VOUT

FSW

MLF

5

6

7

8

12

11

10

9

COMP

DELAY

2.2

Pin description

Table 1. Pin description

Number

Description

The RST open collector output is driven low when the output

voltage is out of regulation. The RST is released after an

adjustable time DELAY once the output voltage is over the active

delay threshold.

1

RST

Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage

reference. This pin supplies the embedded analog circuitry.

2

3

VCC

An open collector stage can disable the device clamping this pin

to GND (INH mode). An internal current generator (4 µA typ.)

charges the external capacitor to implement the soft-start.

SS/INH

The pin features master / slave synchronization in LNM (see Low

noise mode (LNM)) and skip current level selection in LCM (see

Low consumption mode (LCM)). In LNM, leave this pin floating

when it is not used.

4

5

SYNCH/ ISKP

FSW

A pull-up resistor (E24 series only) to VCC or pull down to GND

selects the switching frequency. Pin strapping is active only

before the soft-start phase to minimize the IC consumption.

A pull-up resistor (E24 series only) to VCC or pull-down to GND

selects the low consumption mode/low noise mode and the active

RST threshold. Pin strapping is active only before the soft-start

phase to minimize the IC consumption.

6

7

MLF

Output of the error amplifier. The designed compensation

network is connected at this pin.

COMP

An external capacitor connected to this pin sets the time DELAY

to assert the rising edge of the RST o.c. after the output voltage

is over the reset threshold. If this pin is left floating, RST is like a

Power Good.

8

9

DELAY

VOUT

Output voltage sensing

DS12905 - Rev 2

page 3/68

L6986H

Maximum ratings

Number

10

SGND

PGND

LX

Description

Signal GND

11

Power GND

12

Power GND

13

Switching node

DC input voltage

14

LX

15

VIN

Typically connected to the regulated output voltage. An external

voltage reference can be used to supply part of the analog

circuitry to increase the efficiency at light-load. Connect to GND if

not used.

16

VBIAS

-

Exposed pad

Exposed pad must be connected to SGND, PGND

2.3

Maximum ratings

Stressing the device above the rating listed in Table 2. Absolute maximum ratings may cause permanent damage

to the device. These are stress ratings only and operation of the device at these or any other conditions above

those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 2. Absolute maximum ratings

Symbol

Description

Min.

-0.3

Max.

40

Unit

V

IN

DELAY

PGND

SGND

-0.3

VCC+ 0.3

SGND + 0.3

-

V

SGND - 0.3

-

V

-0.3

(VIN+ 0.3) or (max. 4)

VIN+ 0.3

VCC+ 0.3

10

V

CC

SS /INH

MLF

-0.3

V

-0.3

V

See Table 1

COMP

VOUT

FSW

-0.3

V

-0.3

V

-0.3

VCC+ 0.3

VIN+ 0.3

(VIN+ 0.3) or (max. 6)

VIN+ 0.3

150

V

SYNCH

-0.3

V

-0.3

V

BIAS

RST

LX

-0.3

V

-0.3

V

T

Operating temperature range

Storage temperature range

-40

°C

J

T

-

-65 to 150

°C

A

STG

T

LEAD

Lead temperature (soldering 10 s.)

High-side / low-side switch current

260

2

I

, I

HS LS

DS12905 - Rev 2

page 4/68

L6986H

Thermal data

2.4

Thermal data

Table 3. Thermal data

Parameter

Symbol

Value Unit

Thermal resistance junction ambient (device soldered on the STMicroelectronics demonstration

board)

R

40

5

°C/W

thJA

Thermal resistance junction to exposed pad for board design (not suggested to estimate T from

J

thJC

power losses)

2.5

ESD protection

Table 4. ESD protection

Symbol

Test conditions

HBM

Value

2

Unit

kV

V

ESD

CDM

500

DS12905 - Rev 2

page 5/68

L6986H

Electrical characteristics

3

Electrical characteristics

T_J=25 °C, V_IN= 12 V unless otherwise specified.

Table 5. Electrical characteristics

Symbol

Parameter

Test conditions

Note

Min.

Typ.

Max.

Unit

Operating input voltage

range

V

-

4

-

38

IN

V

UVLO rising

threshold

CC

V

-

2.7

-

3.5

V

IN_H

V

UVLO falling

threshold

CC

V

-

2.4

2.55

2.1

-

3.5

IN_L

Duty cycle < 20%

-

I

Peak current limit

Valley current limit

PK

Duty cycle = 100% closed

loop operation

A

I

-

2.7

-

0.8

-

VY

(1)

I

LCM, V

= GND

= VCC

0.6

0.2

1

SKIPH

SYNCH

Programmable skip

current limit

(2)

I

-

0.8

-

SKIPL

SYNCH

I

LNM or V

overvoltage

OUT

Reverse current limit

High-side RDSON

Low-side RDSON

-

2

VY_SNK

R

I

=1 A

0.18

0.15

0.36

0.30

DS(on) HS

SW

Ω

R

=1 A

-

DS(on) LS

Selected switching

frequency

FSW pinstrapping before

SS

f

See Table 6. f

selection

500

-

SW

I

FSW biasing current

SS ended

-

0

nA

FSW

See Table 7. LNM/ LCM selection

(L6986H3V3), Table 8. LNM/ LCM selection

(L6986H5V) and Table 9. LNM/ LCM selection

(L6986H)

Low noise mode /low

consumption mode

selection

LCM/LNM

MLF pinstrapping before SS

-

I

MLF biasing current

Duty cycle

SS ended

-

0

-

0

-

500

100

-

nA

%

MLF

(2)

D

-

T

Minimum on-time

-

80

ns

ON MIN

VCC regulator

V

= GND (no

switchover)

BIAS

-

2.9

3.3

3.6

VCC

LDO output voltage

V

= 5 V (switchover)

BIAS

Switch internal supply from

V

IN

-

2.85

2.78

-

3.2

V

threshold

BIAS

to V

BIAS

SWO

(3 V< V

<5.5 V)

BIAS

Switch internal supply from

to V

3.15

V

BIAS

IN

Power consumption

VSS/INH =GND

Shutdown current from

I

-

4

8

15

µA

SHTDWN

V

IN

DS12905 - Rev 2

page 6/68

L6986H

Electrical characteristics

Symbol

Parameter

Test conditions

LCM -SWO

Note

Min.

Typ.

Max.

Unit

(3)

4

10

15

V

< V < V

(SLEEP)

REF

FB

OVP

V

= 3.3 V

BIAS

µA

LCM -NO SWO

VREF< VFB<

VOVP(SLEEP) VBIAS =

GND

(3)

35

70

120

Quiescent current from

I

Q OPVIN

V

IN

LNM -SWO

-

0.5

2

1.5

2.8

50

5

6

V

= GND (NO SLEEP)

FB

V

= 3.3 V

BIAS

mA

LNM -NO SWO

-

V

= GND (NO SLEEP)

FB

V

= GND

BIAS

LCM -SWO

< V < V (SLEEP)

(3)

25

0.5

115

5

µA

V

REF

FB

OVP

V

= 3.3 V

BIAS

Quiescent current from

I

Q OPVBIAS

V

BIAS

LNM -SWO

-

1.2

mA

V

= GND (NO SLEEP)

FB

V

= 3.3 V

BIAS

Soft-start

V

VSS threshold

VSS hysteresis

SS rising

-

200

-

460

100

700

140

INH

mV

µA

V

INH HYST

V

<V

OR

INH

SS

(2)

-

1

4

-

t< T

t> T

OR V +>V

EA FB

SS SETUP

I

C

SS

charging current

SS CH

AND V

SS SETUP

EA

(2)

+<V

FB

Start of internal error

amplifier ramp

V

-

0.995

-

1.1

3

1.150

-

V

-

SS START

SS/INH to internal error

amplifier gain

SS

-

GAIN

Error amplifier

3.3 V(L6986H3V3)

-

3.25

3.3

5.0

0.85

6

3.35

5.075

0.859

8.5

V

Voltage feedback

5 V(L6986H5V)

L6986H

4.925

V

OUT

0.841

3.3 V(L6986H3V3)

5 V(L6986H5V)

L6986H

4

7.5

-

µA

I

VOUT biasing current

Error amplifier gain

10

13.5

500

-

VOUT

-

50

nA

dB

(2)

A

V

-

100

EA output current

capability

I

-

±6

±12

±25

µA

COMP

Inner current loop

Current sense

transconductance

(2)

g

CS

I

= 1 A

pk

-

2.5

-

A/V

(V

to inductor

COMP

current gain)

DS12905 - Rev 2

page 7/68

L6986H

Electrical characteristics

Symbol

Parameter

Test conditions

Note

Min.

Typ.

Max.

Unit

(4)

V

*g

PP CS

Slope compensation

-

0.45

0.75

1

A

Overvoltage protection

Overvoltage trip

V

-

1.15

0.5

1.2

2

1.25

5

-

OVP

(V

/V

)

OVP REF

V

Overvoltage hysteresis

%

OVP HYST

Synchronization (fanout: 6 slave devices typ.)

1400 ⁽²⁾

2200 ⁽²⁾

1.2

LNM; FSW=VCC

LNM; FSW=GND

LNM,SYNCH rising

-

275

475

0.70

Synchronization

frequency

f

kHz

SYNCH

V

SYNCH input threshold

-

V

SYN TH

SYNCH pull-down

current

I

LNM, V

=1.2 V

SYN

0.7

-

mA

SYN

High level output

Low level output

LNM,5 mA sinking load

LNM,0.7 mA sourcing load

Reset

-

1.40

-

V

SYN OUT

0.6

See Table 7. LNM/ LCM selection

(L6986H3V3), Table 8. LNM/ LCM selection

(L6986H5V) and Table 9. LNM/ LCM selection

(L6986H)

V

THR

Selected RST threshold MLF pinstrapping before SS

-

(2)

V

RST hysteresis

-

2

-

%

THR HYST

V

>V

AND V < V

mA sinking load

4

TH

IN

INH

FB

-

0.4

RST open collector

output

V

RST

2 <V < V

4 mA sinking

IN

INH

-

0.8

load

Delay

RST open collector

released as soon as

V

> V

FB THR

-

1.19

1

1.234

2

1.258

3

V

THD

V

> V

DELAY

THD

C

charging

DELAY

I

V

> V

FB THR

µA

D CH

current

Thermal shutdown

temperature

(2)

T

-

165

30

-

SHDWN

°C

Thermal shutdown

hysteresis

T

HYS

-

1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application conditions.

2. Not tested in production.

3. LCM enables SLEEP mode at light-load.

4. Measured at f =250 kHz

sw

DS12905 - Rev 2

page 8/68

L6986H

Electrical characteristics

T_J= 25 °C, V_IN= 12 V unless otherwise specified.

Table 6. f_SWselection

R

VCC

(E24 series)

R

GND

(E24 series)

T

f

SW

min.

f

SW

typ.

f

SW

max.

Symbol

Unit

j

(1)

(1)(2)

(3)

0 Ω

1.8 Ω

3.3 kΩ

5.6 kΩ

10 kΩ

NC

225

250

275

-

285

330

-

NC

-

NC

-

380

NC

-

435

0 Ω

450

500

550

18 kΩ

33 kΩ

56 kΩ

NC

-

575

-

NC

-

660

-

(1) (3)

f

kHz

SW

NC

-

755

-

1.8 kΩ

3.3 kΩ

5.6 kΩ

10 kΩ

18 kΩ

33 kΩ

56 kΩ

-

870

-

(3)

NC

900

1000

1150

1310

1500

1750

2000

1100

NC

-

(2) (3)

NC

-

NC

-

(3)

NC

1575

1800

1925

2200

NC

1. Synchronization as slave in LNM between 275 kHz and 1400 kHz.

2. Not tested in production

3. Synchronization as slave in LNM between 475 kHz and 2200 kHz

T_J= 25 °C, V_IN= 12 V unless otherwise specified.

Table 7. LNM/ LCM selection (L6986H3V3)

V

/V

(tgt.

RST OUT

R (E24 1%)

VCC

R

GND

(E24 1%)

V

min.

V

typ.

V

max.

Unit

RST

Symbol

Operating mode

RST

value)

93%

80%

87%

96%

93%

80%

87%

96%

0 Ω

NC

0 Ω

3.008

2.587

2.814

3.105

3.008

2.587

2.814

3.105

3.069

2.640

2.871

3.168

3.069

2.640

2.871

3.168

3.130

8.2 kΩ

18 kΩ

39 kΩ

NC

2.693

2.928

3.231

3.130

2.693

2.928

3.231

LCM

V

RST

NC

8.2 kΩ

18 kΩ

39 kΩ

LNM

NC

DS12905 - Rev 2

page 9/68

L6986H

Electrical characteristics

T_J= 25 °C, V_IN= 12 V unless otherwise specified.

Table 8. LNM/ LCM selection (L6986H5V)

V

/V

(tgt.

RST OUT

R (E24 1%)

VCC

R

GND

(E24 1%)

V

min.

V

typ.

V

max.

Unit

RST

Symbol

Operating mode

RST

value)

93%

80%

87%

96%

93%

80%

87%

96%

0 Ω

NC

0 Ω

4.557

3920

4263

4704

4557

3920

4263

4704

4.650

4000

4350

4800

4650

4000

4350

4800

4743

8.2 kΩ

18 kΩ

39 kΩ

NC

4080

4437

4896

4743

4080

4437

4896

LCM

V

RST

NC

8.2 kΩ

18 kΩ

39 kΩ

LNM

NC

T_J= 25 °C, V_IN= 12 V unless otherwise specified.

Table 9. LNM/ LCM selection (L6986H)

V

/V

(tgt.

RST OUT

R (E24 1%)

VCC

R

GND

(E24 1%)

V

min.

V

typ.

V

max.

Unit

RST

Symbol

Operating mode

RST

value)

93%

80%

87%

96%

93%

80%

87%

96%

0 Ω

NC

0 Ω

0.779

0.670

0.728

0.804

0.779

0.670

0.728

0.804

0.791

0.680

0.740

0.816

0.791

0.680

0.740

0.816

0.802

0.690

0.751

0.828

0.802

0.690

0.751

0.828

8.2 kΩ ±1%

18 kΩ ±1%

39 kΩ ±1%

NC

LCM

V

RST

NC

8.2 kΩ ±1%

18 kΩ ±1%

39 kΩ ±1%

LNM

NC

DS12905 - Rev 2

page 10/68

L6986H

Functional description

4

Functional description

The L6986H device is based on a “peak current mode”, constant frequency control. As a consequence, the

intersection between the error amplifier output and the sensed inductor current generates the PWM control signal

to drive the power switch.

The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to

increase the efficiency at light-load.

The main internal blocks shown in the block diagram in Figure 3. Internal block diagram are:

•

Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features low-

dropout operation

•

A fully integrated sawtooth oscillator with adjustable frequency

A transconductance error amplifier

An internal feedback divider G_{DIV INT}

The high-side current sense amplifier to sense the inductor current

A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements

The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at

power-up. The SS/INH pin inhibits the device when driven low

•

The switchover capability of the internal regulator to supply a portion of the quiescent current when the V_BIAS

pin is connected to an external output voltage

The synchronization circuitry to manage master / slave operation and the synchronization to an external

clock

The current limitation circuit to implement the constant current protection, sensing pulse by pulse high-side /

low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the

stress of the external components

•

A circuit to implement the thermal protection function

The OVP circuitry to discharge the output capacitor in case of overvoltage event

MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator

FSW pinstrapping sets the switching frequency

The RST open collector output

Figure 3. Internal block diagram

FSW

COMP SYNC

VIN

SS/INH

POWER

P_MOS

SENSE

MOS

OSCILLATOR

P

V_REF

SS/INH

VOUT

0

T_SS

PEAK

CL

SLOPE

E/A

+

-

G_{DIV INT}

GND

LOOP

CONTROL

OVP

DRIVER

LX

-

+

L.N. / L.C.

DELAY

ZERO

CROSSING

SENSE

N_MOS

POWER

N_MOS

RST TH.

Vcc

GND

RST

VALLEY

CL

DELAY

GND

MLF

DS12905 - Rev 2

page 11/68

L6986H

Power supply and voltage reference

4.1

Power supply and voltage reference

The internal regulator block consists of a start-up circuit, the voltage pre-regulator that provides current to all the

blocks and the bandgap voltage reference. The starter supplies the start-up current when the input voltage goes

high and the device is enabled (SS/INH pin over the inhibits threshold).

The pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a

very low supply voltage noise sensitivity.

Switchover feature

The switchover scheme of the pre-regulator block features to derive the main contribution of the supply current for

the internal circuitry from an external voltage (3 V < V_BIAS<5.5 V is typically connected to the regulated output

voltage). This helps to decrease the equivalent quiescent current seen at V_IN. (Please refer to Switchover

feature).

4.2

Voltage monitor

An internal block continuously senses the V_CC,V_BIASand V_BG. If the monitored voltages are good, the regulator

starts operating. There is also a hysteresis on the V_CC(UVLO).

Figure 4. Internal circuit

V_CC

STARTER

PREREGULATOR

VREG

BANDGAP

IC BIAS

D00IN1126

VREF

4.3

Soft-start and inhibit

The soft-start and inhibit features are multiplexed on the same pin. An internal current source charges the

external soft-start capacitor to implement a voltage ramp on the SS/INH pin. The device is inhibited as long as the

SS/INH pin voltage is lower than the V_INHthreshold and the soft-start takes place when SS/INH pin crosses V_SS

_START. (See Figure 5. Soft-start phase).

The internal current generator sources 1 mA typ. current when the voltage of the VCC pin crosses the UVLO

threshold. The current increases to 4 µA typ. as soon as the SS/INH voltage is higher than the V_INHthreshold.

This feature helps to decrease the current consumption in inhibit mode. An external open collector can be used to

set the inhibit operation clamping the SS/INH voltage below V_INHthreshold.

The start-up feature minimizes the inrush current and decreases the stress of the power components during the

power-up phase. The ramp implemented on the reference of the error amplifier has a gain three times higher

(SS_GAIN) than the external ramp present at SS/INH pin.

DS12905 - Rev 2

page 12/68

L6986H

Soft-start and inhibit

Figure 5. Soft-start phase

The C_SSis dimensioned accordingly with Eq. (1) :

I

⋅ T

4μA ⋅ T

SS

0.85V

SSCH SS

C

= SS

GAIN

⋅

= 3 ⋅

(1)

SS

V

FB

where T_SSis the soft-start time, I_{SS CH}the charging current and V_FBthe reference of the error amplifier.

The soft-start block supports the precharged output capacitor.

DS12905 - Rev 2

page 13/68

L6986H

Soft-start and inhibit

Figure 6. Soft-start phase with precharged C_OUT

During normal operation a new soft-start cycle takes place in case of:

•

Thermal shutdown event

UVLO event

The device is driven in INH mode

The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 ms time max. For complete and

proper capacitor discharge in case of fault conditions, a maximum C_SS= 67 nF value is suggested.

The application example in Figure 7. Enable the device with external voltage step shows how to enable the

L6986H and perform the soft-start phase driven by an external voltage step.

Figure 7. Enable the device with external voltage step

DS12905 - Rev 2

page 14/68

L6986H

Soft-start and inhibit

The maximum capacitor value has to be limited to guarantee the device can discharge it in case of thermal

shutdown and UVLO events (see Figure 9), so restart the switching activity ramping the error amplifier reference

voltage

−1ms

C

<

(2)

SS

V

− 0.9V

SS_EQ

SS_FINAL

R

⋅ In(1 −

)

SS_EQ

600μA − R

where:

R

⋅ R

R

UP DWN

DWN

+ R

DWN

R

=

V

= ( V

STEP

− V

) ⋅

(3)

SS_EQ

SS_FINAL

DIODE

R

+ R

R

UP

DWN

The optional diode prevents the device from disabling if the external source drops to ground.

R_UPvalue is selected in order to make the capacitor charge at first approximation independent from the internal

current generator (4 µA typ. current capability, see Table 1), so:

V

− V

SS END

STEP

DIODE

≫ I

≡ 4μA

(4)

(5)

SS CHARGE

R

UP

where

V

FB

V

= V

SS START

+

SS END

SS

GAIN

represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier (see Figure 5. Soft-

start phase); refer to Table 1 for V_{SS START}, V_FBand SS_GAINparameters.

As a consequence the voltage across the soft-start capacitor can be written as:

1

V

(t) = V

SS FINAL

⋅

(6)

SS

t

⋅ R

−

1 − e

C

SS SS_EQ

R_{SS_DOWN}is selected to guarantee the device stays in inhibit mode when the internal generator sources 1 µA typ.

out of the SS/INH pin and V_STEPis not present:

R

⋅ I

≡ R

DWN

⋅ 1μA ≪ V

INH

≡ 200mV

(7)

DWN SSINHIBIT

so

R

< 100kΩ

(8)

DWN

R_UPand R_DWNare selected to guarantee:

V

≅ 2V > V

SS_END

(9)

SS_FINAL

The time to ramp the internal voltage reference can be calculated as follows

V

− V

SS START

SS_FINAL

T

= C ⋅ R

SS SS_EQ

⋅ In(

)

(10)

SS

V

− V

SS END

SS_FINAL

that is the equivalent soft-start time to ramp the output voltage.

Figure 8. External soft-start network V_STEPdriven shows the soft-start phase with the following component

selection: R_UP= 180 kΩ, R_DWN= 33 kΩ, C_SS= 200 nF, the 1N4148 is a small signal diode and V_STEP= 13 V.

DS12905 - Rev 2

page 15/68

L6986H

Soft-start and inhibit

Figure 8. External soft-start network V_STEPdriven

The circuit in Figure 7. Enable the device with external voltage step introduces a time delay between V_STEPand

the switching activity that can be calculated as:

V

SS_FINAL

− V

SS START

T

= C ⋅ R

SS SS_EQ

⋅ In(

)

(11)

SS

V

SS_FINAL

Figure 9. External soft-start after UVLO or thermal shutdown shows how the device discharges the soft-start

capacitor after an UVLO or thermal shutdown event in order to restart the switching activity ramping the error

amplifier reference voltage.

Figure 9. External soft-start after UVLO or thermal shutdown

DS12905 - Rev 2

page 16/68

L6986H

Soft-start and inhibit

4.3.1

Ratiometric startup

The ratiometric start-up is implemented sharing the same soft-start capacitor for a set of the L6986H devices

Figure 10. Ratiometric startup

V

V_OUT3

V_OUT2

V_OUT1

t

As a consequence all the internal current generators charge in parallel the external capacitor. The capacitor value

is dimensioned accordingly, as per equation below:

I

⋅ T

4μA ⋅ T

SS

0.85V

SSCH SS

C

= n

L6986H

⋅ SS

GAIN

⋅

= n

L6986H

⋅ 3 ⋅

(12)

SS

V

FB

where n_L6986Hrepresents the number of devices connected in parallel.

For better tracking of the different output voltages the synchronization of the set of regulators is suggested.

Figure 11. Ratiometric start-up operation

DS12905 - Rev 2

page 17/68

L6986H

Error amplifier

4.3.2

Output voltage sequencing

The L6986H device implements sequencing connecting the RST pin of the master device to the SS/INH of the

slave. The slave is inhibited as long as the master output voltage is outside regulation so implementing the

sequencing, see Figure 12. Output voltage sequencing.

Figure 12. Output voltage sequencing

V

V_OUT3

V_OUT2

V_OUT1

t

t_DELAY1

t_DELAY2

t_DELAY3

High flexibility is achieved thanks to the programmable RST thresholds (Table 7. LNM/ LCM selection

(L6986H3V3) and Table 8. LNM/ LCM selection (L6986H5V)) and programmable delay time. To minimize the

component count the DELAY pin capacitor can be also omitted so the pin works as a normal Power Good.

4.4

Error amplifier

The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose

non inverting input is connected to the internal voltage reference (0.85 V), while the inverting input (FB) is

connected to the external divider or directly to the output voltage.

Table 10. Uncompensated error amplifier characteristics

Description

Value

155 µS

100 dB

Transconductance

Low frequency gain

The error amplifier output is compared with the inductor current sense information to perform PWM control. The

error amplifier also determines the burst operation at light-load when the LCM is active.

4.5

Output voltage line regulation

The regulator features an enhanced line regulation thanks to the peak current mode architecture. Figure 13. V_OUT

= 3.3 V line regulation shows negligible output voltage variation (normalized to the value measured at V_IN= 12 V)

over the entire input voltage range for the L6986H with V_OUT= 3.3V.

DS12905 - Rev 2

page 18/68

L6986H

Output voltage load regulation

Figure 13. V_OUT= 3.3 V line regulation

0.10%

0.05%

0.00%

-0.05%

-0.10%

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

V [V]

IN

4.6

Output voltage load regulation

Figure 14. VOUT = 3.3 V load regulation shows negligible output voltage variation (normalized to the value

measured at I_OUT= 0 A) over the entire output current range for the L6986H with V_OUT= 3.3 V, measured on the

L6986H evaluation board (see Section 6.7 Application board).

Figure 14. VOUT = 3.3 V load regulation

0.10%

0.05%

0.00%

-0.05%

-0.10%

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

I_OUT[A]

4.7

High-side switch resistance vs. input voltage

Figure 15. Normalized R_DS(on),HSvariation shows the high-side switch R_DS(on)variation over the entire input

voltage operating range normalized at the value measured at V_IN= 12 V (see Section 3 Electrical

characteristics).

DS12905 - Rev 2

page 19/68

L6986H

Light-load operation

Figure 15. Normalized R_DS(on),HSvariation

R

_DS(on),HS@ I_OUT=1A (normalized @ V_IN=12V)

3%

2%

1%

0%

-1%

-2%

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

V [V]

IN

4.8

Light-load operation

The MLF pinstrapping during the power-up phase determines the light-load operation (refer to Table 7. LNM/ LCM

selection (L6986H3V3) and Table 8. LNM/ LCM selection (L6986H5V)).

4.8.1

Low noise mode (LNM)

The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features

a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed

V_IN. The regulator in steady loading condition never skips pulses and it operates in continuous conduction mode

(CCM) over the different loading conditions, thus making this operation mode ideal for noise sensitive

applications.

DS12905 - Rev 2

page 20/68

L6986H

Light-load operation

Figure 16. Low noise mode operation

4.8.2

Low consumption mode (LCM)

The low consumption mode maximizes the efficiency at light-load. The regulator prevents the switching activity

whenever the switch peak current request is lower than the I_SKIPthreshold. As a consequence the L6986H device

works in bursts and it minimizes the quiescent current request in the meantime between the switching operation.

In LCM operation, the pin SYNCH/ISKIP level dynamically defines the I_SKIPcurrent threshold (see

Table 5. Electrical characteristics) as shown in Table 11. I_SKIPprogrammable current threshold.

Table 11. I_SKIPprogrammable current threshold

I

current threshold

SYNCH / ISKIP (pin 4)

SKIP

ISKIP = 0.6 A typical

Low

H

ISKIP = 0.2 A typical

High

L

The I_SKIPprogrammability helps to optimize the performance in terms of the output voltage ripple or efficiency at

the light-load, that are parameters which disagree each other by definition. A lower skip current level minimizes

the voltage ripple but increases the switching activity (time between bursts gets closer) since less energy per

burst is transferred to the output voltage at the given load. On the other side, a higher skip level reduces the

switching activity and improves the efficiency at the light-load but worsen the voltage ripple.

No difference in terms of the voltage ripple and conversion efficiency for the medium and high load current level,

that is when the device operates in the discontinuous or continuous mode (DCM vs. CCM).

The L6986H allows changing the skip current threshold level while the device is switching in order to adapt the

pulse skipping operation to the loading condition. The time needed to detect and implement this transition is

negligible with respect to the switching period.

When the L6986H is configured in the low consumption mode, the SYNCH/ISKIP pin operates as a logic gate

input pin with an internal pull-down (4.5 µA typ.) guaranteeing the I_SKIPHoperation when leaving the pin floating.

Table 12. SYNCH/ISKIP pin voltage thresholds and driving current reports the V_SYNCH/ISKIPthresholds and the

minimum current needed to drive the pin.

DS12905 - Rev 2

page 21/68

L6986H

Light-load operation

Table 12. SYNCH/ISKIP pin voltage thresholds and driving current

Parameter

Value

0.65 V

1.6 V

V

SKIP_TH_L_MAX

V

SKIP_TH_H_MIN

SYNCH/ISKIP_DRIVING_MIN

I

± 10 µA

Figure 17. L6986H skip current level transition at I_LOAD= 150 mA with L = 10 µH shows a skip current threshold

transition at I_LOAD= 150 mA measured on the L6986H - V_OUT= 3.3 V with fsw = 500 kHz and L = 10 µH:

•

When V(SYNCH/ISKIP) < V_{SKIP_TH_L_MAX}, the L6986H operates in the pulse skipping mode minimizing

current consumption

•

When V(SYNCH/ISKIP) > V_{SKIP_TH_H_MIN}, the L6986H operates in the continuous conduction mode

minimizing the output voltage ripple

Figure 17. L6986H skip current level transition at I_LOAD= 150 mA with L = 10 µH

Figure 18. Light-load efficiency comparison at different I_SKIP- linear scale and Figure 19. Light-load efficiency

comparison at different I_SKIP- log scale report the efficiency measurements to highlight the ISKIP_Hand ISKIP_L

efficiency gap at the light-load also in comparison with the LNM operation. The same efficiency at the medium /

high load is confirmed at different ISKIP levels.

DS12905 - Rev 2

page 22/68

L6986H

Light-load operation

Figure 18. Light-load efficiency comparison at different I_SKIP- linear scale

VIN=13.5 V; VOUT=3.3V; fsw=500kH z

90

85

80

75

70

65

60

55

LCM ISKIPH=600mA

LCM ISKIPL=200mA

LNM - SWO

LNM

LCM_ISKIPH - SWO

LCM_ISKIPL - SWO

50

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

ILOAD [A]

Figure 19. Light-load efficiency comparison at different I_SKIP- log scale

VIN=13.5V; VOUT=3.3 V; fsw=5 00kH z

100

90

80

70

60

50

40

30

20

10

0

LCM ISKIPH=600mA

LCM ISKIPL=200mA

LNM

LNM - SWO

LCM_ISKIPH - SWO

LCM_ISKIPL - SWO

0.001

0.01

0.1

ILOAD [A]

Figure 20. LCM operation with ISKIP_H= 600 mA typ. at zero load and Figure 21. LCM operation with ISKIP_L=

200 mA typ. at zero load show the LCM operation at the different ISKIP level.

Figure 20. LCM operation with ISKIP_H= 600 mA typ. at zero load shows the ISKIP_H= 600 mA typ. and so 50 mV

output voltage ripple.

Figure 21. LCM operation with ISKIP_L= 200 mA typ. at zero load shows the ISKIP_L= 200 mA typ. and so less

than 20 mV output voltage ripple.

DS12905 - Rev 2

page 23/68

L6986H

Light-load operation

Figure 20. LCM operation with ISKIP_H= 600 mA typ. at zero load

Figure 21. LCM operation with ISKIP_L= 200 mA typ. at zero load

DS12905 - Rev 2

page 24/68

L6986H

Light-load operation

The LCM operation satisfies the high efficiency requirements of the battery powered applications. In order to

minimize the regulator quiescent current request from the input voltage, the V_BIASpin can be connected to an

external voltage source in the range 3 V < V_BIAS< 5.5 V (see Section 4.1 Power supply and voltage reference).

Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value:

T

0

BURST

∫

(i (t) ⋅ dt)

L

ΔQ

IL

V

=

(13)

OUT RIPPLE

C

OUT

Figure 22. LCM operation over loading condition (part 1)

DS12905 - Rev 2

page 25/68

L6986H

Light-load operation

Figure 23. LCM operation over loading condition (part 2-pulse skipping)

Figure 24. LCM operation over loading condition (part 3-pulse skipping)

DS12905 - Rev 2

page 26/68

L6986H

Light-load operation

Figure 25. LCM operation over loading condition (part 4-CCM)

4.8.3

Quiescent current in LCM with switchover

The current absorbed from the input voltage in the low consumption mode while regulating the output voltage at

the zero output load depends on the input voltage value and the selected skip current level, as shown in

Figure 26. Quiescent current at V_OUT= 3.3 V and zero output load and Figure 27. Quiescent current at V_OUT= 5

V and zero output load

Figure 26. Quiescent current at V_OUT= 3.3 V and zero output load

When V_INis adequately higher than V_OUT(see Figure 26. Quiescent current at V_OUT= 3.3 V and zero output

load ) the device works in the bursts mode operation, minimizing the power consumption over the entire input

voltage (see Section 4.8.2 Low consumption mode (LCM)).

DS12905 - Rev 2

page 27/68

L6986H

Light-load operation

Figure 27. Quiescent current at V_OUT= 5 V and zero output load

_BIAS=V

_OUT=5 V and I _LOAD= 0

L6986H input current with V

LCM-500kHz

120

100

80

ISKIPH

ISKIPL

60

40

20

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

V_IN[V]

When V_INapproaches V_OUT(see Figure 27. Quiescent current at V_OUT= 5 V and zero output load and zoomed

Figure 28. Quiescent current at V_INwhile regulating V_OUT= 5 V at zero output load) the device increases the

switching activity towards the continuous conduction mode operation for the internal slope contribution effect on

the programmed skip current threshold. As a consequence the quiescent current increases.

When VIN is lower than VOUT (see Figure 28. Quiescent current at V_INwhile regulating V_OUT= 5 V at zero

output load), the device enters in the low-dropout operation with the high-side always switched on. In this

operating condition, all the internal circuit blocks are active and the quiescent current corresponds to what

measured in the low noise mode operation (see I_{Q OP VIN}and I_{Q OP VBIAS}in Table 5. Electrical characteristics

given V_FB= GND).

Figure 28. Quiescent current at V_INwhile regulating V_OUT= 5 V at zero output load

L6986H input current V_BIAS=V_OUT=5 V and I_LOAD=0 LCM=500 kHz

16

ISKIPH

14

ISKIPL

12

10

8

6

Drop Out

Pulse Skipping

SLEEP Mode

No SLEEP Mode

4

2

0

Continuous

Conduction Mode

4

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

5.8

6

V [V]

IN

DS12905 - Rev 2

page 28/68

L6986H

Switchover feature

4.9

Switchover feature

The switchover maximizes the efficiency at the light-load that is crucial for LCM applications.

The switchover operation features to derive the main contribution of the supply current for the internal circuitry

from an external voltage (3 V < V_BIAS< 5.5 V is typically connected to the regulated output voltage). This helps to

decrease the equivalent quiescent current seen at V_IN.

In case the regulator output voltage is not compatible with the V_BIASinput voltage range, it is possible to use an

auxiliary voltage source for the switchover operation. The external auxiliary voltage source must always respect

the condition 3 V < V_AUX< 5.5 V, and must be derived from the L6986H power supply (VIN - pin 15) for proper

power sequencing of the internal circuits.

4.9.1

LCM

The LCM operation satisfies the high efficiency requirements of the battery powered applications.

In case the V_BIASpin is connected to the regulated output voltage (V_OUT), the total current drawn from the input

voltage can be calculated as:

V

1

BIAS

I

= I

QOPVIN

+

⋅

⋅ I

QOPVBIAS

(14)

QVIN

η

V

L6986H

IN

where I_{Q OP VIN}, I_{Q OP VBIAS}are defined in Table 5. Electrical characteristics and η_L6986His the efficiency of the

conversion in the working point.

4.9.2

LNM

is also valid when the device works in LNM and it can increase the efficiency at the medium load since the

regulator always operates in the continuous conduction mode.

4.10

Overcurrent protection

The current protection circuitry features a constant current protection, so the device limits the maximum peak

current (see Table 5. Electrical characteristics) in overcurrent condition.

The L6986H device implements a pulse by pulse current sensing on both power elements (high-side and low-side

switches) for effective current protection over the duty cycle range. The high-side current sensing is called “peak”

the low-side sensing “valley”.

The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a

minimum conduction time of the power element. This time is called “masking time” because the information from

the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. As a

consequence, the peak current protection is disabled for a masking time after the high-side switch is turned on,

the valley for a masking time after the low-side switch is turned on. In other words, the peak current protection can

be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles.

The L6986H device assures an effective overcurrent protection sensing the current flowing in both power

elements. In case one of the two current sensing circuitry is ineffective because of the masking time, the device is

protected sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley” current

limits assures the effectiveness of the overcurrent protection even in extreme duty cycle conditions.

The valley current threshold is designed higher than the peak to guarantee a proper operation. In case the current

diverges because of the high-side masking time, the low-side power element is turned on until the switch current

level drops below the valley current sense threshold. The low-side operation is able to prevent the high-side turn

on, so the device can skip pulses decreasing the switching frequency.

DS12905 - Rev 2

page 29/68

L6986H

Overcurrent protection

Figure 29. Valley current sense operation in overcurrent condition

Figure 29. Valley current sense operation in overcurrent condition shows the switching frequency reduction during

the valley current sense operation in case of extremely low duty cycle (V_IN= 12 V, f_SW= 2 MHz short-circuit

condition).

In a worst case scenario (like Figure 29. Valley current sense operation in overcurrent condition) of the

overcurrent protection the switch current is limited to:

V

− V

L

IN

OUT

I

= I

VALLEYTH

+

⋅ T

MASKHS

(15)

MAX

where I_{VALLEY_TH}is the current threshold of the valley sensing circuitry (see Table 5. Electrical characteristics)

and T_{MASK_HS}is the masking time of the high-side switch 100 ns typ.).

In most of the overcurrent conditions the conduction time of the high-side switch is higher than the masking time

and so the peak current protection limits the switch current.

I

= I

PEAK_TH

(16)

MAX

DS12905 - Rev 2

page 30/68

L6986H

OCP and switchover feature

Figure 30. Peak current sense operation in overcurrent condition

The DC current flowing in the load in overcurrent condition is:

I

(V

)

V

− V

RIPPLE OUT

IN OUT

I

(V

) = I

MAX

−

= I

MAX

− (

⋅ T

)

(17)

DCOC OUT

ON

2

2 ⋅ L

4.11

OCP and switchover feature

Output capacitor discharging the current flowing to ground during heavy short-circuit events is only limited by

parasitic elements like the output capacitor ESR and short-circuit impedance.

Due to parasitic inductance of the short-circuit impedance, negative output voltage oscillations can be generated

with huge discharging current levels (see Figure 1).

DS12905 - Rev 2

page 31/68

L6986H

OCP and switchover feature

Figure 31. Output voltage oscillations during heavy short-circuit

Figure 32. Zoomed waveforms

DS12905 - Rev 2

page 32/68

L6986H

Overvoltage protection

The V_BIASpin absolute maximum ratings (see Table 1) must be satisfied over the different dynamic conditions.

If the V_BIASis connected to GND there are no issues (see Figure 31. Output voltage oscillations during heavy

short-circuit and Figure 32. Zoomed waveforms).

A small resistor value (few ohms) in series with the V_BIAScan help to limit the pin negative voltage (see

Figure 33. V_BIASin heavy short-circuit event) during heavy short-circuit events if it is connected to the regulated

output voltage.

Figure 33. V_BIASin heavy short-circuit event

4.12

Overvoltage protection

The overvoltage protection monitors the VOUT pin and enables the low-side MOSFET to discharge the output

capacitor if the output voltage is 20% over the nominal value.

This is a second level protection and should never be triggered in normal operating conditions if the system is

properly dimensioned. In other words, the selection of the external power components and the dynamic

performance determined by the compensation network should guarantee an output voltage regulation within the

overvoltage threshold even during the worst case scenario in term of load transitions.

The protection is reliable and also able to operate even during normal load transitions for a system whose

dynamic performance is not in line with the load dynamic request. As a consequence the output voltage regulation

would be affected.

Figure 34. Overvoltage operation shows the overvoltage operation during a negative steep load transient for a

system configured in low consumption mode and designed with a not optimized compensation network. This can

be considered as an example for a system with dynamic performance not in line with the load request.

The L6986H device implements a 1 A typ. negative current limitation to limit the maximum reversed switch current

during the overvoltage operation.

Moreover, the overvoltage protection also activates the internal pull-down on RST pin. Once OVP is deactivated,

the L6986H releases the RST pin after the delay programmed by DELAY capacitor (6 ms in

Figure 34. Overvoltage operation).

DS12905 - Rev 2

page 33/68

L6986H

Thermal shutdown

Figure 34. Overvoltage operation

4.13

Thermal shutdown

The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal

threshold (165 °C typical). The thermal sensing element is close to the power elements, ensuring fast and

accurate temperature detection. A hysteresis of approximately 30 °C prevents the device from turning ON and

OFF continuously. When the thermal protection runs away a new soft-start cycle will take place.

DS12905 - Rev 2

page 34/68

L6986H

Closing the loop

5

Closing the loop

Figure 35. Block diagram of the loop

5.1

G

(s) control to output transfer function

CO

The accurate control to output transfer function for a buck peak current mode converter can be written as:

S

1 +

ω

1

Z

G

(s) = R

⋅ g

⋅

⋅ F (s)

(18)

CO LOAD CS

H

R

⋅ T

S

LOAD SW

L

1 +

⋅ [m ⋅ (1 − D) − 0.5]

C

ω

p

where R_LOADrepresents the load resistance, g_CSthe equivalent sensing transconductance of the current sense

circuitry, w_pthe single pole introduced by the power stage and w_zthe zero given by the ESR of the output

capacitor.

F_H(s) accounts the sampling effect performed by the PWM comparator on the output of the error amplifier that

introduces a double pole at one half of the switching frequency.

1

ω

=

(19)

(20)

Z

ESR ⋅ C

OUT

m ⋅ (1 − D) − 0.5

1

c

ω

=

+

p

R

⋅ C

L ⋅ C

⋅ f

LOAD OUT

OUT SW

where:

S

e

S

n

m

= 1 +

C

S

= V ⋅ g ⋅ f

PP CS SW

(21)

e

V

− V

L

IN

OUT

S

=

n

S_nrepresents the on time slope of the sensed inductor current, Se the on time slope of the external ramp (V_PP

peak-to-peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle

over 50%.

S_ecan be calculated from the parameter V_PP× g_CSgiven in Table 1 .

DS12905 - Rev 2

page 35/68

L6986H

Error amplifier compensation network

The sampling effect contribution F_H(s) is:

1

F (s) =

(22)

(23)

H

s

1 +

2

S

ω

⋅ Q

+

n

p

ω

n

where:

ω

= π ⋅ f

n

SW

1

Q

=

p

π ⋅ [m ⋅ (1 − D) − 0.5]

c

5.2

Error amplifier compensation network

The typical compensation network required to stabilize the system is shown in Figure 36. Transconductance

embedded error amplifier:

Figure 36. Transconductance embedded error amplifier

R_Cand C_Cintroduce a pole and a zero in the open loop gain. C_Pdoes not significantly affect system stability but it

is useful to reduce the noise at the output of the error amplifier.

The transfer function of the error amplifier and its compensation network is:

A

⋅ (1 + s ⋅ R ⋅ C )

C c

V0

A (s) =

(24)

0

2

s

⋅ R ⋅ (C + C ) ⋅ R ⋅ C + s ⋅ (R ⋅ C + R ⋅ (C + C ) + R ⋅ C ) + 1

0

p

C

c

0

c

0

p

c

Where A_vo= G_m· R_o

The poles of this transfer function are (if C_c>> C₀+ C_P):

1

f

=

(25)

(26)

PLF

2 ⋅ π ⋅ R ⋅ C

0

c

1

f

=

PHF

2 ⋅ π ⋅ R ⋅ (C + C )

0

p

DS12905 - Rev 2

page 36/68

L6986H

Voltage divider

whereas the zero is defined as:

1

f

=

(27)

Z

2 ⋅ π ⋅ R ⋅ C

c

5.3

Voltage divider

The contribution of the internal voltage divider for fixed output voltage devices is:

R

V

FB

2

0.85

3.3

G

(s) =

=

= 0.2575

L6986H3V

L698H5V

DIV

R

+ R

V

1

2

OUT

V

(28)

R

2

FB

0.85

G

(s) =

=

= 0.17

DIV

R

+ R

V

5

1

2

OUT

while for the adjustable output part number L6986H is:

R

2

G

(s) =

L6986H

(29)

DIV

R

+ R

2

1

A small signal capacitor in parallel to the upper resistor (see Figure 37. Leading network example) of the voltage

divider implements a leading network (f_zero< f_pole), sometimes necessary to improve the system phase margin:

Figure 37. Leading network example

uC RST

4

15

2

1

SYNCH

VIN

RST

16

VIN

VBIAS

13

14

VOUT

VCC

FSW

MLF

LX

5

Cr1

R1

L6986H

6

9

7

FB

3

SS/INH

DELAY

EP

Rc

8

COMP

PGND

12

PGND

SGND

10

Cc

Cp

R2

17

11

signal GND

Power GND

GND

The Laplace transformer of the leading network is:

R

(1 + s + R ⋅ C

)

2

1

R1

G

(s) =

⋅

DIV

R

+ R

R ⋅ R

1 2

(30)

(31)

1

2

(1 + s ⋅

⋅ C

)

R1

R

+ R

2

1

where

1

f

=

Z

2 ⋅ π ⋅ R ⋅ C

1

R1

1

f

=

p

R

⋅ R

2

1

2 ⋅ π ⋅

⋅ C

R1

+ R

2

R

1

f

< f

p

Z

DS12905 - Rev 2

page 37/68

L6986H

Total loop gain

5.4

Total loop gain

In summary, the open loop gain can be expressed as:

G

= G

(s) ⋅ G (s) ⋅ A (s)

CO

(32)

(s)

DIV

0

example 1:

V_IN= 12 V, V_OUT= 3.3 V, R_OUT= 1.67 Ω

Selecting the L6986H with V_OUT=3.3 V, f_SW= 500 kHz, L = 10 µH, C_OUT= 20 µF and ESR = 3 mΩ, R_C= 75 kΩ,

C_C= 330 pF, C_P= 2.2 pF (please refer to Table 19. L6986H 3V3 demonstration board BOM), the gain and phase

bode diagrams are plotted respectively in Figure 38. Module plot and Figure 39. Phase plot.

Figure 38. Module plot

BW = 55 kHZ

phase margin = 60 °

Figure 39. Phase plot

The blue solid trace represents the transfer function including the sampling effect term (see ), the dotted blue

trace neglects the contribution.

DS12905 - Rev 2

page 38/68

L6986H

Compensation network design

5.5

Compensation network design

The maximum bandwidth of the system can be designed up to f_SW/6 up to 150 kHz maximum to guarantee a valid

small signal model.

2 ⋅ π ⋅ BW ⋅ C

⋅ V

m TYP

OUT OUT

R

=

(33)

C

0.85V ⋅ g ⋅ g

CS

where:

ω

p

f

=

(34)

POLE

2 ⋅ π

ω_pis defined by , gCS represents the current sense transconductance (see Table 1) and g_{m TYP}the error

amplifier transconductance.

5

C

=

(35)

C

2 ⋅ π ⋅ R ⋅ BW

C

Example 2:

Considering V_IN= 12 V, V_OUT= 3.3 V, L = 6.8 µH, C_OUT= 10 µF, f_SW= 500 kHz, I_OUT= 1 A.

The maximum system bandwidth is 80 kHz. Assuming to design the compensation network to achieve a system

bandwidth of 70 kHz:

f

= 2.7 kHz

(36)

POLE

V

OUT

R

=

= 3.3Ω

(37)

LOAD

I

OUT

so accordingly with Eq. (33) and Eq. (35):

R

= 48.5kΩ ≈ 47kΩ

= 237pF ≈ 270pF

(38)

(39)

C

The gain and phase bode diagrams are plotted respectively in Figure 40. Magnitude plot for example 2 and

Figure 41. Phase plot for example 2.

Figure 40. Magnitude plot for example 2

DS12905 - Rev 2

page 39/68

L6986H

Compensation network design

Figure 41. Phase plot for example 2

DS12905 - Rev 2

page 40/68

L6986H

Application notes

6

Application notes

6.1

Output voltage adjustment

The error amplifier reference voltage is 0.85 V typical.

The output voltage is adjusted accordingly as per equation below: (see Figure 42. L6986H application circuit).

R

1

V

= 0.85 ⋅ (1 +

)

(40)

OUT

R

2

C_r1capacitor is sometimes useful to increase the small signal phase margin (please refer to Compensation

network design).

Figure 42. L6986H application circuit

uC RST

4

15

2

1

16

RST

SYNCH

VBIAS

VIN

13

VOUT

LX

VCC

FSW

MLF

14

5

Cr1

R1

L6986H

6

3

8

9

7

FB

SS/INH

DELAY

Rc

COMP

PGND

11

EP SGND

Cc

Cp

R2

17

10

12

signal GND

Power GND

GND

6.2

6.3

Switching frequency

A resistor connected to the FSW pin features the selection of the switching frequency. The pinstrapping is

performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in

order to minimize the quiescent current from VIN. Please refer to Table 2 to identify the pull-up / pull-down resistor

value. f_SW= 250 kHz / f_SW= 500 kHz preferred codifications do not require any external resistor.

MLF pin

A resistor connected to the MLF pin features the selection of the between low noise mode / low consumption

mode and the different RST thresholds. The pinstrapping is performed at power-up, before the soft-start takes

place. The FSW pin is pinstrapped and then driven floating in order to minimize the quiescent current from VIN.

Please refer to Table 7. LNM/ LCM selection (L6986H3V3), Table 8. LNM/ LCM selection (L6986H5V), and

Table 9. LNM/ LCM selection (L6986H) to identify the pull-up / pull-down resistor value. (LNM, RST threshold

93%) / (LCM, RST threshold 93%) preferred codifications don't require any external resistor.

6.4

Voltage supervisor

The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the regulated output

voltage and keeps the RST open collector output in low impedance as long as the V_OUTis out of regulation. In

order to ensure a proper reset of digital devices with a valid power supply, the device can delay the RST assertion

with a programmable time.

DS12905 - Rev 2

page 41/68

L6986H

Voltage supervisor

Figure 43. Voltage supervisor operation

The comparator monitoring the FB voltage has four different programmable thresholds (80%, 87%, 93%, 96%

nominal output voltage) for high flexibility (see MLF pin, Table 7. LNM/ LCM selection (L6986H3V3),

Table 8. LNM/ LCM selection (L6986H5V), and Table 9. LNM/ LCM selection (L6986H)).

When the RST comparator detects the output voltage is in regulation, a 2 mA internal current source starts to

charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then

released as soon as V_DELAY= 1.234 V (see Figure 43. Voltage supervisor operation). The C_DELAYis dimensioned

as follows:

I

⋅ T

2μA ⋅ T

DELAY

SSCH DELAY

C

=

(41)

DELAY

V

1.234V

DELAY

The maximum suggested capacitor value is 270 nF.

The L6986H also activates internal pull-down on RST pin in case overvoltage protection is triggered. As soon as

the output voltage goes below OVP threshold (20% typ.), the 2 µA internal current source starts to charge an

external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as

soon as V_DELAY= 1.234 V(see figure below).

DS12905 - Rev 2

page 42/68

L6986H

Synchronization (LNM)

Figure 44. Voltage supervisor operation during OVP

6.5

Synchronization (LNM)

The synchronization feature helps the hardware designer to prevent beating frequency noise that is an issue

when multiple switching regulators populate the same application board.

6.5.1

Embedded master - slave synchronization

The L6986H synchronization circuitry features the same switching frequency for a set of regulators simply

connecting their SYNCH pin together, so preventing beating noise. The master device provides the

synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal.

For proper synchronization of multiple regulators, all of them have to be configured with the same switching

frequency (see Table 2), so the same resistor connected at the FSW pin.

In order to minimize the RMS current flowing through the input filter, the L6986H device provides a phase shift of

180° between the master and the SLAVES. If more than two devices are synchronized, all slaves will have a

common 180° phase shift with respect to the master.

Considering two synchronized L6986H which regulate the same output voltage (i.e.: operating with the same duty

cycle), the input filter RMS current is optimized and is calculated as:

I

OUT

2

⋅

2D ⋅ (1 − 2D)

ifD < 0.5

I

=

(42)

RMS

I

OUT

2

⋅

(2D − 1) ⋅ (2 − 2D)

ifD > 0.5

The graphical representation of the input RMS current of the input filter in the case of two devices with 0° phase

shift (synchronized to an external signal) or 180° phase shift (synchronized connecting their SYNCH pins)

regulating the same output voltage is provided in the figure below. To dimension the proper input capacitor please

refer to Input capacitor selection).

DS12905 - Rev 2

page 43/68

L6986H

Synchronization (LNM)

Figure 45. Input RMS current

0.5

0.4

0.3

0.2

0.1

0

two regulators operating in phase

two regulators operating out of phase

0

0.2

0.4

0.6

0.8

1

Duty cycle

Figure 46. Two regulators not synchronized shows two not synchronized regulators with unconnected SYNCH

pin.

Figure 46. Two regulators not synchronized

Figure 47. Two regulators synchronized shows the same regulators working synchronized having the SYNCH

pins connected. The MASTER regulator (LX_reg2 trace) delivers the synchronization signal to the SLAVE device

(LX_reg1). The SLAVE regulator works in phase with the synchronization signal, which is out of phase with the

MASTER switching operation.

DS12905 - Rev 2

page 44/68

L6986H

Synchronization (LNM)

Figure 47. Two regulators synchronized

6.5.2

External synchronization signal

Multiple L6986H can be synchronized to an external frequency signal fed to the SYNCH pin. In this case the

regulator set is phased to the reference and all the devices will work with 0° phase shift.

The minimum synchronization pulse width is 100 ns and the frequency range of the synchronization signal is:

•

[275 kHz - 1.4 MHz] if f_{SW_PROGRAMMED}< 500 kHz

[475 kHz - 2.2 MHz] if f_{SW_PROGRAMMED}≥ 500 kHz

(see Figure 48. Synchronization pulse definition).

Figure 48. Synchronization pulse definition

275 kHz < f_SYNCHRO< 1.4 MHz if

475 kHz < f_SYNCHRO< 2.2 MHz if

f

_{SW_PROGRAMMED}< 500 kHz typ

f

_{SW_PROGRAMMED}≥ 500 kHz typ

f_SYNCHRO

100 nsec. min.

Since the internal slope compensation contribution that is required to prevent subharmonic oscillations in peak

current mode architecture depends on the oscillator frequency, it is important to select the same oscillator

frequency for all regulators (all of them operate as SLAVE) as close as possible to the frequency of the reference

signal (please refer to Table 2). As a consequence all the regulators have the same resistor value connected to

the FSW pin, so the slope compensation is optimized accordingly with the frequency of the synchronization

signal. The slope compensation contribution is latched at power-up and so fixed during the device operation.

The L6986H normally operates in the MASTER mode, driving the SYNCH line at the selected oscillator frequency

as shown in Figure 49. L6986H synchronization driving capability.

DS12905 - Rev 2

page 45/68

L6986H

Synchronization (LNM)

In the SLAVE mode the L6986H sets the internal oscillator at 250 kHz typ. (see Table 2) and drives the line

accordingly.

Figure 49. L6986H synchronization driving capability

In order to safely guarantee that each regulator recognizes itself in SLAVE mode when synchronized, the external

master must drive the SYNCH pin with a clock signal frequency higher than the maximum oscillator spread of the

selected line in Table 2 for at least 10 internal clock cycles.

Once recognized as SLAVE the synchronization range is:

•

275 - 1.4 MHz if f_SW< 500 kHz

475 kHz - 2.2 MHz if f_SW>=500 kHz

example 1: selecting R_FSW= 0 Ω to VCC

Table 13. Example of oscillator frequency selection

R

VCC

(E24 series)

R

GND

(E24 series)

f

SW

min.

f

SW

typ.

f

SW

max.

Symbol

f

NC

0 Ω

225

250

275

SW

the device enters in slave mode after 10 pulses at frequency higher than 275 kHz and so it is able to synchronize

to a clock signal in the range 275 kHz - 1.4 MHz (see Figure 48. Synchronization pulse definition).

Example 2: selecting R_FSW= 0 Ω to GND

Table 14. Example of oscillator frequency selection (2)

R

VCC

(E24 series)

R

GND

(E24 series)

f

SW

min.

f

SW

typ.

f

SW

max.

Symbol

f

NC

0 Ω

450

500

550

SW

The device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it is able to synchronize

to a clock signal in the range 475 kHz - 2.2 MHz (see Figure 48. Synchronization pulse definition).

DS12905 - Rev 2

page 46/68

L6986H

Synchronization (LNM)

As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the slope compensation

is dimensioned accordingly with FSW resistors so it is important to limit the switching operation around a working

point close to the selected oscillator frequency (FSW resistor).

As a consequence, to guarantee the full output current capability and to prevent the subharmonic oscillations, the

MASTER may limit the driving frequency range within ± 5% of the selected frequency.

A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the peak current capability

(see IPK parameter in Table 1) since the internal slope compensation signal may be saturated.

The device keeps operating in slave mode as far as the master is able to drive the SYNCH pin faster than 275

kHz, otherwise the L6986H goes back into MASTER mode at the programmed R_FSWoscillator frequency after

successfully driving one pulse 250 kHz typ. (see Figure 50. Slave-to-master mode transition) in the SYNCH line.

Figure 50. Slave-to-master mode transition

The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the soft-

start begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is

triggered regardless FSW resistor value, that otherwise counts to design the slope compensation. The same

considerations above are also valid.

The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see Table 1):

•

Low level < V_{SYN THL}= 0.7 V sinking 5 mA

High level > V_{SYN THH}= 1.2 V sourcing 0.7 mA

DS12905 - Rev 2

page 47/68

L6986H

Design of the power components

Figure 51. Master driving capability to synchronize the L6986H

6.6

Design of the power components

6.6.1

Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.

During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must

be selected accordingly with the application conditions. Internal losses of the input filter depends on the ESR

value so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On

the other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher

conversion efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

D

(1 − ) ⋅

η

D

η

I

= I

OUT

⋅

(43)

RMS

Where I_OUTis the maximum DC output current, D is the duty cycles, ƞ is the efficiency. This function has a

maximum at D = 0.5 and, considering h = 1, it is equal to I_OUT/2.

In a specific application the range of possible duty cycles has to be considered in order to find out the maximum

RMS input current. The maximum and minimum duty cycles can be calculated as:

V

+ ΔV

LOWSIDE

OUT

LOWSIDE

+ ΔV

D

=

(44)

(45)

MAX

V

+ ΔV

− V

+ ΔV

INMIN

HIGHSIDE

− V + ΔV

INMIN HIGHSIDE

V

OUT

LOWSIDE

D

=

MIN

V

INMAX

Where DV_{HIGH_SIDE}and DV_{LOW_SIDE}are the voltage drops across the embedded switches. The peak-to-peak

voltage across the input filter can be calculated as follows:

I

OUT

⋅ f

D

η

D

η

C

=

⋅ (1 − ) ⋅ + ESR ⋅ (I

OUT

+ ΔI )

(46)

IN

L

V

PP SW

In case of negligible ESR (MLCC capacitor) the equation of C_INas a function of the target V_PPcan be written as

follows:

I

OUT

⋅ f

D

⋅ (1 − ) ⋅

η

D

η

C

=

(47)

(48)

IN

V

PP SW

Considering ƞ=1 this function has its maximum in D = 0.5:

I

OUT

C

=

INMIN

4 ⋅ V

⋅ f

PPMAX SW

Typically C_INis dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5%

V_{IN_MAX}

.

DS12905 - Rev 2

page 48/68

L6986H

Design of the power components

Table 15. Input capacitors

Manufacturer

Series

Size

1210

1206

1210

Cap value (µF)

Rated voltage (V)

C3225X7S1H106M

C3216X5R1H106M

UMK325BJ106MM-T

10

-

50

-

TDK

Taiyo Yuden

-

6.6.2

Inductor selection

The inductor current ripple flowing into the output capacitor determines the output voltage ripple (please refer to

Output capacitor selection). Usually the inductor value is selected in order to keep the current ripple lower than

20% - 40% of the output current over the input voltage range. The inductance value can be calculated by equation

below:

V

− V

L

V

OUT

L

IN

OUT

ΔI

=

⋅ T

ON

=

⋅ T

OFF

(49)

L

Where T_ONand T_OFFare the on and off time of the internal power switch. The maximum current ripple, at fixed

V_OUT, is obtained at maximum T_OFFthat is at minimum duty cycle (see Input capacitor selection to calculate

minimum duty). So fixing ΔI_L= 20% to 40% of the maximum output current, the minimum inductance value can be

calculated:

V

1 − D

OUT

MIN

L

=

⋅

(50)

MIN

ΔI

LMAX

f

SW

where f_SWis the switching frequency 1/(T_ON+ T_OFF).

For example for V_OUT= 3.3 V, V_IN= 12 V, I_OUT= 2 A and F_SW= 500 kHz the minimum inductance value to have

ΔI_L= 30% of I_OUTis about 8.2 µH.

The peak current through the inductor is given by:

ΔI

L

I

= I

OUT

+

(51)

L, PK

2

So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device)

increases. The higher is the inductor value, the higher is the average output current that can be delivered, without

reaching the current limit.

In the table below, some inductor part numbers are listed.

Table 16. Inductors

Manufacturer

Series

XAL50xx

XAL60xx

Inductor value (µH)

Saturation current (A)

6.5 to 2.7

Coilcraft

2.2 to 22

12.5 to 4

6.6.3

Output capacitor selection

The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output

voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). As a

consequence the output capacitor has to be selected in order to have a voltage ripple compliant with the

application requirements.

The voltage ripple equation can be calculated as:

ΔI

LMAX

ΔV

OUT

= ESR ⋅ ΔI

LMAX

+

(52)

8 ⋅ C

⋅ f

OUT SW

Usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi layer

ceramic capacitor (MLCC).

The output capacitor is important also for loop stability: it determines the main pole and the zero due to its ESR.

(See Closing the loop to consider its effect in the system stability).

DS12905 - Rev 2

page 49/68

L6986H

Application board

For example with V_OUT= 3.3 V, V_IN= 12 V, f_SW= 500 kHz, ΔI_L= 0.6 A, (resulting by the inductor value) and C_OUT

= 20 µF MLCC :

ΔV

ΔI

OUT

1

LMAX

C ⋅ f

OUT SW

1

0.6

7.5mV

3.3

≅

⋅

= (

⋅

) =

= 0.23 %

(53)

V

3.3 8 ⋅ 20μF ⋅ 500kHz

OUT

The output capacitor value has a key role to sustain the output voltage during a steep load transient. When the

load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. In

case the final application specifies high slew rate load transient, the system bandwidth must be maximized and

the output capacitor has to sustain the output voltage for time response shorter than the loop response time.

In Table 17. Output capacitors some capacitor series are listed.

Table 17. Output capacitors

Manufacturer

Series

GRM32

GRM31

ECJ

Cap value (μF)

22 to 100

10 to 47

Rated voltage (V)

ESR (mΩ)

<5

6.3 to 25

6.3

MURATA

<5

10 to 22

<5

PANASONIC

EEFCD

TPA/B/C

C3225

10 to 68

6.3

15 to 55

40 to 80

<5

SANYO

TDK

100 to 470

22 to 100

4 to 16

6.3

6.7

Application board

The reference evaluation board schematic is shown in the figure below.

Figure 52. Evaluation board schematic

TP1

TP3

R11

R10

NM

R5

NM

TP2

TP4

RST

SS/INH

SYNCH

U1

L6986H

RST

R6

1M

J3

4

15

2

1

VOUT

SYNCH

VIN

VIN_FLT

16

VBIAS

L1

10uH

13

14

VCC

FSW

MLF

LX

J5

R3

R1

NM

0

L1A

82k

NM

5

J2

6

C7

NM

9

7

FB

3

SS/INH

DELAY

EP

R8

75k C8

C4 2.2p

330p

R9

R7

240k

8

COMP

C11

NM

C3

R2

NM

R4

0

+

SGND

10

PGND PGND

11 12

470nF

10V

C5

68nF

C6

10nF

17

J1

signal GND

power GND

TP7

PGND

GND

J4

L3

size XAL5030 Coilcraft

L2 4.7uH

TP8

TP5

VIN_FLT

VIN

MPZ2012S221A

size 0805

VIN_EMI

TP6

PGND

GND

The additional input filter (C16, L3, C15, L2, C14) limits the conducted emission on the power supply (refer to

HTSSOP16 package information).

DS12905 - Rev 2

page 50/68

L6986H

Application board

Table 18. Bill of material (communal parts)

Reference

Part number

Description

Manufacturer

10 µF - 1206 - 50 V - X5R -

10%

C1, C9, C10

CGA5L3X5R1H106K

TDK

1 µF - 0805 - 50 V - X7R -

10%

C2

C3

CGA4J3X7R1H105K

-

470 nF - 10 V - 0603

See Table 19. L6986H 3V3

demonstration board BOM,

Table 20. L6986H 5V

demonstration board BOM,

and Table 21. L6986H adj.

demonstration board BOM

C4,C7,C8

-

C5

C6

-

68 nF - 10 V - 0603

10 nF - 10 V - 0603

4.7 µF - 1206 - 50 V - X7R -

10%

C14, C15, C16

CGA5L3X7R1H475K

TDK

C11, C13, C13A

R1, R4

Not mounted

0 Ω - 0603

R6

1 MΩ - 1%- 0603

See Table 19. L6986H 3V3

demonstration board BOM,

Table 20. L6986H 5V

demonstration board BOM,

and Table 21. L6986H adj.

demonstration board BOM

R7, R8, R9

R11

10 Ω - 1% - 0603

Not mounted

10 µH

R2, R3, R5, R10

L1

L2

L3

J1

J2

XAL5050-103MEC

XAL4030-472MEC

MPZ2012S221A

Open

Coilcraft

TDK

4.7 µH

EMC bead

Closed

Switchover disabled

See Table 19. L6986H 3V3

demonstration board BOM,

Table 20. L6986H 5V

demonstration board BOM,

and Table 21. L6986H adj.

demonstration board BOM

J3

J4

J5

Open

To adjust the ISKIP current

level in LCM operation. Leave

open in LNM

See Table 19. L6986H 3V3

demonstration board BOM,

Table 20. L6986H 5V

demonstration board BOM,

and Table 21. L6986H adj.

demonstration board BOM

U1

L6986H x-

ST

DS12905 - Rev 2

page 51/68

L6986H

Application board

Table 19. L6986H 3V3 demonstration board BOM

Reference

Part number

Description

0 R - 0603

Manufacturer

R7

R9, C7

R8

Not mounted

-

75 kΩ - 1% - 0603

330 pF - 10 V - 0603

2.2 pF - 10 V - 0603

C8

-

C4

-

J3

Open

U1

L6986H 3V3

3.3 V internal divider

STM

Table 20. L6986H 5V demonstration board BOM

Reference

Part number

Description

0 R - 0603

Manufacturer

R7

R9, C7

R7

Not mounted

-

0 Ω -0603

R8

100 kΩ - 1% - 0603

330 pF - 10 V - 0603

2.2 pF - 10 V - 0603

C8

C4

J3

Open

U1

L6986H 5V

5 V internal divider

STM

Table 21. L6986H adj. demonstration board BOM

Reference

Part number

Description

240 kΩ - 1% - 0603

Not mounted

Manufacturer

R7

C7

R9

R8

C8

C4

J3

-

82 kΩ - 1% - 0603

75 kΩ - 1% - 0603

330 pF - 10 V - 0603

2.2 pF - 10 V - 0603

Open

External divider (V

=3.3 V)

U1

L6986H

STM

OUT

Figure 53. Magnitude bode plot and Figure 54. Phase margin bode plot show the magnitude and phase margin

Bode plots related to the BOM of Table 21. L6986H adj. demonstration board BOM.

The small signal dynamic performance in this configuration is:

BW = 55kHz

pℎase margin = 60 ∘

(54)

DS12905 - Rev 2

page 52/68

L6986H

Application board

Figure 53. Magnitude bode plot

Figure 54. Phase margin bode plot

DS12905 - Rev 2

page 53/68

L6986H

Application board

Figure 55. Top layer

Figure 56. Bottom layer

DS12905 - Rev 2

page 54/68

L6986H

Efficency curves

6.8

Efficency curves

Figure 57. Efficiency: V_IN= 13.5 V - V_OUT= 3.3 V - f_sw= 500 kHz

Figure 58. Efficiency: V_IN= 13.5 V - V_OUT= 3.3 V - f_sw= 500 kHz (log scale)

DS12905 - Rev 2

page 55/68

L6986H

Efficency curves

Figure 59. Efficiency: V_IN= 13.5 V - V_OUT= 5 V - f_sw= 500 kHz

Figure 60. Efficiency: V_IN= 13.5 V - V_OUT= 5 V - f_sw= 500 kHz (log scale)

DS12905 - Rev 2

page 56/68

L6986H

Efficency curves

Figure 61. Efficiency: V_IN= 24 V - V_OUT= 3.3 V - f_sw= 500 kHz

Figure 62. Efficiency: V_IN= 24 V - V_OUT= 3.3 V - f_sw= 500 kHz (log scale)

DS12905 - Rev 2

page 57/68

L6986H

Efficency curves

Figure 63. Efficiency: V_IN= 24 V - V_OUT= 5 V - f_sw= 500 kHz

Figure 64. Efficiency: V_IN= 24 V - V_OUT= 5 V - f_sw= 500 kHz (log scale)

DS12905 - Rev 2

page 58/68

L6986H

Package information

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,

depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product

status are available at: www.st.com. ECOPACK is an ST trademark.

7.1

HTSSOP16 package information

Figure 65. HTSSOP16 package outline

DS12905 - Rev 2

page 59/68

L6986H

HTSSOP16 package information

Table 22. HTSSOP16 mechanical data

mm

Symbol

Min.

Typ.

Max.

1.20

0.15

1.05

0.30

0.20

5.10

3.2

A

A1

A2

b

0.80

0.19

0.09

4.90

2.8

1.00

c

D

5.00

3

D1

E

6.20

4.30

2.8

6.40

4.40

3

6.60

4.50

3.2

E1

E2

e

0.65

0.60

1.00

L

0.45

0.00

0.75

L1

K

8.00

0.10

aaa

DS12905 - Rev 2

page 60/68

L6986H

Ordering information

8

Ordering information

Table 23. Ordering information

Package

Part number

L6986H3V3

L6986H3V3TR

L6986H5V

Packing

Tube

Tape and reel

Tube

HTSSOP16

L6986H5VTR

L6986H

Tape and reel

Tube

L6986HTR

Tape and reel

DS12905 - Rev 2

page 61/68

L6986H

Revision history

Table 24. Document revision history

Date

Version

Changes

26-Mar-2019

27-Feb-2020

1

2

Initial release.

Updated I

Unit value in Table 5. Electrical characteristics.

Q OPVIN

DS12905 - Rev 2

page 62/68

L6986H

Contents

1

2

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Pin settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1

2.2

2.3

2.4

2.5

Pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1

4.2

4.3

Power supply and voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.3.1

4.3.2

Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4

4.5

4.6

4.7

4.8

Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Output voltage line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Output voltage load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

High-side switch resistance vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.8.1

4.8.2

4.8.3

Low noise mode (LNM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Quiescent current in LCM with switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.9

Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.9.1

4.9.2

LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.10 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.11 OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.12 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.13 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

DS12905 - Rev 2

page 63/68

L6986H

Contents

5

Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.1

5.2

5.3

5.4

5.5

G

(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

CO

Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Voltage divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6

Application notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

6.1

6.2

6.3

6.4

6.5

Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Voltage supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Synchronization (LNM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.5.1

6.5.2

Embedded master - slave synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

External synchronization signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.6

Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

6.6.1

6.6.2

6.6.3

Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.7

6.8

Application board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Efficency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7

8

Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

7.1

HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

DS12905 - Rev 2

page 64/68

L6986H

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

f_SWselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LNM/ LCM selection (L6986H3V3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LNM/ LCM selection (L6986H5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

LNM/ LCM selection (L6986H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. I_SKIPprogrammable current threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. SYNCH/ISKIP pin voltage thresholds and driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Example of oscillator frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 14. Example of oscillator frequency selection (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 15. Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 16. Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 17. Output capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 18. Bill of material (communal parts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 19. L6986H 3V3 demonstration board BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 20. L6986H 5V demonstration board BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 21. L6986H adj. demonstration board BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 22. HTSSOP16 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 23. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 24. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

DS12905 - Rev 2

page 65/68

L6986H

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Internal circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Soft-start phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Soft-start phase with precharged C_OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Enable the device with external voltage step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

External soft-start network V_STEPdriven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

External soft-start after UVLO or thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ratiometric start-up operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output voltage sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V_OUT= 3.3 V line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VOUT = 3.3 V load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Normalized R_DS(on),HSvariation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Low noise mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

L6986H skip current level transition at I_LOAD= 150 mA with L = 10 µH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Light-load efficiency comparison at different I_SKIP- linear scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Light-load efficiency comparison at different I_SKIP- log scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LCM operation with ISKIP_H= 600 mA typ. at zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

LCM operation with ISKIP_L= 200 mA typ. at zero load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

LCM operation over loading condition (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

LCM operation over loading condition (part 2-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LCM operation over loading condition (part 3-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LCM operation over loading condition (part 4-CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Quiescent current at V_OUT= 3.3 V and zero output load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Quiescent current at V_OUT= 5 V and zero output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Quiescent current at V_INwhile regulating V_OUT= 5 V at zero output load . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Valley current sense operation in overcurrent condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Peak current sense operation in overcurrent condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Output voltage oscillations during heavy short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Zoomed waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

V_BIASin heavy short-circuit event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Overvoltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Block diagram of the loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Transconductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Magnitude plot for example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Phase plot for example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

L6986H application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Voltage supervisor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Voltage supervisor operation during OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Input RMS current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Two regulators not synchronized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Two regulators synchronized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Synchronization pulse definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

L6986H synchronization driving capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Slave-to-master mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Figure 38.

Figure 39.

Figure 40.

Figure 41.

Figure 42.

Figure 43.

Figure 44.

Figure 45.

Figure 46.

Figure 47.

Figure 48.

Figure 49.

Figure 50.

DS12905 - Rev 2

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L6986H

List of figures

Figure 51.

Figure 52.

Figure 53.

Figure 54.

Figure 55.

Figure 56.

Figure 57.

Figure 58.

Figure 59.

Figure 60.

Figure 61.

Figure 62.

Figure 63.

Figure 64.

Figure 65.

Master driving capability to synchronize the L6986H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Magnitude bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Phase margin bode plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Bottom layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Efficiency: V_IN= 13.5 V - V_OUT= 3.3 V - f_sw= 500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Efficiency: V_IN= 13.5 V - V_OUT= 3.3 V - f_sw= 500 kHz (log scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Efficiency: V_IN= 13.5 V - V_OUT= 5 V - f_sw= 500 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Efficiency: V_IN= 13.5 V - V_OUT= 5 V - f_sw= 500 kHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Efficiency: V_IN= 24 V - V_OUT= 3.3 V - f_sw= 500 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Efficiency: V_IN= 24 V - V_OUT= 3.3 V - f_sw= 500 kHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Efficiency: V_IN= 24 V - V_OUT= 5 V - f_sw= 500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Efficiency: V_IN= 24 V - V_OUT= 5 V - f_sw= 500 kHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

HTSSOP16 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

DS12905 - Rev 2

page 67/68

L6986H

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST

products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST

products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of

Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service

names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DS12905 - Rev 2

page 68/68


型号：	L6986H5V
厂家：	ST
描述：	38 V, 2 A synchronous step-down switching regulator with 30 Î¼A quiescent current
文件：	总68页 (文件大小：18008K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6986H5V [STMICROELECTRONICS]

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