L9733TR [STMICROELECTRONICS]
BUF OR INV BASED PRPHL DRVR, PDSO28, ROHS COMPLIANT, SOP-28;
| 型号： | L9733TR |
| 厂家： | 
ST |
| 描述： | BUF OR INV BASED PRPHL DRVR, PDSO28, ROHS COMPLIANT, SOP-28 驱动 光电二极管 接口集成电路 |
| 文件： | 总34页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9733
Octal self configuring low/high side driver
Features
■ Eight independently self configuring low/high
drivers
■ Supply voltage from 4.5 V to 5.5 V
PowerSSO-28
■ RON(max) = 0.7 Ω @ T = 25 °C,
j
R
ON(max) = 1.2 Ω @T = 125 °C
j
■ Minimum current limit of each output 1 A
Outputs 1-8 are self-configuring as high or low-
side drives. Self-configuration allows a user to
connect a high or low-side load to any of these
outputs and the L9733 will drive them correctly as
well as provide proper fault mode operation with
no other needed inputs. In addition, outputs 6, 7 and
8 can be PWM controlled via a external pins (IN6-8).
■ Output voltage clamping min. 40 V in low-side
configuration
■
Output voltage clamping max. -14 V in high-side
configuration
■ SPI interface for outputs control and for
diagnosis data communication
This device is capable of switching variable load
currents over the ambient range of -40 °C to
+125 °C. The outputs are MOSFET drivers to
minimize Vdd current requirements. For low-side
configured outputs an internal zener clamp from
the drain to gate with a breakdown of 50 V
minimum will provide fast turn off of inductive
loads. When a high-side configured output is
commanded Off after having been commanded
On, the source voltage will go to (VGND - 15 V).
■ Additional PWM inputs for 3 outputs
■ Independent thermal shutdown for all outputs
open load, short to GND, short to Vb,
overcurrent diagnostics in latched or unlatched
mode for each channel
■ Internal charge pump without need of external
capacitor
■ Controlled SR for reduced EMC
An 16 bit SPI input is used to command the 8
output drivers either "On" or "Off", reducing the
I/O port requirement of the microcontroller.
Multiple L9733 can be daisy-chained. In addition
the SPI output indicates latched fault conditions
that may have occurred.
Description
The L9733 is a highly flexible monolithic, medium
current, output driver that incorporates 8 outputs
that can be used as either internal low or high-side
drives in any combination.
Table 1.
Device summary
Order code
Package
Packing
L9733XP
PowerSSO-28 (Exposed pad)
PowerSSO-28 (Exposed pad)
Tube
L9733XPTR
Tape and reel
May 2009
Doc ID 11319 Rev 9
1/34
www.st.com
1
Contents
L9733
Contents
1
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Functional operative range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Jump start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operation at low battery condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operation at load dump condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Loss of protection against short to battery . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
Electrical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
3.3
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Configurations for outputs 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1
4.1.2
Low-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
4.3
4.4
4.5
Outputs 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Outputs 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Drn1-8 susceptibility to negative voltage transients . . . . . . . . . . . . . . . . . 19
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.1
4.5.2
4.5.3
Main power input (Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Battery supply (Vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Discrete inputs voltage supply (VDO) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
Discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.1
4.6.2
Output 6-8 enable input (In6, ln7, ln8) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset input (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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L9733
Contents
5.1
5.2
5.3
5.4
5.5
5.6
Serial data output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial data input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chip select (CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Initial input command register and fault register SPI cycle . . . . . . . . . . . . 22
Input command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
7
Other L9733 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
6.2
6.3
6.4
Charge pump usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
POR register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fault operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
7.2
Low-side configured output fault operation . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1.1
7.1.2
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-side configured output fault operation . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.1
7.2.2
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
10
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List of tables
L9733
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI characteristics and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bit command register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Command register logic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Fault register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fault logic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/34
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L9733
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output turn on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output loading for slew rate measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI input/output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
L9733 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
L9733 HVAC applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
L9733 powertrain applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Optimized circuit layout to achieve proper EMI/ESD capability . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. PowerSSO28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 11319 Rev 9
5/34
Pin description
L9733
1
Pin description
Figure 1.
Pin connection (top view)
VDD
SCLK
CS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDO
D0
2
3
D1
SRC1
DRN1
DRN2
SRC2
SRC3
DRN3
DRN4
SRC4
IN6
4
SRC8
DRN8
DRN7
SRC7
SRC6
DRN6
DRN5
SRC5
RES
5
6
7
8
9
10
11
12
13
14
IN7
IN8
Vbat
GND
D06AT544
Table 2.
N°
Pin description
Pin
Function
1
2
VDD 5 Volt supply input
SCLK SPI serial clock input
3
CS
SPI chip select (active low)
4
SRC1 Source pin of configurable driver #1 (0.7 Ω Rdson @ +25 °C)
DRN1 Drain pin of configurable driver #1(0.7 Ω Rdson @ +25 °C)
DRN2 Drain pin of configurable driver #2 (0.7 Ω Rdson @ +25 °C)
SRC2 Source pin of configurable driver #2 (0.7 Ω Rdson @ +25 °C)
SRC3 Source pin of configurable driver #3 (0.7 Ω Rdson @ +25 °C)
DRN3 Drain pin of configurable driver #3 (0.7 Ω Rdson @ +25 °C)
DRN4 Drain pin of configurable driver #4 (0.7 Ω Rdson @ +25 °C)
SRC4 Source pin of configurable driver #4 (0.7 Ω Rdson @ +25 °C)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
IN6
IN7
Discrete input used to PWM output driver #6
Discrete input used to PWM output driver #7
Vbat Battery supply voltage
GND Analog ground
IN8
Discrete input used to PWM output driver #8
RES Reset input (active low)
SRC5 Source pin of configurable driver #5 (0.7 Ω Rdson @ +25 °C)
6/34
Doc ID 11319 Rev 9
L9733
Pin description
Table 2.
N°
Pin description (continued)
Pin
Function
19
20
21
22
23
24
25
26
27
28
DRN5 Drain pin of configurable driver #5 (0.7 Ω Rdson @ +25 °C)
DRN6 Drain pin of configurable driver #6 (0.7 Ω Rdson @ +25 °C)
SRC6 Source pin of configurable driver #6 (0.7 Ω Rdson @ +25 °C)
SRC7 Source pin of configurable driver #7 (0.7 Ω Rdson @ +25 °C)
DRN7 Drain pin of low-side driver #7 (0.7 Ω Rdson @ +25 °C)
DRN8 Drain pin of low-side driver #8 (0.7 Ω Rdson @ +25 °C)
SRC8 Source pin of configurable driver #8 (0.7 Ω Rdson @ +25 °C)
DI
SPI data in
DO
SPI data out
VDO Microcontroller logic interface voltage
Note:
The exposed slug must be soldered on the PCB and connected to GND.
Doc ID 11319 Rev 9
7/34
Operating conditions
L9733
2
Operating conditions
2.1
Operating range
This part may not operate if taken outside the operating range. Once the condition is
returned to within the specified maximum rating or the power is recycled, the part will
recover with no damage or degradation.
Table 3.
Symbol
Vdd
Operating range
Parameter
Value
Unit
Supply voltage
4.5 to 5.5
V
V
bat (operative
range)
4.5V to 18
18 to 27
Vbat @ JSC
Battery supply voltage
V
V
bat @ low
battery
3.5 to 4.5
V
bat @ load
dump
27 to 40
Tj
Thermal junction temperature range
Snubbing voltage of DRN1-8
Output current 1-8
-40 to 150
min 50
max 800
20
°C
VDC
mA
mJ
IOx
Eso
Maximum clamping energy at switch-off
2.1.1
2.1.2
Functional operative range
4.5 V ≤ V ≤ 18 V (-40 °C ≤ T ≤ 150 °C);
bat
j
All the electrical capabilities are guaranteed by characterization as reported in Section 3:
Electrical performance characteristics.
Jump start conditions
18 V ≤ V ≤ 27 V (-40 °C ≤ T ≤ 150 °C);
bat
j
Operation at Jump start condition for a maximum duration of 1 minute.
All ouputs are switched according to the commands on the SPI bus or the PWM inputs. The
SPI bus and the inputs are functional during the Jump-Start condition.
The over-temperature shutdown and over current protection of the device is not guaranteed
to stay functional for Vbat between 18 V and 27 V.
The reliability and the functionality of the L9733XP are not compromised when the Jump-
Start condition is not repeated for more than five times.
8/34
Doc ID 11319 Rev 9
L9733
Operating conditions
2.1.3
Operation at low battery condition
3.5 V ≤ V ≤ 4.5 V (-40 °C ≤ T ≤ 150 °C);
bat
j
All outputs are able to keep the status in according to the commands on the SPI bus or the
PWM inputs. Switching commands entered via the SPI bus might not be executed by the
L9733 at low-battery condition. The SPI bus and the inputs are functional during the Low-
Battery condition.
2.1.4
Operation at load dump condition
27 V ≤ V ≤ 40 V (-40 °C ≤ T ≤ 150 °C)
bat
j
There is not an internal circuit that switches OFF the drivers during load dump condition.
The over-temperature shutdown and over current protection of the device is not guaranteed
to stay functional during load dump condition.
2.1.5
Loss of protection against short to battery
When the battery supply voltage, V
is switched off during a short-to-battery
bat (pin 14)
condition at a output in high-side configuration, the protection circuits are no longer
functional, and the L9733 may fail with EOS.
2.2
Absolute maximum ratings
This part may be irreparably damaged if taken outside the specified absolute maximum
ratings. Operation outside the absolute maximum ratings may also cause a decrease in
reliability.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDD
Vbat
Supply voltage
-0.3 to 7
-0.3 to 40
-0.3 to 7.0
min. -24
V
V
Supply voltage
CS,DI,DO,SCLK,EN,IN6,IN7,IN8,VDO
SRCx pin
V
VDC
Max. value of VSRCx = Minimum of {Vbat +1V ||| VDRNx+0,3 V ||| +40 V}
DRN1-8(1)
-0.3 to 60
VDC
A
IOL
IOP
Current limit of output 1-8 (-40 °C)
Over current protection at output 1-8 (-40 °C)
Maximum clamping energy
2.5
3
A
20
mj
kV
kV
Human body model - All pins
Human body model - Driver outputs
2 (2)
4 (2)
ESD
1. For the DRNx the MAX ASB value is the Max Clamp Voltage (see Table 6 on page 13 - DRNx Clamp
voltage).
2. Device is only protected vs. GND.
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Operating conditions
L9733
Unit
2.3
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Min
Typ
Max
Tamb
Tstg
Operating ambient temperature
Storage temperature
-40
-
125
150
150
200
25
°C
°C
-50
-
-
Tj
Maximum operating junction temperature
Thermal shutdown temperature
Thermal shutdown temperature hysteresis
-
°C
Rth
151
175
10
-
°C
Rth-hys
7
-
°C
RTh j-amb Thermal resistance junction-to-ambient (1)
RTh j-case Thermal resistance junction-to-case
1. With 2s2p PCB thermally enhanced.
24
°C/W
°C/W
-
-
3
10/34
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L9733
Electrical performance characteristics
3
Electrical performance characteristics
These are the electrical capabilities this part was designed to meet. It is required that every
part meet these characteristics.
3.1
DC characteristics
Tamb = -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc (high-side configuration),
unless otherwise specified.
Table 6.
DC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IN6vih
IN6vil
IIN6il
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.7vdo
-
V
V
IN6 input voltage
0.3vdo
In6 = 0 VDC
-
|10|
100
0.7vdo
-
μA
μA
V
IN6 input current
IN7 input voltage
IN7 input current
IN8 input voltage
IN8 input current
CS input voltage
CS input current
SCLK input voltage
SCLK input current
DI input voltage
DI input current
IIN6ih
IN7vih
IN7vil
IIN7il
In6 = VDO
10
-
0.3vdo
V
In7 = 0 VDC
In7 = VDO
-
|10|
100
0.7vdo
-
μA
μA
V
IIN7ih
IN8vih
IN8vil
IIN8il
10
-
0.3vdo
V
In8 = 0 VDC
In8 = VDO
-
|10|
100
0.7vdo
-
μA
μA
V
IIN8ih
CSih
10
-
CSil
0.3vdo
V
ICSih
ICSil
CS = VDO
-
|10|
100
0.7vdo
-
μA
μA
V
CS = 0 VDC
10
SCLKih
SCLKil
ISCLKih
ISCLKil
DIih
-
0.3vdo
V
SCLK = VDO
-
|10|
100
0.7vdo
-
μA
μA
V
SCLK = 0 VDC
10
-
DIil
0.3vdo
V
IDIih
DI = VDO
-
|10|
100
0.4
μA
μA
V
IDIil
DI = 0 VDC
IDO = 2.5 mA
IDO = -2.5 mA
10
-
DOol
DOoh
DO output voltages
vdo-0.6
-
V
Doc ID 11319 Rev 9
11/34
Electrical performance characteristics
L9733
Units
Table 6.
Symbol
DC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
IDOzol
IDOzoh
RESih
RESil
IRESil
DO = 0 VDC
DO = VDO
-
-
-
-
-
-
-
-
-
-
|10|
|10|
0.7vdo
-
μA
μA
V
DO Tri-state currents
RES input voltage
RES input current
-
-
0.3vdo
10
V
RES = 0 VDC
RES = VDO
@ -40 °C
100
|10|
4.2
μA
μA
IRESih
-
2.8
2.8
2
PORth
Power on reset threshold
@ 25 °C
3.7
V
@ 125 °C
3.4
VDD = SRC1-8 = 0VDC
DRN1-DRN8=18VDC, Vb. Sum
currents (Tamb > 0 °C)
Islp
Vbat sleep current
Vbat current
-
-
-
10
3
μA
μA
(Tamb @ -40 °C)
VDD = 5 V
Ivbat
-
15
mA
All Outputs Commanded On
IVDD
IVDD
Max. VDD current
Min. VDD current
All Outputs Commanded On
All Outputs Commanded Off
-
-
-
8.5
mA
mA
0.5
DRN1 - DRN8
leakage currents
(low-side)
VDD = 0 VDC: SRC1-8 = 0 VDC
DRN1- DRN8 = 16 VDC
IDRN1lk
IDRN8lk
-
-
-
-
-
-
5
μA
μA
DRN1- DRN8 = 40 VDC
10
VDD = 0 VDC: SRC1-8 = 0 VDC
DRN1- 8 = 16 V
SRC1 – SRC8
ISRC1lk
ISRC8lk.
-
-5
μA
μA
Leakage currents
(high-side)
DRN1- 8 = 40 VDC
-10
SRC1-8 = GND DI = AC00h
Rload ≤ 11 kΩ
Rload ≤ 200 kΩ
DRN1 – DRN8 sink current
(low-side)
IDrn1-8sink
10
100
280
μA
μA
120
Open load detection
resistance
RDRN1-8
VBAT>=9V
11
-
-
-
-
200
KΩ
μA
IDrn1-8source Source current
DRN1-DRN8 = GND
-10
-100
DRN1- 8 = Vb, DI = AC00h
SCR1- 8 = Vb
SRC1 – SRC8
Isrc1-8sink
10
100
μA
μA
sink/source current
(high-side)
Isrc1-8source
SCR1- 8 = GND
-18
-100
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
VDD=4.9 to 5.1 VDC
2.7
2.5
-
-
3.1
3.5
V
V
DRN1 – DRN8
VDrn1-8open open load voltage
(low-side)
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
VDD = 4.5 to 5.5 V
12/34
Doc ID 11319 Rev 9
L9733
Electrical performance characteristics
Table 6.
DC characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
SRC1 – SRC8 open load
Vsrc1-8open voltage (High-side)
DRN1 - DRN8
DRN1-8 = Vb, DI = AC00h
SCR1-8 = open
2.0
-
2.8
V
DI = ACFFh, DI = AAFFh
SRC1 – SRC8 = 0 VDC
DRN1 - DRN8
IDRN1limit
IDRN8limit
-
-
-
current limits
(low-side)
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0 °C)
1
1
2.2
2.5
A
A
(Tamb @ -40 °C)
DI = AC00h, DI = AA00h SRC1 –
SRC8 = 0 VDC
DRN1 - DRN8
overcurrent threshold
(low-side)
IDRN1OVC
-
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0 °C)
IDRN8OVC
1
1
2.7
3
A
A
(Tamb - 40 °C)
DI = ACFFh, DI = AAFFh
DRN1 - DRN8 = Vb
SRC1 – SRC8
current limits
(high-side)
ISRC1limit
ISRC8limit
-
-
-
SRC1 – SRC8 = GND
(Tamb > 0 °C)
1
1
2.2
2.5
A
A
(Tamb - 40 °C)
DRN1 - DRN8 = Vbat
Overcurrent threshold
(high-side)
ISRC1OVC
ISRC8OVC
-
SRC1 – SRC8 = GND
(Tamb > 0 °C)
1
1
2.7
3
A
A
(Tamb - 40 °C)
DRN1 - DRN8
DI = AC00h
DRN1Cl+
DRN8Cl+
-
50
-
-
60
V
V
Clamp voltages (low-side) SRC1-8 = GND, IDRN1-8 = 350 mA
SRC1 – SRC8 DI = AC00h
Clamp voltages (High-side) DRN1-8 = Vbat, ISRC1-8 = -350 mA
SRC1Cl+
SRC8Cl+
-
-24
-14
VDrn1-8open
SRC1 – SRC8 = GND:
Short to GND threshold
distance from open load
voltage (low-side)
0.3
0.3
-
-
0.7
0.7
V
V
- DRN1-
8VthGND
Decrease Drn1 - Drn8 until Faults
are ”Set”
DRN1 - DRN8
DI = AC00h
DRN1-
Short to Vbat threshold
distance from open load
voltage (low-side)
SRC1 – SRC8 = GND: Increase
Drn1 - Drn8 until Faults are ”Not
Set”
8VthVbat
VDrn1-8open
-
SRC1 - SRC8
VDrn1-8open
DI = AC00h
Short to GND threshold
distance from open load
voltage (High-side)
0.2
0.2
-
-
0.6
0.6
V
V
- SRC1-
8VthGND
Drn1 – Drn8 = Vb: Decrease SRC1
- SRC8 until Faults are ”Not Set”
SRC1 – SRC8
DI = AC00h
SRC1-
8VthVbat
VDrn1-8open
Short to Vbat threshold
distance from open load
voltage (High-side)
Drn1 – Drn8 = Vbat: Increase
SCR1 - SCR8 until Faults are ”
Set”
-
Doc ID 11319 Rev 9
13/34
Electrical performance characteristics
L9733
Units
Table 6.
Symbol
DC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
@ +125 °C @ IDRN = 350 mA
@ +25 °C @ IDRN = 350 mA
@ -40 °C @ IDRN = 350 mA
-
-
-
-
-
1.2
0.7
0.5
Ω
Ω
Ω
On resistance
(Drn to SRC1-8)
(1)
RdsonDrn1-8
DI = ACFFh, IDrn1-8 = 1 mA,
Thermal shutdown
temperature
SRC1 – SRC8 = GND, Increase
temperature until Drn1 - Drn8 > 2
VDC, Verify DO Bits 0-15 are ”Set”
(2)
Drn1-8ther
151
5
-
-
200
15
°C
°C
(2)
Drn1-8hyst
Hysteresis
Drn1 - Drn8 < 2 VDC
1. RdsonDrn1-8 ≤ 1.2 Ω; at Vbat between 3.5 V and 27 V and T between -40 °C and 150 °C
2. Design Information, not tested.
3.2
AC characteristics
Tamb = -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc, unless otherwise specified
Table 7.
AC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRN1 - DRN8
DI = AC00h, DI = A3FFh
SRC1 – SRC8 = GND
Open load & short to
GND filter time (low-side)
TfiltDRN1-8
300
-
900
μs
(Latch mode)
SRC1 - SRC8
Open load & short to
Vbat filter time
(high-side)
DI = AC00h, DI = A3FFh
DRN1 – DRN8 = Vb
TfiltSRC1-8
300
10
-
-
900
75
μs
μs
(Latch mode)
DRN1 - DRN8
Overcurrent switch off
delay
DI = ACFFh, DI = AA00h
SRC1 – SRC8 = GND
TdelDRN1-8
(low-side)
SRC1 - SRC8
Overcurrent switch off
delay
DI = ACFFh, DI = AA00h
DRN1 – DRN8 = Vb
TdelSRC1-8
10
-
-
75
μs
(high-side)
Restart time after
overcurrent switch off
time (Int)
T
DI = ACFFh, DI = AA00h
120
450
ms
res
Slew rate
turn on
Outputs loaded as Figure 4
See Figure 2
Drn1-8htol
Drn1-8ltoh
-
-
0.65
0.5
1.95
1.5
V/μs
V/μs
Turn off (low-side)
See Figure 2
14/34
Doc ID 11319 Rev 9
L9733
Electrical performance characteristics
Table 7.
AC characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Slew rate
turn on
Outputs loaded as Figure 4
See Figure 2
SRC1-8htol
-
0.65
0.5
1.95
1.5
V/μs
V/μs
SRC1-8ltoh Turn off (High-side)
-
-
-
-
-
See Figure 2
Outputs loaded as Figure 4
See Figure 2
Delay time
Drn1-8tondly
Turn on
2
20
μs
μs
Drn1-8toffdly Turn off (low-side)
10
100
See Figure 2
Delay time
SRC1-8tondly
Outputs loaded as Figure 4
See Figure 2
Turn on
2
20
μs
μs
SRC1-8toffdly Turn off (high-side)
10
100
See Figure 2
Drn1-8offon Delay delta
SRC1-8offon Delay delta
Drn1-8toffdly - Drn1-8tondly
SRC1-8toffdly - SRC1-8tondly
10
10
-
-
60
60
μs
μs
Figure 2.
Output turn on/off delays and slew rates
6-8
IN
IN 6-8
-
90%
90%
20%
DRN1-8
20%
LSD
HSD
DRN1-8
DRN1-8ltoh
DRN1-8htol
DRN1-8toffdly
DRN1-8tondly
80%
10%
80%
10%
SRC1-8
SRC1-8
SRC1-8htol
SRC1-8toffdly
SRC1-8ltoh
SRC1-8tondly
IN1- 5 are available on wafer only
Doc ID 11319 Rev 9
15/34
Electrical performance characteristics
L9733
3.3
SPI characteristics and timings
Tamb= -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc, unless otherwise specified
Table 8.
SPI characteristics and timings
Parameter
Symbol
Conditions
Min
Typ
Max
Units
DINCin
-
-
-
-
20
20
pF
pF
Input capacitance
SCLKCin
50 pF from DO to Ground
Output data (do)
rise time
DOrise
DOfall
-
-
-
-
70
70
ns
ns
See Figure 5
Output data (do)
fall time
See Figure 5
DOa
DOsum
DOhm
Access time
Set up time
Hold time
See Figure 6
See Figure 6
See Figure 6
-
-
-
-
350
ns
ns
ns
20
10
-
-
Output data (DO)
disable time
DOdis
No Capacitor on DO, See Figure 5
-
-
400
ns
tthFilt
Filter time
All Fault bits are “Set”
5
185
58
58
-
-
-
-
-
-
-
20
-
μs
ns
ns
ns
ns
ns
SCLKwid
SCLKlm
SCLKhm
SCLKrise
SCLKfall
SCLK width
See Figure 5, @ fSCLK = 5.4MHz(1)
See Figure 5, @ fSCLK = 5.4MHz(1)
See Figure 5, @ fSCLK = 5.4MHz(1)
See Figure 5, @ fSCLK = 5.4MHz(1)
See Figure 5, @ fSCLK = 5.4MHz(1)
SCLK low time
SCLK high time
SCLK rise time
SCLK fall time
-
-
21
21
-
Channel select (CS)
rise time
CSrise
CSfall
CSlead
CSlag
DIrise
DIfall
See Figure 5 (1)
See Figure 5 (1)
-
-
-
-
-
-
-
-
-
100
100
-
ns
ns
ns
ns
ns
ns
ns
Channel select (CS)
fall time
Channel select (CS)
lead time
(1)
See Figure 6
455
50
-
Channel select (CS)
lag time
(1)
See Figure 6
-
Input data (DI)
rise time
See Figure 5, @ fSCLK = 5.4MHz(1)
See Figure 5 @ fSCLK = 5.4MHz(1)
See Figure 6, @ fSCLK = 5.4MHz(1)
30
30
-
Input data (DI)
fall time
-
Input data (DI)
set-up time
DIsus
15
Input data (DI)
hold time
DIhs
See Figure 6, @ fSCLK = 5.4MHz(1)
See Figure 6, @ fSCLK = 5.4MHz(1)
10
40
-
-
-
ns
ns
CS2SCLK
CS rise to SCLK rise
300
1. Guaranteed by design.
16/34
Doc ID 11319 Rev 9
L9733
Electrical performance characteristics
DO loading for disable time measurement
Figure 3.
+5 V
Vcc
4.0 V
DOdis
DO
1 k
1 k
Ω
Ω
1.0 V
DO
0 V
CS
Figure 4.
Output loading for slew rate measurements
All High Side Outputs must
meet the slew rate requirements
of this load condition
Vbat
180Ω
Outputs 1-8
Outputs 1-8
180 Ω
All Low Side Outputs must
meet the slew rate requirements
of this load condition
Figure 5.
SPI input/output timings
SCLKwid
SCLKlm
SCLKhm
90%
10%
SCLKrise
SCLK
CLKfall
S
90%
90%
CS
DI
CSrise
10%
CSfall
90%
DIrise
10%
DIfall
DO
DOrise
DOfall
10%
Figure 6.
SPI timing diagram
CS
CSlead
CSlag
SCLK
DOa
CS2SCLK
DOdis
DOhm
DOsum
DO
FAULT LSB
FAULT MSB
DI
DI
DI LSB
DI MSB
DIsus
DIhs
Doc ID 11319 Rev 9
17/34
Functional description
L9733
4
Functional description
L9733 integrates 8 self-configuring outputs (OUT1-8) which are able to drive either
incandescent lamps, inductive loads (non-pwm'd, in pwm is necessary an external diode to
reduce flyback power dissipation), or resistive loads biased to Vbat (low-side configuration)
or to GND (high-side configuration). These outputs can be enabled and disabled via the SPI
bus. Each of these outputs has a short circuit protection (with 0.8-2.4 Amps threshold)
selectable via SPI bus between a filtered switching OFF overcurrent protection or a linear
current limitation (default condition after power ON is switching OFF protection enabled).
An over-temperature protection as described in Section 2.1 is available for each outputs.
When a high-side configured output is commanded OFF after having been commanded ON,
the source voltage will go to (VGND - 15 V). This is due to the design of the circuitry and the
transconductance of the MOSFET. When a low-side configured output is commanded OFF
after having been commanded ON, the output voltage will rise to the internal zener clamp
voltage (50 VDC minimum) due to the flyback of the inductive load.
Outputs 1-8 are able to drive any combination of inductive loads or lamps at one time.
Inductive loads for the L9733 can range from 35mH to a maximum of 325 mH. The
recommended worst-case solenoid loads (at -40 °C) are calculated using a minimum
resistance of 40Ω for each output. The maximum single pulse inductive load energy the
L9733 outputs is able to be safely handle is 20 mJ at -40 °C to 125 °C (Worst-case load of
325 mH and 40 Ω).
4.1
Configurations for outputs 1-8
The drain and source pins for each output must be connected in one of the two following
configurations (see Figure 7).
4.1.1
Low-side drivers
When any combination of outputs 1-8 are connected in a low-side drive configuration the
source of the applicable output (Src1-8) shall be connected to ground. The drain of the
applicable output (Drn1-8) shall be connected to the low-side of the load.
4.1.2
High-side drivers
When any combination of outputs 1-8 are connected in a high-side drive configuration the
Drain of the applicable output (Drn1-8) shall be connected to Vbat. The source of the
applicable output (Src1-8) shall be connected to the high-side of the load.
4.2
Outputs 1-5
These five outputs can be used as either high or low-side drives. The room temperature
Rdson of these outputs is 0.7 Ω. A current limited (100 µA max) voltage generator is
connected to Src 1-5 for open load and short to GND detection when a low-side configured
output is commanded OFF. Another current limited (100 µA max if VDrn 1-5 > 60 %Vbat,
280 µA max if VDrn 1-5 < 60 % Vbat) voltage generator is connected to Drn 1-5 for open
load and short to V bat detection when a high-side configured output is commanded OFF.
Drain pins of outputs 1-5 (Drn1-5) are connected to the drains of the N channel MOSFET
18/34
Doc ID 11319 Rev 9
L9733
Functional description
transistors. Source pins of outputs 1-5 (Src1-5) are connected to the sources of the
N-channel MOSFET transistors.
4.3
Outputs 6-8
These three self-configuring outputs can be used to drive either high or low-side loads. In
addition to being controlled by the SPI BUS these outputs can also be enabled and disabled
via the IN6 & IN7& IN8 inputs. The IN6, IN7 and IN8 inputs are logically or'd with the SPI
commands to allow either the IN6 & IN7 & IN8 inputs or the SPI commands to activate these
outputs. The use of the IN6 & IN7 & IN8 pins for PWM control on these outputs should only
be done with non-inductive loads if an external flyback diode is not present. The room
temperature Rdson of these four outputs is 0.7 Ω. A current limited (100µA max) voltage
generator is connected to Src 6-8 for open load and short to GND detection when a low-side
configured output is commanded OFF. Another current limited (100µA max if VDrn 6-8 >
60%Vbat, 280 µA max if VDrn 6-8 < 60 %Vbat) voltage generator is connected to Drn 6-8
for open load and short to Vbat detection when a high-side configured output is commanded
OFF.
Drain pins of Outputs 6-8 (Drn6-8) are connected to the drains of the N channel MOSFET
transistors. Source pins of Outputs 6-8 (Src6-8) are connected to the sources of the N
channel MOSFET transistors.
4.4
Drn1-8 susceptibility to negative voltage transients
All outputs connected in the low-side configuration must have a ceramic chip capacitor of
0.01µF to 0.1 µF connected from drain to ground. This is needed to prevent potential
problems with the device operation due to the presence of fast negative transient(s) on the
drain(s) of the device. Adequate de-coupling capacitors from the Drain (VBAT) to ground
shall be provided for high-side configured outputs.
4.5
Supply pins
4.5.1
Main power input (Vdd)
An external +5.0 0.5 VDC supply provided from an external source is the primary power
source to the L9733. This supply is used as the power source for all of its internal logic
circuitry and other miscellaneous functions.
4.5.2
4.5.3
Battery supply (Vbat)
This input is the supply for the on board charge pump. This input shall be connected directly
to battery. If this input is not connected to the same supply, without additional voltage drops,
of the drains of any high-side connected outputs, then the Rdson of that given output will be
higher than the specified maximum.
Discrete inputs voltage supply (VDO)
This pin is used to supply the discrete input stages of L9733 and must be connected to the
same voltage used to supply the peripherals of the processor interfaced to L9733.
Doc ID 11319 Rev 9
19/34
Functional description
L9733
4.6
Discrete inputs
4.6.1
Output 6-8 enable input (In6, ln7, ln8)
This input allows Output 6 (or Output 7, or Output 8) to be enabled via this external pin
without the use of the SPI. The SPI command and the In6-7 input are logically or'd together.
A logic "1" on this input (In6, ln7 or ln8) will enable this output no matter what the status of
the SPI command register. A logic "0" on this input will disable this output if the SPI
command register is not commanding this output on. This pins (In6, ln7 or ln8) can be left
"open" if the internal output device is being controlled only via the SPI. This input has a
nominal 100kΩ resistor connected from this pin to ground, which will pull this pin to ground if
an open circuit condition occur. This input is ideally suited for non-inductive loads that are
pulse width modulated (PWM'd). This allows PWM control without the use of the SPI inputs.
4.6.2
Reset input (RES)
When this input goes low it resets all the internal registers and switches off all the output
stages. This input has a nominal 100 kΩ resistor connected from this pin to VDD, which will
pull this pin to VDD if an open circuit condition occur.
20/34
Doc ID 11319 Rev 9
L9733
Serial peripheral interface (SPI)
5
Serial peripheral interface (SPI)
The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out
(DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input
pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper
operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The
design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need
for controller pins.
5.1
5.2
5.3
Serial data output (DO)
This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this
pin transmits 16 bits of data from the fault register to the digital controller. After the first 16
bits of DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then
the DO output sequentially transmits the digital data that was just received (16 SCLK cycles
earlier) on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data
from the DI input until CS eventually transitions from a logic '0' to a logic '1'. DO data
changes state 10 nsec or later, after the falling edge of SCLK. The LSB is the first bit of the
byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO, once CS
transitions from a logic '1' to a logic '0'.
Serial data input (DI)
This input takes data from the digital controller while CS is low. The L9733 accepts an 16 bit
byte to command the outputs on or off. The L9733 also serially wraps around the DI input
bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first
bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once
CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte
are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing
mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal
100 kΩ resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an
open circuit condition occurs.
Chip select (CS)
This is the chip select input pin. On the falling edge of CS, the DO pin is released from tri-
state mode. While CS is low, register data are shifted in and shifted out the DI pin and DO
pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tri-
stated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte
is defined as such:
–
–
a multiple of 16 bits was received.
a valid key-word was received
The fault data is not cleared unless all of the 2 previous conditions have been met. The CS
input has a nominal 100 kΩ resistor connected from this pin to the VDO pin, which pulls this
pin to VDO if an open circuit condition occurs.
Doc ID 11319 Rev 9
21/34
Serial peripheral interface (SPI)
L9733
5.4
Serial clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
The SCLK input has a nominal 100kΩ resistor connected from this pin to the VDO pin,
which pulls this pin to VDO if an open circuit condition occurs.
5.5
Initial input command register and fault register SPI cycle
After initial application of Vdd to the L9733, the input command register and the fault register
are "Cleared" by the POR circuitry and that means that the default condition for the output
status is Off, the default diagnostic mode is No Latch and the switching OFF overcurrent
protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data
will be clocked out of DO (fault bits).
5.6
Input command register
An input byte (16 bits) is routed to the Command Register. The content of this Command
Register is given in table 9. Additional DI data will continue to be wrapped around to the DO
pin. If CS should happen to go high before complete reception of the current byte, this just
transmitted byte shall be ignored (invalid).
Table 9.
Bit command register definition
Key word
Writing mode: output
Output status
MSB
LSB
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
1
0
1
0
1
1
0
0
b15 b14 b13
b12
b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Key word
MSB
Writing mode: diag
Driver diag mode
LSB
1
0
1
0
0
0
1
1
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1
b15 b14 b13
b12
b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Key word
MSB
Writing mode: protect
Driver overcurrent protection
LSB
1
0
1
0
1
0
1
0
Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2 Ilim 1
b7 b6 b5 b4 b3 b2 b1 b0
b15 b14 b13
b12
b11 b10
b9
b8
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L9733
Serial peripheral interface (SPI)
Writing mode
Table 10. Command register logic definition
Bit
State
Status
b0-b7
b0-b7
b0-b7
b0-b7
b0-b7
b0-b7
0
1
0
1
0
1
OUT1 - OUT8 are commanded off
Output
Output
Diag
OUT1 - OUT8 are commanded on
OUT1 - OUT8 diagnostic is No Latch Mode
OUT1 - OUT8 diagnostic is Latch Mode
Diag
OUT1 - OUT8 switching OFF overcurrent protection
OUT1 - OUT8 linear overcurrent protection
Protection
Protection
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Other L9733 features
L9733
6
Other L9733 features
6.1
Charge pump usage
In order to provide low Rdson values when connected in a high-side configuration, a charge
pump to drive the internal gate voltage(s) above Vbat is implemented. The charge pump
used on the L9733 doesn't need external capacitor. The L9733 uses a common charge
pump and oscillator for all the 8 configurable output channels. The charge pump uses the
Vbat supply connected directly to the Vb pin. The normal range of the Vbat voltage is 10 to
18V18V. However, the L9733 is functional with Vbat voltages as low as 4.5V DC with
eventually a degradation of Rdson.
The frequency range of this charge pump is from 3.6 to 7.6 MHz. The frequency is above
1.8 MHz in order to be above the AM radio band and below 8.0 MHz so that harmonics do
not get within the FM radio band.
6.2
6.3
Waveshaping
Both the turn on and the turn off slew rates on all outputs (OUT1-8) are limited to between
10 µs and 100 µs for both rise and fall times (10 to 90 %, and vice versa), to reduce
conducted EMC energy in the vehicle's wiring harness. The characteristics of the turn-on
and turn-off voltage is linear, with no discontinuities, during the output driver state transition.
POR register initialization
When the L9733 wakes up, the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0.3 to
3ms. The L9733 has a POR circuit, which monitors the Vdd voltage. When the Vdd voltage
reaches an internal threshold, and remains above this trip level for at least 5 to 20 µs, the
Command and Fault registers are "cleared". Before Vdd reaches this trip level, none of the
eight outputs are allowed to momentarily glitch on.
6.4
Thermal shutdown
Each of the eight outputs has independent thermal protection circuitry that disables each
output driver once the local N-Channel MOSFET's device temperature reaches between
+151 and +200 °C. A filter is present to validate the thermal fault (5 µs to 20 µs). There is a
5 to 15 °C hysteresis between the enable and disable temperature levels. The faulted
channel will periodically turn off and on until the fault condition is cleared, the ambient
temperature is decreased sufficiently or the output is commanded off. If a thermal shutdown,
of one or more output drivers, is active during the falling edge of the chip select (CS) signal
all the bits of the Fault Register are "setted" to "1" (thermal shutdown is not latched and
could be read only in the moment it is present). The thermal fault is cleared on the rising
edge of Chip Select if a valid DI byte was received.
Note:
Due to the design of the L9733 each output's thermal limit "may not" be truly independent to
the extent that if one output is shorted, it may impact the operation of other outputs (due to
lateral heating in the die).
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L9733
Fault operation
7
Fault operation
The fault diagnostic capability consists of one internal 16 bits shift register and 2 bits are
used for each output. The diagnostic information are: no fault present, overcurrent, open
load and short circuit.
All of the faults will be cleared on the rising edge of chip select if a valid DI byte was received
Table 11. Fault register definition
OUT 8 OUT 7 OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
LSB
MSB
D1
D0
D1
D0
D1
D0
D1
b9
D0
b8
D1
b7
D0
b6
D1
b5
D0
b4
D1
b3
D0
b2
D1
b1
D0
b0
b15
b14
b13 b12 b11 b10
Table 12. Fault logic definition
D1
D0
Fault status
0
0
1
1
0
1
0
1
No fault is present
Open load
Short circuit to GND (low-side) or short circuit to Vbat (high-side)
Overcurrent
If all the bits b0-b15 of the fault register have value '1' it means that a thermal fault, at least
on one of the eight independent Outputs, occurred.
7.1
Low-side configured output fault operation
The diagnostic circuitry verifies for the low-side configured output the following condition:
Normal operation, open load, short circuit to GND and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to GND, this means that if an overcurrent occurs the fault register is always
overwritten and following open load or short to GND faults that happen before that the
register is cleared will be ignored.
7.1.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to GND faults.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
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Fault operation
L9733
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the
described range when no load is connected.
2. Short circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is lower than the Vth_GND threshold.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occurred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the falling edge
of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault
signals during Drn6-8 transient after falling edge of IN6-8.
7.1.2
Latch mode
This diagnostic operating mode latches all faults when they happen.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2. Short circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected if the power drain voltage is lower than the
Vth_GND threshold for the filtering time Tfilt.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register. If the switching OFF protection is not active the On
26/34
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L9733
Fault operation
phase overcurrent protection is a linear current limitation and no diagnosis is available.
There are three possibilities to restart one output after the fault has occurred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the power MOS transient, after a switching-off command, is longer than Tdel
filtering time, a bad diagnostic behavior happens and software filtering may be
needed.
7.2
High-side configured output fault operation
The diagnostic circuitry verifies for the high-side configured output the following condition:
Normal operation, open load, short circuit to Vbat and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to Vb, this means that if an overcurrent occurs the fault register is always overwritten
and following open load or short to Vbat faults that happen before that the register is cleared
will be ignored.
7.2.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to Vbat faults.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the
described range when no load is connected.
2. Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is higher than the Vth_Vbat threshold.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occurred:
Doc ID 11319 Rev 9
27/34
Fault operation
L9733
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the
falling edge of IN6-8 during the power MOS transient. Software filtering may be
needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.
7.2.2
Latch mode
This diagnostic operating mode latches all faults when they happen.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2. Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected if the power drain voltage is higher than the
Vth_Vbat threshold for the filtering time Tfilt.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occurred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
If the power MOS transient, after a switching-off command, is longer than Tdel filtering time,
a bad diagnostic behavior happens and software filtering may be needed.
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L9733
Fault operation
Figure 7.
L9733 application schematic
VDD
8 HIGH/LOW SIDE DRIVER
VBAT
RES
SCLK
DI
DRN[x]
DO
High Side Driver
Configuration
CS
SRC[x]
DRN[x]
SRC[x]
VDO
IN6
IN7
IN8
Low Side Driver
Configuration
To driver 6
To driver 7
To driver 8
GND
Figure 8.
L9733 HVAC applicative examples
Vbatt
M
Vbatt
SM
SM
SM
SM
M
M
L9733
973
Stall sense
4 channels configured to low- and 4 channels
configured to high side build a quad half bridge.
Four flap motors become sequentially driven. Unipolar stepper motor are
selected by 4 high-side configured switches. If the decoupling diodes are inside
the motor housing, only 8 wires are needed to drive this arrangement.
This can drive 3 DC-motors sequantially.
Doc ID 11319 Rev 9
29/34
Fault operation
L9733
Figure 9.
L9733 powertrain applicative examples
Vbatt
Vbatt
Tach-Out
(PWM)
Starter Relay
Key-On Relay
A/C Fan Relay
Power Latch Relay
A/C Compressor Relay
Air Pump Relay
Canister Purge Relay
(opt PWM)
MIL Lamp
Water Lamp
SM
Idle Speed Control
Fuel Pump Relay
(opt PWM)
L9733
L9733
Coolant Fan Relay
Main Relays and Lamps Driving
Idle speed stepper motor driving and auxiliary loads
30/34
Doc ID 11319 Rev 9
L9733
Application circuit
8
Application circuit
Figure 10. Optimized circuit layout to achieve proper EMI/ESD capability
Voltage
Reg.
Reverse polarity & neg. ISO -pulse protection
Battery
R1= 10...22 (EMI improvement)
47…100nF
Ceramic
Positive ISO - pulse
protection
VBAT
C1
47…100nF Ceramic
VDD 5V
DRNX
VDD
RES
SCLK
DI
All output C = 47nF ceramic
SPI
VDD on/off for low
quiescent current
DO
CS
VDO
Capacitor impedance
IN 6
IN 7
IN 8
Frequency
GND
VBAT supplies the floating charge pump. Filtering
capacitor C1 is important to achieve a proper EMI
performance. Impedance minimum should fit to
the critical frequency range. A series resistor to
VBAT can improve furthermore EMI performance.
Central ground plane (blue coloured)
Module
Connector
Doc ID 11319 Rev 9
31/34
Package information
L9733
9
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 11. PowerSSO28 mechanical data and package dimensions
mm
inch
DIM.
MIN.
2.15
2.15
0
0.18
0.23
10.10
TYP. MAX. MIN.
2.45 0.084
2.35 0.084
TYP. MAX.
0.0965
0.0925
0.004
OUTLINE AND
MECHANICAL DATA
A
A2
a1
b
0.10
0
0.36 0.007
0.32 0.009
10.50 0.398
0.014
0.012
0.413
c
(1)
D
(1)
E
7.4
7.6
0.291
0.299
e
e3
F
G
G1
H
h
0.65
8.45
2.3
0.025
0.033
0.090
0.004
0.002
0.413
0.016
0.10
0.06
10.50 0.398
0.40
5˚ ( typ)
1.0
10.10
0.60
k
L
0.023
0.039
0.169
M
N
O
Q
S
T
U
X
4.3
10˚ (max)
1.2
0.8
2.9
3.65
1.0
0.047
0.031
0.114
0.144
0.039
0.189
0.283
4.2
6.6
4.8
7.2
0.165
0.259
PowerSSO-28
(Exposed pad)
Y
(1) "D” and “E" do not include mold flash or protrusions Mold flash
or protrusions shall not exceed 0.15 mm per side(0.006”)
7633868 C
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Doc ID 11319 Rev 9
L9733
Revision history
10
Revision history
Table 13. Document revision history
Date
Revision
Changes
13-Apr-2005
15-Jun-2006
08-Aug-2006
28-May-2007
1
2
3
4
Initial release.
Changed only look and feel.
Modified Table 9: Bit command register definition on page 22.
Changed the min. value of the CSlead parameter on the Table 8.
Updated Table 6 and Table 7. Added new Figure 4.
17-Jul-2007
03-Aug-2007
5
6
Changed the status from Preliminary data to Datasheet.
Updated in Table 4 the ESD parameter.
Added order codes in Table 1: Device summary.
Added “CS2SCLK” parameter in Table 8: SPI characteristics and
timings.
12-Jun-2008
7
Updated Figure 6: SPI timing diagram.
Updated Table 1: Device summary on page 1.
Removed all references to the SO-28 package.
Updated Section 2.1: Operating range and Section 2.2: Absolute
maximum ratings.
02-Dec-2008
13-May-2009
8
9
Added Section 2.1.1: Functional operative range, Section 2.1.2:
Jump start conditions, Section 2.1.3: Operation at low battery
condition and Section 2.1.4: Operation at load dump condition.
Added Section 8: Application circuit.
Added “PORth” parameter in Table 6: DC characteristics.
Updated Table 1: Device summary on page 1.
Updated Figure 11: PowerSSO28 mechanical data and package
dimensions.
Doc ID 11319 Rev 9
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L9733
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