L9826_技术文档

L9826

Octal Low-Side Driver for resistive and inductive loads with

serial/parallel input control, output protection and diagnostic

■

OUTPUTS CURRENT CAPABILITY UP TO

=

Ω

2.2 AT T = 25°C

J

500mA, R

ON

PARALLEL CONTROL INPUTS FOR

OUTPUTS 1 AND 2

■

SPI CONTROL FOR OUTPUTS 1 TO 8

RESET FUNCTION WITH RESET SIGNAL AT

NRES PIN OR UNDERVOLTAGE AT V

CC

SO20 (16+2+2)

ORDERING NUMBER: L9826

■

- INTRINSIC OUTPUT VOLTAGE CLAMPING

AT TYP. 50V

OVERCURRENT SHUTDOWN AT OUTPUTS

3 TO 8

DESCRIPTION

SHORT CIRCUIT CURRENT LIMITATION

AND SELECTIVE THERMAL SHUTDOWN AT

OUTPUTS 1 AND 2

The L9826 is a Octal Low-Side Driver Circuit, dedicated

for automotive applications. Output voltage clamping is

provided for flyback current recirculation, when induc-

tive loads are driven. Chip Select and Serial Peripheral

Interface for outputs control and diagnostic data trans-

fer. Parallel Control inputs for two outputs.

■

OUTPUT STATUS DATA AVAILABLE ON THE SPI

BLOCK DIAGRAM

V

CC

V

CC

OUT1

NON1

1

2

3

I

OL

S

Latch / Driver

Q1

R

Overtemperature Detection

+

-

Diag1

Fault Latch

V

DG

CH1

NON2

NCS

OUT2

OUT3

V

CC

Q2

CH2

Diag2

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

S

Q3

I

OL

Latch / Driver

V

CC

R

CLK

SDI

+

-

Diag3

Diag1

Diag2

Diag3

Diag4

Diag5

Diag6

Diag7

Diag8

V

DG

V

CH3

CH4

OUT4

Q4

Diag4

OUT5

OUT6

Q5

Diag5

CH5

V

CC

SDO

Q6

Diag6

V

CC

CH6

CH7

nRES

OUT7

OUT8

Q7

Diag7

Reset

V

CC

Undervoltage

RESET

Q8

Diag8

CH8

GND

October 2002

1/12

L9826

PIN FUNCTION

N°

1

Description

Out 6

Out 1

nRes

NCS

GND

output 6

2

output 1

3

asynchronous nRes

chip select (active low)

device ground

4

5

6

7

NON1 control input 1

8

SDO

Out 8

Out 3

Out 5

Out 2

SDI

serial data output

output 8

9

10

11

12

13

14

15

16

17

18

19

20

output 3

output 5

output 2

serial data input

serial clock

device ground

CLK

GND

NON2 control input 2

V

supply voltage

output 7

CC

Out 7

Out 4

output 4

PIN CONNECTIONS (Top view)

OUT6

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OUT4

OUT7

Vcc

OUT1

nRES

NCS

NON2

GND

CLK

GND

NON1

SDO

SDI

OUT8

OUT3

OUT2

OUT5

PINCON_L9826

2/12

L9826

ABSOLUTE MAXIMUM RATINGS

For voltages and currents applied externally to the device

Symbol

Parameter

Supply voltage

Test Condition

Min.

Typ.

Max.

Unit

V

-0.3

7

V

CC

Inputs and data lines

(NONx, NCS, CLK, SDI, nRes)

V

Voltage

-0.3

-20

7

V

IN

(NONx, NCS, CLK, SDI, nRes)

1)

I

IN

T ≤ 1ms

20

mA

Protection diodes current

Outputs (Out1 ... Out8)

V

Continuous output voltage

-1,0

-2

45

V

A

OUTc

OUT

2)

I

1,0

Output current

E

OUTcl

Output clamp energy

I

≤ 250mA

OUT

10

mJ

Notes: 1. All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV. It corresponds to a dissipated energy E £

0,2mJ.

2. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.

For currents determined within the device:

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Outputs (Out1 ... Out8)

I

Output current (Out1 ... Out8)

1,0

A

OUT

Total average-current all outputs

3)

2.0

I

∑

OUTi

i = 1-8

3. When operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may

occur.

THERMAL DATA

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Thermal shutdown

T

Thermal shutdown threshold

150

165

°C

JSC

Thermal resistance

R

Single output (junction ambient)

All outputs (junction ambient)

Junction to Pin

90

75

18

°C/W

thjA-one

R

thjA-all

R

thj-pin

3/12

L9826

ELECTRICAL CHARACTERISTCS (4.5V

≤

V

CC

≤

5,5V; -40°C

≤ ≤

T 150°C; unless otherwise specified)

J

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply voltage

I

Standby current

Operating mode

without load (nRes = Low)

= 500mA

70

5

µA

ccSTB

I

mA

ccOPM

OUT1 ... 8

SPI - CLK = 3MHz

NCS = LOW

SDO no load

∆I

during reverse output

I = -2A

out

100

mA

CC

current

Inputs (NONx. NCS, CLK, SDI, nRes)

V

Low level

-0.3

0.2·V

V

INL

INH

hyst

CC

V

High level

0.7·V

V +0,3

CC

Hysteresis voltage

Input current

0.85

-10

50

V

I

V

= V

CC

10

µA

kΩ

IN

R

Pullup resistance

250

IN

(NONx, NCS, CLK, SDI)

Pulldown resistance (nRes)

C

Input capacitance

10

pF

IN

Serial data outputs

V

High output level

I

= -4mA

V -0.4

CC

V

SDOH

SDO

V

Low output level

= 3,2mA

0.4

10

SDOL

I

Tristate leakage current

Output capacitance

NCS = high; 0V

f = 300kHz

SDO

≤

V

SDO

≤

V

CC

-10

µA

pF

SDOL

C

SDO

Outputs OUT 1 ... 8

I

Leakage current

Output clamp voltage

OUTx = OFF; V

= 25V;

100

10

µA

V

OUTL1 - 8

OUTx

V

CC

= 5V

OUTx = OFF; V

= 5V

= 16V;

V

CC

OUTx = OFF; V

= 1V

= 16V;

V

CC

V

clp

1mA

≤

I

≤ I ; I = 10mA with

outp test

45

62

clp

correlation

R

On resistance OUT 1 ... 8

Output capacitance

I

= 500mA; T = +150°C

3.0

Ω

DSon

OUT

j

C

V

= 16V; f = 1MHz

300

pF

OUT

4/12

L9826

ELECTRICAL CHARACTERISTCS (continued)

Symbol Parameter

Test Condition

Min.

Typ.

Max.

Unit

Outputs short circuit protection

I

Overcurrent shutoff threshold

Short circuit current limitation

Delay shutdown

OUT3 ... OUT8

0.45

0.5

1.1

1,0

12

A

SBC

I

OUT1; OUT2

LIM

t

for output 3 ... 8; I

≤ 1/2 I

SCB

0.2

3,0

µs

SCB

OUT

Diagnostics

V

Diagnostic threshold voltage

0.32·V

CC

0.4·V

V

DG

C

I

Open load detection sink

current

V

out

= V

20

15

100

50

µA

µs

OL

DG

t

Diagnostic detection filter time

for output 1 & 2 on each

diagnostic condition

df

Outputs timing

t

Turn ON delay of OUT 1 and 2

NON

= 50% to V

= 0,9·V

5

µs

don1

1, 2

OUT

bat

NCS = 50% to V

= 0,9·V

OUT

bat

t

Turn ON delay of OUT 3 to 8

Turn OFF delay of OUT 1 to 8

= 0,9·V

10

µs

don2

OUT

t

dU

= 0,1·V

doff

OUT

NON

= 50% to V

= 0,1·V

1, 2

OUT

Turn ON voltage slew-rate

Turn OFF voltage slew-rate

For output 3 to 8; 90% to 30% of

; R = 500Ω; V = 16V

0.7

2

3.5

10

15

V/µs

on1/dt

on2/dt

off1/dt

off2/dt

V

bat

L

bat

For output 1 and 2; 90% to 30% of

; R = 500Ω; V = 16V

V

bat

L

bat

For output 1 to 8; 30% to 90% of

; R = 500Ω; V = 16V

2

V

bat

L

bat

For output 1 to 8; 30% to 80% of

; R = 500Ω; V = 0.9 · V

clp

2

V

bat

L

bat

Serial diagnostic link (Load capacitor at SDO = 100pF)

f

Clock frequency

50% duty cycle

3

MHz

ns

clk

t

Minimum time CLK = HIGH

Minimum time CLK = LOW

160

clh

t

ns

cll

t

Propagation delay

CLK to data at SDO valid

4,9V ≤ V ≤ 5,1V

100

ns

pcld

CC

t

NCS = LOW to data at SDO

active

ns

csdv

t

CLK low before NCS low

Setup time CLK to NCS change H/L

100

sclch

5/12

L9826

ELECTRICAL CHARACTERISTCS (continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

t

CLK change L/H after NCS =

low

100

ns

hclcl

t

SDI input setup time

CLK change H/L after SDI data

valid

20

ns

scld

t

SDI input hold time

SDI data hold after CLK change H/L

20

ns

hcld

sclcl

t

CLK low before NCS high

CLK high after NCS high

NCS L/H to output data float

NCS pulse filter time

150

t

hclch

t

100

pchdz

Multiple of 8 CLK cycles inside

NCS period

FUNCTIONAL DESCRIPTION

General

The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using

the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power

outputs features voltage clamping function for flyback current recirculation and are protected against short cir-

cuit to Vbat.

The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and ther-

mal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to GND in switch-off condition

for all outputs. The outputs status can be read out via the serial interface.

The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes

signal.

Output Stages Control

Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1

and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These

inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open.

The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1.

The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every

falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.

6/12

L9826

Figure 1. Timing of the Serial Interface.

NCS

tsclch

tcsdv

thclcl

tclh

tcll

tsclcl

thclch

CLK

tpcld

not defined

tscld

tpchdz

D1

D8

SDO

thcld

D8

D7

D1

SDI

The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and

the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since

the last NCS falling edge. The NCS changes only at low CLK.

Outputs Control Tables :

Outputs 1, 2:

NON1, 2

Outputs 3 to 8:

1

0

1

SPI-bit 1, 2

Output 1, 2

SPI-bit 3 ... 8

Output 3 ... 8

0

1

off

on

off

on

Figure 2. Output Control register structure

MSB

LSB

Q2 Q4 Q6 Q8 Q1 Q3 Q5 Q7

Control-bit output 7

Control-bit output 5

Control-bit output 3

Control-bit output 1

Control-bit output 8

Control-bit output 6

Control-bit output 4

Control-bit output 2

7/12

L9826

Power outputs characteristics

for flyback current, outputs short circuit protection and diagnostics

For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V.

This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is

absorbed in the chip.

Output short circuit protection for outputs 3 to 8 (dedicated for loads without inrush current): when the output

current exceeds the short circuit threshold, the corresponding output overload latch is set and the output is

switched off immediately.

Output short circuit protection for outputs 1 and 2 (dedicated for loads with inrush current, as lamps): when the

load current would exceed the short circuit limit value, the corresponding output goes in a current regulation

mode. The output current is determined by the output characteristics and the output voltage depends on the

load resistance. In this mode high power is dissipated in the output transistor and its temperature increases rap-

idly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set

and the corresponding output switched off.

For the load diagnostic in output off condition each output features a diagnostic current sink, typ 60µA.

Diagnostics

The output voltage at all outputs is compared with the diagnostic threshold, typ 0,38 · V

.

CC

Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and latched. The fault latch-

es are cleared during NCS low. The latch stores the status bit, so the first reading after the error occurred might

be wrong. The second reading is right.

Diagnostic Table for outputs 1 and 2 in parallel controlled mode:

Output 1, 2

Output-voltage

> DG-threshold

< DG-threshold

> DG-threshold

Status-bit

high

Output-mode

off

on

correct operation

fault condition 2)

correct operation

fault condition 1)

low

high

low

Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output ex-

ceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due

to thermal shutdown. The status bit is low.

Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the

output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur-

rent source, the load is interrupted. The diagnostic bit is low.

For outputs 3 to 8 the output status signals, are fed directly to the SPI register.

Diagnostic Table for outputs 1 to 8 in SPI controlled mode:

Output 1 ... 8

Output-voltage

> DG-threshold

< DG-threshold

> DG-threshold

Status-bit

high

Output-mode

off

on

correct operation

fault condition 2)

correct operation

fault condition 1)

low

high

8/12

L9826

The fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output

exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has

been switched off. The diagnostic bit is high.

Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and 2.

At the falling edge of NCS the output status data are transferred to the shift register. When NSC is low, data bits

contained in the shift register are transferred to SDO output et every rising CLK edge.

Figure 3. The Pulse Diagram to Read the Outputs Status Register

NCS

CLK

MSB

6

5

4

3

2

1

LSB

SDO

SDI

MSB

6

5

4

3

2

1

Figure 4. The Structure of the Outputs Status Register

MSB

LSB

Diag2Diag4Diag6Diag8Diag1Diag3Diag5Diag7

Diagnostic-bit output 7

Diagnostic-bit output 5

Diagnostic-bit output 3

Diagnostic-bit output 1

Diagnostic-bit output 8

Diagnostic-bit output 6

Diagnostic-bit output 4

Diagnostic-bit output 2

9/12

L9826

APPLICATION INFORMATION

The typical application diagram is shown in Fig. 5.

Figure 5. Typical Application Circuit Diagram for the L9826 Circuit.

V

CC

BAT

VOLTAGE

REGULATOR

V

CC

V

OUT1

CC

NON1

1

3

I

OL

S

2

Latch / Driver

Q1

R

Overtemperature Detection

+

Diag1

Fault Latch

V

-

DG

CH

1

NON2

V

OUT2

OUT3

CH2

CC

Q2

Diag2

NCS

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

S

Q3

I

OL

Latch / Driver

V

CC

R

CLK

SDI

+

-

Diag

3

Diag

1

2

V

CH3

DG

3

Diag4

Q4

OUT4

C

H

4

Diag

5

6

7

Diag

4

Q5

OUT5

OUT6

OUT7

OUT8

Diag8

C

5

6

H

Diag

5

V

CC

SDO

Q6

V

H

CC

Diag

6

nRES

Q7

Diag7

Reset

CH7

Reset

V

µP

Undervoltage

RESET

Q8

Diag8

C

8

H

L9826

R, L loads

GND

For higher current driving capability two outputs of the same kind can be paralleled. In this case the maximum

flyback energy should not exceed the limit value for single output.

The immunity of the circuit with respect to the transients at the output is verified during the characterization for

Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with

200pF series capacitor. All outputs withstand testpulses without damage.

The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characteriza-

Ω

tion for the typical application with R = 30 to 100 , L= 0 to 600mH loads. The Test Pulses are coupled to the

outputs with 200pF series capacitor.

10/12

L9826

mm

inch

OUTLINE AND

MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A

A1

B

C

D

E

e

2.35

0.1

2.65 0.093

0.3 0.004

0.104

0.012

0.020

0.013

0.512

0.299

0.33

0.23

12.6

7.4

0.51 0.013

0.32 0.009

13

0.496

0.291

7.6

1.27

0.050

H

h

10

0.25

0.4

10.65 0.394

0.75 0.010

0.419

0.030

0.050

L

1.27 0.016

SO20

K

0˚ (min.)8˚ (max.)

L

h x 45˚

A

B

A1

K

C

e

H

D

20

11

E

1

01

SO20MEC

11/12

L9826

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

http://www.st.com

12/12


型号：	L9826
厂家：	ST
描述：	Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic 为阻性和感性负载与串行/并行输入控制，输出保护和诊断八路低端驱动器外围驱动器驱动程序和接口接口集成电路光电二极管
文件：	总12页 (文件大小：177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9826 [STMICROELECTRONICS]

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