LD3986J3133R-E [STMICROELECTRONICS]
DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS; 双超低压降低噪声BICMOS电压REG 。适用于非常低的ESR OUT 。电容器
| 型号： | LD3986J3133R-E |
| 厂家： | 
ST |
| 描述： | DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS |
| 文件： | 总12页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LD3986
SERIES
DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE
REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS
■
■
INPUT VOLTAGE FROM 2.5V TO 6V
STABLE WITH LOW ESR CERAMIC
CAPACITORS
■
■
■
ULTRA LOW DROPOUT VOLTAGE (60mV
TYP. AT 150mA LOAD, 0.4mV TYP. AT 1mA
LOAD)
VERY LOW QUIESCENT CURRENT (155µA
TYP. AT NO LOAD, 290µA TYP. AT 150mA
LOAD; MAX 2µA IN OFF MODE)
Flip-Chip
GUARANTEED OUTPUT CURRENT UP TO
150mA FOR BOTH OUTPUTS
■
■
DUAL OUTPUT VOLTAGES
FAST TURN-ON TIME: TYP. 120µs (C =1µF,
make it suitable for low power applications and in
battery powered systems. Regulator ground
current increases only slightly in dropout, further
prolonging the battery life. Power supply rejection
is 50 dB at 1KHz and 40 dB at 10KHz. High power
supply rejection is maintained down to low input
voltage levels common to battery operated
circuits. Shutdown Logic Control function is
available for each output, this means that when
the device is used as local regulator, it is possible
to put a part of the board in standby, decreasing
the total power consumption. The LD3986 is
designed to work with low ESR ceramic
capacitors. Typical applications are in mobile
phone and similar battery powered wireless
systems.
O
C
=10nF AND I =1mA)
BYP
O
■
LOGIC-CONTROLLED ELECTRONIC
SHUTDOWN
INTERNAL CURRENT AND THERMAL LIMIT
OUTPUT LOW NOISE VOLTAGE 30µV
OVER 10Hz to 100KHz
S.V.R. OF 50dB AT 1KHz, 40dB AT 10KHz
TEMPERATURE RANGE: -40°C TO 125°C
■
■
RMS
■
■
DESCRIPTION
The LD3986 provides up to 150mA at each output,
from 2.5V to 6V input voltage. The ultra low
drop-voltage, low quiescent current and low noise
Figure 1: Schematic Diagram
Rev. 3
1/12
September 2005
LD3986 SERIES
Table 1: Order Codes
Flip-Chip
Flip-Chip (Lead Free)
1 OUTPUT VOLTAGES
2 OUTPUT VOLTAGES
LD3986J122R-E
LD3986J12248R-E
LD3986J1828R-E
LD3986J2528R-E (*)
LD3986J28R-E
1.22 V
1.22 V
1.8 V
2.5 V
2.8 V
2.85 V
2.9 V
3.0 V
2.8 V
3.1 V
3.3 V
1.22 V
4.8 V
2.8 V
2.8 V
2.8 V
2.85 V
2.9 V
3.0 V
3.0 V
3.3 V
3.3 V
LD3986J12248R
LD3986J285R
LD3986J285R-E
LD3986J29R-E (*)
LD3986J30R-E (*)
LD3986J2830R-E (*)
LD3986J3133R-E (*)
LD3986J33R-E
(*) Available on Request.
Table 2: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
DC Input Voltage
-0.3 to 6
V
V
V
I
V
DC Output Voltage
-0.3 to V +0.3
O1,2
I
V
ENABLE Input Voltage
Output Current
-0.3 to V +0.3
EN1,2
I
I
Internally limited
Internally limited
-65 to 150
O
P
Power Dissipation
D
T
Storage Temperature Range
Operating Junction Temperature Range
°C
°C
STG
T
-40 to 125
OP
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Table 3: Thermal Data
Symbol
Parameter
Flip-Chip
Unit
R
Thermal Resistance Junction-Ambient
120
°C/W
thj-amb
2/12
LD3986 SERIES
Figure 2: Pin Connection (top through view)
Table 4: Pin Description
Symbol
Pin N°
A1
Name and Function
V
Output Voltage 2 of the dual LDO
O2
EN2
B1
Enables voltage for output voltage 2: ON MODE when V ≥ 1.4V, OFF MODE when V
≤
≤
EN
EN
0.4V (Do not leave floating, not internally pulled down/up)
Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise voltage
Common Ground
BYPASS
GND
C1
C2
C3
B3
GND
Common Ground
EN1
Enables voltage for output voltage 1: ON MODE when V ≥ 1.4V, OFF MODE when V
EN
EN
0.4V (Do not leave floating, not internally pulled down/up)
Output Voltage 1 of the dual LDO
V
A3
A2
O1
V
Input Voltage for both LDO
I
Figure 3: Typical Application Circuit
3/12
LD3986 SERIES
Table 5: Electrical Characteristics For LD3986 (T = 25°C, V = V
+0.5V, C = C =1µF,
j
I
O(NOM)
I
O
C
= 10nF, I = 1mA, V = 1.4V, unless otherwise specified)
O EN
BYP
Symbol
Parameter
Test Conditions
Min.
2.5
-2.5
-3
Typ.
Max.
Unit
V
V
Operating Input Voltage
Output Voltage Tolerance
6
2.5
3
I
∆V
∆V
∆V
∆V
I
= 1mA
% of V
O
O
O
O
O
O
T = -40 to 125°C
J
Line Regulation (Note 1)
Load Regulation
V = V
+ 0.5 V to 6V
0.006 0.092
0.128
%/V
I
O(NOM)
T = -40 to 125°C
J
I
= 1 mA to 150mA
0.003 0.006
0.01
%/mA
O
T = -40 to 125°C
J
Output AC Line Regulation V = V
+ 1 V, I = 150mA,
1.5
mV
PP
I
O(NOM)
O
(See fig. 5)
t = t = 30µs
R
O
O
O
O
F
I
Quiescent Current
BOTH ON MODE:
I
I
I
I
= 0
150
200
290
370
µA
Q
= 0
T = -40 to 125°C
J
V
= 1.4V
EN
= 0 to 150mA
= 0 to 150mA
T = -40 to 125°C
J
BOTH OFF MODE:
= 0.4V
0.001
2
4
V
EN
T = -40 to 125°C
J
ONE REGULATOR
I
I
I
I
I
I
I
I
= 0
95
O
O
O
O
O
O
O
O
ON MODE: V = 1.4V
EN
= 0
T = -40 to 125°C
130
220
2
J
= 0 to 150mA
= 0 to 150mA
= 1mA
165
0.4
50
T = -40 to 125°C
J
V
Dropout Voltage (Note 2)
mV
dB
DROP
= 1mA
T = -40 to 125°C
J
= 150mA
= 150mA
T = -40 to 125°C
100
J
SVR Supply Voltage Rejection
(See fig. 4)
V = V
+0.25V ±
= 0.1V, I = 50mA
O
f = 1KHz
50
40
I
O(NOM)
V
f = 10KHz
RIPPLE
V
< 2.5V,
V = 2.55V
I
O(NOM)
I
Short Circuit Current
Peak Output Current
R = 0
600
550
mA
mA
V
SC
L
I
V
≥ V - 5%
O(NOM)
300
1.4
O(PK)
O
V
Enable Input Logic Low
(Note 3)
V = 2.5V to 6V
T = -40 to 125°C
0.4
EN
I
J
Enable Input Logic High
(Note 3)
I
Enable Input Current
Crosstalk Rejection
V
= 0.4V
V = 6V
±10
40
nA
µV
EN
EN
I
X
∆I
= 150 mA at 1KHz rate
TALK
LOAD1
I
= 1 mA, V under test
O2
LOAD2
∆I
= 150 mA at 1KHz rate
40
LOAD2
I
= 1 mA, V under test
LOAD1
O1
eN
Output Noise Voltage
Turn On Time (Note 4)
B
= 10 Hz to 100 KHz
C
= 1 µF
30
50
µV
RMS
W
O
t
C
= 10 nF
BYP
µs
ON
T
Thermal Shutdown (Note
4)
(Note 3)
160
°C
SHDN
4/12
LD3986 SERIES
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
C
Output Capacitor
Capacitance
ESR
1
22
5
µF
O
0.005
Ω
Note 1: For V < 2V, V =2.5V
O
I
Note 2: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specifi-
cation does not apply for input voltages below 2.5V.
Note 3: Enable pin must be driven with a T = T < 10ms
Note 4: Turn-on time is time measured between the enable input just exceeding V
of its nominal value
R
F
High Value and the output voltage just reaching 95%
INH
Note 5: Typical thermal protection hysteresis is 20°C
Figure 4: SVR Input Voltage Test Signal
Figure 5: AC Line Regulation Input Voltage Test Signal
5/12
LD3986 SERIES
TYPICAL PERFORMANCE CHARACTERISTICS (T = 25°C, V = V
+0.5V, C = C = 1µF,
I O
j
I
O(NOM)
C
= 10nF, I = 1mA, V = 1.4V, unless otherwise specified)
O EN
BYP
Figure 6: V
vs Temperature
Figure 9: Load Regulation vs Temperature
O1,2
Figure 7: V
vs Temperature
Figure 10: Quiescent Current vs Temperature
O1,2
Figure 8: Line Regulation vs Temperature
Figure 11: Quiescent Current vs Temperature
6/12
LD3986 SERIES
Figure 12: Supply Voltage Rejection vs
Figure 15: Load Transient Response
Frequency
I
= 1 mA, I = 0mA, T = T = 10µs
O1
O2
R
F
Figure 13: Supply Voltage Rejection vs
Figure 16: TURN-ON
Temperature
V = 3.2V, V
= 0 to 1.4V, I
= 1mA, T = T = 1µs
O1,2 R F
I
EN1,2
Figure 14: Line Transient Response
Figure 17: TURN-OFF
V = 3.2V to 3.8V, I = I = 150mA, T = T = 10µs
V = 3.2V, V
= 1.4 to 0V, I
= 1mA, T = T = 1µs
O1,2 R F
I
O1
O2
R
F
I
EN1,2
7/12
LD3986 SERIES
APPLICATION INFORMATION
CURRENT LIMIT
The device includes short-circuit protection. It
includes a current limiter that controls the pass
transistor’s gate voltage to limit the output current
to about 600mA.
Important: Tantalum capacitors can suffer
catastrophic failures due to surge current when
connected to a low impedance source of power
(like a battery or a very large capacitor). If a
tantalum capacitor is used at the input, it must be
guaranteed by the manufacturer to have a surge
current rating sufficient for the application.
There are no requirements for the ESR on the
input capacitor, but tolerance and temperature
coefficient must be considered when selecting the
capacitor to ensure
THERMAL OVERLOAD PROTECTION
The Thermal over load protection limits total
power dissipation in the device. When the junction
the capacitance will be ≈ 1µF over the entire
operating temperature range.
temperature (T ) exceeds +160°C, the thermal
J
sensor sends a signal to the shutdown logic,
turning off the pass transistors and allowing the
device to cool. The pass transistors turns on again
after the device’s junction temperature typically
cools by 20°C, resulting in a pulsed output during
continuous thermal overload conditions.
OUTPUT CAPACITOR
The LD3986 is designed specifically to work with
very small ceramic output capacitors, any ceramic
capacitor (temperature characteristics X7R, X5R,
Z5U or Y5V) in 1 to 22 µF range with 5m. to 500m.
ESR range is suitable in the LD3986 application
circuit. it may also be possible to use tantalum or
film capacitors at the output, but these are not as
attractive for reasons of size and cost.
The output capacitor must meet the requirement
for minimum amount of capacitance and also have
an ESR (Equivalent Series Resistance) value
which is within a stable range.
POWER DISSIPATION
Maximum power dissipation of the device
depends on the thermal resistance of the case
and circuit board, the temperature difference
between the die junction and ambient air, and the
rate of air flow. The power dissipated by the
device is:
NOISE BYPASS CAPACITOR
P = I (V -V )
D
O
I
O
Connecting a 0.01µF capacitor between the C
BYP
pin and ground significantly reduces noise on both
regulator outputs.
The maximum power dissipation is:
= (T - T ) / R
This cap is connected directly to a high impedance
node in the band gap reference circuit. Any
significant loading on this node will cause a
change on the regulated output voltage.
For this reason, DC leakage current through this
pin must be kept as low as possible for best output
voltage accuracy. The use of this 0.01µF bypass
capacitor is strongly recommended to prevent
overshoot on the output during start up.
The types of capacitors best suited for the noise
bypass capacitor are ceramic and film.
High-quality ceramic capacitors with either NPO
or COG dielectric typically have very low leakage.
Polypropylene and polycarbonate film capacitors
are available in small surface-mount packages
and typically have extremely low leakage current.
Unlike many other LDO’s, addition of a noise
reduction capacitor does not effect the transient
response of the device.
P
MAX
JMAX
A
TH
Where:
= +125°C
T
JMAX
T is the ambient temperature
A
R
thermal resistance.
TH
The device’s pins perform the dual function of
providing an electrical connection as well as
channeling heat away from the die. Use wide
circuit-board traces and large, solid copper
polygons to improve power dissipation. Using
multiple vias to buried ground planes further
enhances thermal conductivity.
INPUT CAPACITOR
An input capacitance of ≈ 1µF is required between
the LD3986 input pin and ground (the amount of
the capacitance may be increased without limit).
This capacitor must be located a distance of not
more than 1cm from the input pin and returned to
a clean analog ground. Any good quality ceramic,
tantalum, or film capacitor may be used at the
input.
TURN-ON/OFF INPUT OPERATION
Each LD3986 output is turned off by pulling the
relevant EN pin low, and turned on by pulling it
high. To assure proper operation, the signal
8/12
LD3986 SERIES
source used to drive the EN input must be able to
swing above and below the specified turn-on/off
voltage thresholds listed in the Electrical
Characteristics section under Enable Input Logic
Low and Enable Input Logic High.
internal 70µA current source. The current source
is turned off when the bandgap voltage reaches
approximately 95% of its final value. The turn on
time is determined by the time constant of the
bypass capacitor. The smaller the capacitor value,
the shorter the turn on time, but less noise gets
reduced. As a result, turn on time and noise
reduction need to be taken into design
consideration when choosing the value of the
bypass capacitor.
Proper operation of the Enable function is
guaranteed by driving EN pins with T and T = 10
R
F
ms.
FAST ON-TIME
The LD3986 outputs are turned on after V
REF
voltage reaches its final value (1.23V nominal). To
speed up this process, the noise reduction
capacitor at the bypass pin is charged with an
9/12
LD3986 SERIES
Flip-Chip8 MECHANICAL DATA
mm.
mils
TYP.
25.6
9.8
DIM.
MIN.
0.585
0.21
TYP
0.65
0.25
0.40
0.315
1.57
1
MAX.
0.715
0.29
MIN.
23.0
8.3
MAX.
28.1
11.4
A
A1
A2
b
15.7
12.4
61.8
39.4
61.8
39.4
19.7
11.2
3.1
0.265
1.52
0.365
1.62
10.4
59.8
14.4
63.8
D
D1
E
1.52
0.45
1.57
1
1.62
0.55
59.8
17.7
63.8
20.7
E1
e
0.5
f
0.285
0.080
ccc
7224720E
10/12
LD3986 SERIES
Table 6: Revision History
Date
Revision
Description of Changes
07-Dec-2004
06-Jun-2005
22-Sep-2005
1
2
3
First Release.
Add New Part Number - Table 1.
Order Codes has been updated.
11/12
LD3986 SERIES
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2005 STMicroelectronics - All Rights Reserved
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12/12
相关型号：
LD3986J33R-E
DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS
STMICROELECTR
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