LD57100 [STMICROELECTRONICS]
1 A ultra low-dropout LDO with bias;
| 型号： | LD57100 |
| 厂家： | 
ST |
| 描述： | 1 A ultra low-dropout LDO with bias |
| 文件： | 总21页 (文件大小：1369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LD57100
Datasheet
1 A ultra low-dropout LDO with bias
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input voltage from VOUT to 5.5 V
Input bias supply pin from 3.0 V to 5.5 V
Ultra low-dropout voltage (40 mV typ. at 1 A load)
Low ground current (35 μA typ. at no load)
Output voltage tolerance: ±1% all over temperature range, ±0.5% at 25 °C
1 A guaranteed output current
50 mV output voltage step available from 0.4 V to 1.8 V
100 mV output voltage step available from 1.9 V to 3.6 V
Adjustable version from 0.5 V to 3.0 V
Logic-controlled electronic shutdown
Internal current limit
Thermal shutdown
Output active discharge function
Available in Flip Chip6 (0.8x1.2 mm) package
Temperature range: -40 °C to 85 °C
Applications
•
•
•
Smartphones
Product status link
Cameras
LD57100
Low voltage, low noise post regulation
Description
The LD57100 is a high accuracy voltage regulator, which provides 1 A of current. It
is equipped with an NMOS pass transistor, whose gate is biased by a dedicated pin,
thus allowing the ultra-low drop performance even at very low input voltages.
It is available in Flip Chip6 (0.8x1.2 mm), maximizing the space saving. This device
is stabilized with a small ceramic capacitor on the output. The ultra low drop, low
quiescent current and short-circuit protection make the LD57100 suitable for low
power battery-operated applications.
An enable logic control function puts the LD57100 in shutdown mode allowing a total
current consumption lower than 0.1 µA. Thermal protection is also included.
DS13123 - Rev 5 - April 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
LD57100
Diagrams
1
Diagrams
Figure 1. Block diagram fixed version
VBIAS
EN
VIN
Thermal
protection
Vref
VOUT
SNS
Current limiter
EN
GND
Figure 2. Block diagram adjustable version
VBIAS
EN
VIN
Thermal
protection
Vref
VOUT
FB
Current limiter
EN
GND
DS13123 - Rev 5
page 2/21
LD57100
Pin configuration
2
Pin configuration
Figure 3. Pin connection (top view)
2
1
VIN
VOUT
A
B
C
SNS/FB
GND
EN
VBIAS
Table 1. Pin description
Pin #
A1
Symbol
Functions
Output voltage
Input voltage
V
OUT
V
A2
IN
Output voltage sense pin in fixed version. Connect to the load with a separate PCB track.
Feedback pin in adjustable version. Connect to the resistor divider central node
B1
SNS / FB
B2
C1
C2
EN
Enable pin logic input: low = shutdown, high = active
Common ground
GND
V
Bias supply input
BIAS
DS13123 - Rev 5
page 3/21
LD57100
Typical application circuits
3
Typical application circuits
Figure 4. Typical application for fixed version
VIN
VIN
VBIAS
VOUT
VBIAS
VOUT
LD5710 0
CBIAS
E N
COUT
CIN
S NS
GND
Figure 5. Typical application for adjustable version
VIN
VIN
VBIAS
VOUT
VBIAS
E N
VOUT
LD5710 0
CBIAS
R1
R2
COUT
CIN
FB
GND
Table 2. Typical application components
Symbol
Value
Description
Input capacitor
Note
C
IN
1 µF
4.7 µF
10 µF
Ceramic type
Ceramic type
C
BIAS
Control logic bypass capacitor
Output capacitor
C
OUT
Ceramic type
R
R
Output voltage side resistor
Ground side resistor
See Section 6.4 VOUT setting (adjustable version)
<500 kΩ max.
1
2
DS13123 - Rev 5
page 4/21
LD57100
Absolute maximum ratings
4
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
, V
Parameter
Value
Unit
V
V
Input voltage
Output voltage
-0.3 to 7
IN
BIAS
V
, V , V
OUT
-0.3 to V + 0.3
V
FB
SNS
IN
V
EN
Enable input voltage
-0.3 to 7
V
Internally limited
I
Output current
A
OUT
(see I in Table 7. Electrical characteristics)
SC
T
STG
Storage temperature range
- 40 to 150
°C
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. All values are referred to GND.
Table 4. Thermal data
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient(1)
R
thJA
60
°C/W
1. We considered the STD JEDEC board 4 layers (2s2p) 101.5 x114.5 mm with a top copper plane of 4x4 mm.
Table 5. ESD performance
Symbol
Parameter
Test conditions
HBM
Value
2
Unit
kV
V
ESD
ESD protection voltage
CDM
500
Table 6. Recommended operating conditions
Parameter
Supply input voltage, V
Value
0.6 to 5.5
3 to 5.5
Unit
V
IN
Supply input voltage, BIAS
Junction temperature range
V
- 40 to 125
ºC
DS13123 - Rev 5
page 5/21
LD57100
Electrical characteristics
5
Electrical characteristics
VBIAS = 3.0 V or VOUT + 1.6 V (whichever is greater); VIN = VOUT(NOM) + 0.3 V; IOUT = 1 mA; CIN = 4.7 µF, COUT
= 10 µF; CBIAS = 1 µF, VEN = 1 V; typical values are at TJ = 25 °C; min./max. values are at -40 °C ≤ TJ ≤ 85 °C,
unless otherwise specified.
Table 7. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
V
+
OUT
V
Operating input voltage
5.5
V
IN
DROP
(V
+
OUT
V
Operating bias voltage
5.5
V
1.60) ≥
3.0
BIAS
V
rising
BIAS
1.45
0.15
1.6
1.75
0.25
V
V
T = 25 °C
J
Bias undervoltage
lockout
V
UVLO
Hysteresis
0.2
0.5
T = 25 °C
J
Reference voltage for
adjustable devices
V
T = 25 °C;
J
0.4975
-0.5
0.5025
0.5
V
REF
All versions, as per conditions above
+ 0.3 V ≤ V ≤ V + 1.0 V;
OUT(NOM)
%
V
OUT(NOM)
IN
3.0 V or V
greater) ≤ V
+ 1.6 V (whichever is
≤ 5.5 V;
Output voltage
accuracy
OUT(NOM)
V
OUT
BIAS
-1.0
+1.0
%
I
= 1 mA to 1 A;
OUT
-40 °C ≤ T ≤ 85 °C
J
V
+ 0.3 V ≤ V ≤ 5.0 V,
OUT(NOM)
IN
∆V
V
V
static regulation
line regulation
0.01
0.01
0.1
0.1
% / V
% / V
OUT-IN
IN
T = 25 °C
J
3.0 V or V
greater) ≤ V
+ 1.6 V (whichever is
OUT(NOM)
≤ 5.5 V,
BIAS
∆V
∆V
OUT-BIAS
BIAS
T = 25 °C
J
I
I
= 1 mA to 1 A, T = 25 °C
J
Static load regulation
Dropout voltage
1.0
40
2.0
80
mV
mV
OUT-LOAD
OUT
OUT
V
= 1 A; V
= 97% of V
OUT OUT(NOM)
DROP
V
V
=V ; I
= 1 A; V = 97% of
OUT
BIAS
IN OUT
Bias dropout voltage (1)
Output current limit
V
1.05
1.5
V
A
DROP-BIAS
OUT(NOM)
V
OUT
V
OUT
= 90% V
1.5
2
2
2.6
2.6
OUT(NOM)
I
LIM
= 90% V
, −30 °C ≤ T ≤ 85 °C
J
1.55
OUT(NOM)
FB/SNS pin operating
current
I
, I
0.1
35
0.5
50
µA
µA
FB SNS
VBIAS operating
current
I
V
= 3.0 V, I
= 0 mA
BIAS
BIAS
OUT
I
V
standby current
V
V
input current in OFF mode: V = GND
EN
0.1
0.1
1
1
µA
µA
Standby-BIAS
BIAS
BIAS
I
V
standby current
input current in OFF mode: V = GND
IN EN
Standby-IN
IN
Enable input logic low
Enable input logic high
0.4
V
V
EN
0.9
DS13123 - Rev 5
page 6/21
LD57100
Electrical characteristics
Symbol
Parameter
Test conditions
= 5.5 V
Min.
Typ.
Max.
Unit
I
V
= V
EN BIAS
Enable pin input current
0.2
1
µA
EN
From assertion of V to V
=
OUT
EN
T
Turn-on time
160
70
µs
ON
98% V
, V
= 1.0 V
OUT(NOM)
OUT(NOM)
V
V
= V
+ 0.5 V +/- V
OUT(NOM) RIPPLE
IN
V
supply voltage
IN
SVR
= 0.2 V; freq=1 kHz
dB
IN-ADJ
RIPPLE
rejection (adj version)
I
= 10 mA; V
= 1.0 V
OUT(NOM)
OUT
V
V
V
= 3.0 V +/- V
,
BIAS
RIPPLE
= 0.2 V; freq=1 kHz;
RIPPLE
V
supply voltage
BIAS
SVR
85
dB
BIAS-ADJ
rejection (adj version)
= V
+ 0.5 V
OUT(NOM)
IN
I
= 10 mA; V
= 1.0 V
OUT
OUT(NOM)
35 x
V
= V
+ 0.5 V; V
= 1.0 V;
Output noise voltage
(adj version)
IN
OUT(NOM)
OUT(NOM)
V
/
e
µV
RMS
OUT
N-ADJ
10 Hz to 100 kHz, I
= 1 mA
OUT
V
REF
V
V
= V
+ 0.5 V +/- V
OUT(NOM) RIPPLE
IN
VIN supply voltage
rejection (adj version)
SVR
= 0.2 V; freq=1 kHz
75
dB
dB
IN-FIX
RIPPLE
OUT
I
= 10 mA; V
= 1.8 V
OUT(NOM)
V
V
V
= 4.0 V +/- V
RIPPLE
BIAS
V
BIAS
supply voltage
= 0.2 V; freq=1 kHz;
RIPPLE
SVR
85
rejection (fixed
versions)
BIAS-FIX
= V
+ 0.5 V
IN
OUT(NOM)
I
= 10 mA; V
= 1.8 V
OUT
OUT(NOM)
V
= V
+ 0.5 V; V
= 1.0 V;
Output noise voltage
(fixed versions)
IN
OUT(NOM)
OUT(NOM)
e
N-FIX
µV
RMS
27
10 Hz to 100 kHz, I
= 1 mA
OUT
Output voltage
discharge MOSFET
R
ON
150
Ω
Thermal shutdown
Hysteresis
160
20
T
°C
SHDN
1. Not applicable to fixed versions with V
< 2.0 V.
OUT(NOM)
DS13123 - Rev 5
page 7/21
LD57100
Application information
6
Application information
6.1
V
pin voltage requirements
BIAS
The bias input is the supply of the internal driving and control circuitry. In order to assure a proper biasing of the
N-channel power element, the bias pin must have a minimum voltage of 3.0 V and be 1.6 V (typically) higher than
the output. If VIN supply voltage meets these requirements then the bias pin can be tied to VIN.
6.2
Output discharge function
The LD57100 integrates a MOSFET connected between VOUT and GND. This transistor is activated when the
EN pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is
disabled by the user.
6.3
6.4
Short-circuit and current limitation
The LD57100 is protected against short-circuit on the output. The load current is limited to the maximum value of
ILIM when VOUT is equal to 90% of its nominal value.
V
setting (adjustable version)
OUT
In the LD57100 adjustable version, the desired output voltage is set according to the formula below:
R
1
V
= V
REF
×
1 +
(1)
OUT
R
2
where R2 cannot be higher than 500 kΩ.
Please, refer to Figure 5. Typical application for adjustable version for R1 and R2 connections.
6.5
6.6
Thermal protection
Thermal protection works when the junction temperature reaches 160 °C typical. At this point, the output of the
IC shuts down. As soon as the junction temperature falls below the thermal hysteresis value, the device starts
working again.
In order to calculate the maximum power that the device can dissipate, keeping the junction temperature below
the maximum operating value, the following formula is used:
P
=
85 − T
/R
AMB tℎJA
(2)
DMAX
Input and output capacitors
The LD57100 requires external capacitors to assure the regulator control loop stability.
Any good quality ceramic capacitor can be used, however the X5R and the X7R are suggested since they
guarantee a very stable combination of capacitance and ESR all over the temperature range.
It is recommended to place the input/output capacitors as close as possible to the relative pins. The LD57100
requires a VIN capacitor with a minimum value of 1 μF and a VBIAS capacitor of 100 nF minimum. These
capacitors must be placed as close as possible to the input pins of the device and returned to a clean analog
ground.
The control loop is designed to be stable with any good quality output ceramic capacitor (such as: X5R/X7R
types) with a minimum value of 1.0 μF and equivalent series resistance in the [3 – 300 mΩ] range. It is important
to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the
full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR
variations must be taken into account in the design phase to be sure that the device works in the expected
stability region.
DS13123 - Rev 5
page 8/21
LD57100
Typical characteristics
7
Typical characteristics
CIN = 1 µF; COUT = 10 µF, TJ = 25 °C unless otherwise specified.
Figure 6. VIN drop vs temperature
Figure 7. UVLO vs temperature
80
70
60
50
40
30
20
10
0
1.8
1.7
Rising
Falling
1.6
1.5
1.4
1.3
Iout=1A
Iout=500mA
-75
-50
-25
0
25
50
75
100
125
150
Iout=250mA
[ C
° ]
T
-50
-25
0
25
50
75
100
125
150
T[°C]
Figure 8. VOUT vs temperature (VBIAS@3 V, VIN@VOUT +0.3 Figure 9. VOUT vs temperature (VBIAS@3 V, VIN@VOUT +0.3
V@1 mA) V@1 A)
506
505
503
502
500
499
497
496
494
506
505
503
502
500
499
497
496
494
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100 125 150
T [°C]
T [°C]
Figure 11. VBIAS_line vs temp. (3.0 V or VOUT(NOM) + 1.6 V,
whichever is greater, ≤ VBIAS ≤ 5.5 V)
Figure 10. Vin_line vs temp. (VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0
V)
3.0 V or V
OUT(NOM) + 1.6 V (whichever is
BIAS≤ 5.5 V
greater) ≤ V
V
OUT(NOM)
+ 0.3 V ≤ V
IN
≤ 5.0 V
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
T [°C]
75
100 125 150
-50
-25
0
25
T [°C]
50
75
100 125 150
DS13123 - Rev 5
page 9/21
LD57100
Typical characteristics
Figure 13. ISENSE vs temperature
Figure 12. Load vs temperature
IOUT = 1 mA to 1 A
20
16
12
8
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4
0
-50
-25
0
25
50
T [°C]
75
100
125
150
-50
-25
0
25
50
75
100
125 150
T [°C]
Figure 14. IBIAS vs temperature
Figure 15. Enable high vs temperature (VBIAS min.)
250
225
200
175
150
125
100
75
0.90
0.80
0.70
Iout=1A
ON
0.60
0.50
OFF
Iout=1mA
50
25
0
0.40
0.30
-50
-25
0
25
50
75
100 125
150
-50
-25
0
25
50
75
100
T [°C]
T [°C]
Figure 16. IENABLE vs temperature
Figure 17. Ground pin current vs load current
60
50
40
30
20
10
0
0.50
0.40
0.30
0.20
0.10
0.00
-50
-25
0
25
50
75
100 125 150
0
100
200
300
400
500
600
700
800
900
1000
T [°C]
Iout [mA]
DS13123 - Rev 5
page 10/21
LD57100
Typical characteristics
VOUT = 0.5 V, CIN = 4.7 µF, COUT = 10 µF, CBIAS = 1 µF, trise fall = 5 µs
/
Figure 18. Input voltage turn-on (VIN= from 0 V to 0.8 V,
VBIAS=3 V, VEN=0.8 V, IOUT=1 A)
Figure 19. Load transient (VIN=0.8 V, VBIAS=3 V, VEN=1 V,
IOUT from 1 mA to 1 A)
Figure 20. Line transient vs input voltage (VIN= from 0.8 V
to 1.08 V, VBIAS=3 V, VEN=1 V, IOUT 100 mA)
Figure 21. Line transient vs BIAS voltage (VIN=0.8 V to
1.08 V, VBIAS= from 2.8 to 3.8 V, VEN=1 V, IOUT=100 mA)
Figure 22. VBIAS PSRR vs frequency
Figure 23. VIN PSRR vs frequency
110
100
90
100
90
80
80
70
70
60
60
Test condition:
50
Vripple=200mVpkpk
50
Cout=10uF MLCC 0603
Headroom=500mV
Vbias=4V, V_EN=1V
40
40
Test condition:
Vripple=200mVpkpk
30
30
Cout=10uF MLCC 0603
Headroom=500mV
20
10
0
20
Vbias=3V, V_EN=1V
Iload=10mA
10
0
0.01
0.10
1.00
10.00
100.00
1,000.00
10,000.00
0.01
0.10
1.00
10.00
100.00
1,000.00
10,000.00
Frequency(kHz)
Frequency(kHz)
DS13123 - Rev 5
page 11/21
LD57100
Typical characteristics
Figure 24. Output voltage spectral noise density vs
frequency (VOUT= 1 V adj.)
Figure 25. Output voltage spectral noise density vs
frequency
1.000
1.000
0.100
0.100
Frequency Range: 10Hz-
100kHz
Output Noise:
1mA 20 μVRMS
10mA34 μVRMS
100mA44 μVRMS
500mA 42μVRMS
Frequency Range: 10Hz-
1MHz
Frequency Range: 10Hz -
100kHz
Output Noise:
1mA 41 μVRMS
10mA 52 μVRMS
100mA 70 μVRMS
500mA 51 μVRMS
Frequency Range: 10Hz -
1MHz
Output Noise:
1mA 41 μVRMS
10mA 53 μVRMS
100mA 99 μVRMS
500mA 29119 μVRMS
0.010
0.001
0.000
0.010
Iout = 1mA
Output Noise:
Iout = 1mA
0.001
Iout = 10mA
Iout = 100mA
Iout = 500mA
1mA 20 μVRMS
10mA36μVRMS
100mA81μVRMS
500mA 29112 μVRMS
Iout = 10mA
Iout = 100mA
0.000
0.01
0.1
1
10
100
1000
10000
0.01
0.1
1
10
100
1000
10000
Frequency: f [kHz]
Frequency: f [kHz]
Figure 26. Discharge_RMOS vs temperature
210
200
190
180
170
160
150
140
-50
-25
0
25
50
75
100 125 150
T [°C]
DS13123 - Rev 5
page 12/21
LD57100
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
8.1
Flip Chip6 (0.8x1.2 mm) package information
Figure 27. Flip Chip6 (0.8x1.2 mm) package outline
DS13123 - Rev 5
page 13/21
LD57100
Flip Chip6 (0.8x1.2 mm) package information
Table 8. Flip Chip6 (0.8x1.2 mm) package mechanical data
Milimeters
Typ.
Symbol
Min.
0.277
0.045
0.205
0.022
0.210
1.155
0.755
Max.
0.361
0.075
0.255
0.028
0.270
1.195
0.795
A
A1
A2
A3
b
0.315
0.060
0.230
0.025
0.240
D
1.175
E
0.775
D1
E1
e
0.8 BSC
0.4 BSC
0.4 BSC
0.2 BSC
0.03
SE
aaa
bbb
ccc
ddd
0.06
0.03
0.015
Figure 28. Flip Chip6 (0.8x1.2 mm) recommended footprint
DS13123 - Rev 5
page 14/21
LD57100
Flip Chip6 (0.8x1.2 mm) packing information
8.2
Flip Chip6 (0.8x1.2 mm) packing information
Figure 29. Flip Chip6 (0.8x1.2 mm) carrier tape outline
DS13123 - Rev 5
page 15/21
LD57100
Ordering information
9
Ordering information
Table 9. Order codes
V
Order code
LD57100J100R
LD57100J105R
LD57100J800R
LD57100J110R
LD57100J120R
LD57100JR
Marking
OUT
1.00 V
1.05 V
JB
JC
JF
JD
JE
JA
0.8 V
1.10 V
1.20 V
Adjustable
DS13123 - Rev 5
page 16/21
LD57100
Revision history
Table 10. Document revision history
Date
Version
Changes
30-Oct-2019
1
Initial release.
Updated Figure 2. Block diagram adjustable version, Figure 22. V
PSRR
BIAS
vs frequency and Figure 23. V PSRR vs frequency .
IN
20-Dec-2019
2
Updated Table 3. Absolute maximum ratings and Table 6. Electrical
characteristics.
20-Jan-2020
22-Feb-2021
3
4
Updated Table 6. Electrical characteristics and Table 8. Order codes.
Added new order code LD57100J120R in Table 9. Order codes.
Added new Table 6. Recommended operating conditions.
21-Apr-2021
5
Updated V
and V
values in Table 7. Electrical characteristics.
OUT
REF
DS13123 - Rev 5
page 17/21
LD57100
Contents
Contents
1
2
3
4
5
6
Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
6.1
6.2
6.3
6.4
6.5
6.6
V
pin voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BIAS
Output discharge function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Short-circuit and current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
setting (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OUT
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input and output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
8
Typical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
8.1
8.2
Flip Chip6 (0.8x1.2 mm) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Flip Chip6 (0.8x1.2 mm) packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DS13123 - Rev 5
page 18/21
LD57100
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical application components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flip Chip6 (0.8x1.2 mm) package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DS13123 - Rev 5
page 19/21
LD57100
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Block diagram fixed version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram adjustable version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical application for fixed version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical application for adjustable version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
VIN drop vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
UVLO vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VOUT vs temperature (VBIAS@3 V, VIN@VOUT +0.3 V@1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VOUT vs temperature (VBIAS@3 V, VIN@VOUT +0.3 V@1 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Vin_line vs temp. (VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VBIAS_line vs temp. (3.0 V or VOUT(NOM) + 1.6 V, whichever is greater, ≤ VBIAS ≤ 5.5 V) . . . . . . . . . . . . . . . . . . 9
Load vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ISENSE vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IBIAS vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Enable high vs temperature (VBIAS min.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IENABLE vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ground pin current vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input voltage turn-on (VIN= from 0 V to 0.8 V, VBIAS=3 V, VEN=0.8 V, IOUT=1 A) . . . . . . . . . . . . . . . . . . . . . . 11
Load transient (VIN=0.8 V, VBIAS=3 V, VEN=1 V, IOUT from 1 mA to 1 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Line transient vs input voltage (VIN= from 0.8 V to 1.08 V, VBIAS=3 V, VEN=1 V, IOUT 100 mA). . . . . . . . . . . . . 11
Line transient vs BIAS voltage (VIN=0.8 V to 1.08 V, VBIAS= from 2.8 to 3.8 V, VEN=1 V, IOUT=100 mA) . . . . . . 11
VBIAS PSRR vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VIN PSRR vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage spectral noise density vs frequency (VOUT= 1 V adj.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage spectral noise density vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Discharge_RMOS vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flip Chip6 (0.8x1.2 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flip Chip6 (0.8x1.2 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flip Chip6 (0.8x1.2 mm) carrier tape outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DS13123 - Rev 5
page 20/21
LD57100
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13123 - Rev 5
page 21/21
相关型号：
LD5805
Step up, 4 strings, Max. 250mA/string, Multi-dimming mode WLED Backlight Controller
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