LPS22HB [STMICROELECTRONICS]
ABSOLUTE, PEIZORESISTIVE PRESSURE SENSOR, 3.77-18.274Psi, SQUARE, SURFACE MOUNT, 2 X 2 MM, 0.76 MM HEIGHT, ROHS COMPLIANT, HLGA-10;
| 型号： | LPS22HB |
| 厂家： | 
ST |
| 描述： | ABSOLUTE, PEIZORESISTIVE PRESSURE SENSOR, 3.77-18.274Psi, SQUARE, SURFACE MOUNT, 2 X 2 MM, 0.76 MM HEIGHT, ROHS COMPLIANT, HLGA-10 输出元件 传感器 换能器 |
| 文件： | 总37页 (文件大小：876K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPS22HB
MEMS nano pressure sensor: 260-1260 hPa absolute
digital output barometer
Datasheet - target specification
Applications
Altimeter and barometer for portable devices
GPS applications
Weather station equipment
Sport watches
HLGA 10L
2.0 x 2.0 x 0.76 mm
Description
The LPS22HB is an ultra-compact piezoresistive
absolute pressure sensor which functions as a
digital output barometer. The device comprises a
Features
260 to 1260 hPa absolute pressure range
Current consumption down to 4 μA
High overpressure capability: 20x full scale
Embedded temperature compensation
24-bit pressure data output
sensing element and an IC interface which
2
communicates through I C or SPI from the
sensing element to the application.
The sensing element, which detects absolute
pressure, consists of a suspended membrane
manufactured using a dedicated process
developed by ST.
16-bit temperature data output
ODR from 1 Hz to 75 Hz
The LPS22HB is available in a full-mold, holed
LGA package (HLGA). It is guaranteed to operate
over a temperature range extending from -40 °C
to +85 °C. The package is holed to allow external
pressure to reach the sensing element.
SPI and I²C interfaces
Embedded FIFO
Interrupt functions: Data Ready, FIFO flags,
pressure thresholds
Supply voltage: 1.7 to 3.6 V
High shock survivability: 22,000 g
Small and thin package
®
ECOPACK lead-free compliant
Table 1. Device summary
Order codes
Temperature range [°C]
Package
Packing
LPS22HBTR
LPS22HB
HLGA-10L
HLGA-10L
Tape and reel
Tray
-40 to +85°C
October 2014
DocID027083 Rev 1
1/37
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.st.com
Contents
LPS22HB
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1
2.3.2
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
I C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0.1
4.0.2
4.0.3
4.0.4
4.0.5
4.0.6
4.0.7
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bypass-to-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
6
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
6.1
6.2
I C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
I C serial interface (CS = High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
6.2.1
I C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
6.3.2
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
6.3.3
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
8
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
INTERRUPT_CFG (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
THS_P_L (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
THS_P_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
WHO_AM_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTRL_REG1 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTRL_REG2 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CTRL_REG3 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIFO_CTRL (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REF_P_XL (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.10 REF_P_L (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.11 REF_P_H (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.12 RPDS_L (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13 RPDS_H (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.14 RES_CONF (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.15 INT_SOURCE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.16 FIFO_STATUS (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.17 STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.18 PRESS_OUT_XL (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.19 PRESS_OUT_L (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.20 PRESS_OUT_H (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.21 TEMP_OUT_L (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.22 TEMP_OUT_H (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10
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List of tables
LPS22HB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pressure and temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
I C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
I C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19
Registers address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output data rate bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Low-pass filter configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupt configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIFO mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
I C slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LPS22HB electrical connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. HLGA - 10L (2.0 x 2.0 x 0.76 mm typ.) outline and mechanical data . . . . . . . . . . . . . . . . . 35
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Block diagram and pin description
LPS22HB
1
Block diagram and pin description
Figure 1. Block diagram
p
DSP for
Temperature
Compensation
I2 C
SPI
MUX
Temperature
sensor
Sensing
element
Voltage and
current bias
Clock and timing
Sensor bias
Figure 2. Pin connections (bottom view)
1
7
2
6
VDD
GND
GND
10
9
RES
3
4
5
SDA/SDI/SDO
SDO/SA0
8
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Block diagram and pin description
Table 2. Pin description
Pin number
Name
Function
1
Vdd_IO
Power supply for I/O pins
SCL
SPC
I2C serial clock (SCL)
2
3
SPI serial port clock (SPC)
Reserved
Connect to GND
SDA
SDI
I2C serial data (SDA)
4
5
4-wire SPI serial data input (SDI)
SDI/SDO
3-wire serial data input/output (SDI/SDO)
SDO
SA0
4-wire SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)
SPI enable
I2C/SPI mode selection
6
7
CS
(1: SPI idle mode / I2C communication enabled;
0: SPI communication mode / I2C disabled)
INT_DRDY
Interrupt or Data Ready
8
9
GND
GND
VDD
0 V supply
0 V supply
Power supply
10
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Mechanical and electrical specifications
LPS22HB
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Table 3. Pressure and temperature sensor characteristics
Symbol
Pressure sensor characteristics
Operating temperature range
Parameter
Test condition
Min.
Typ.(1)
Max.
Unit
-40
+85
°C
PT
op
PTfull
Pop
Full accuracy temperature range
Operating pressure range
Pressure output data
0
+65
°C
hPa
bits
260
1260
Pbits
24
LSB/
hPa
Psens
Pressure sensitivity
4096
P = 800 - 1100 hPa
T = 25 °C
PAccRel
Relative accuracy over pressure(2)
±0.1
±0.1
hPa
hPa
Pop
T = 0 to 65 °C
After OPC(3)
Pop
PAccT
Absolute accuracy over temperature
RMS pressure sensing noise(4)
T = 0 to 65 °C
no OPC (3)
±1
without embedded
filtering
hPa
RMS
Pnoise
0.01
1
10
25
50
75
ODRPres Pressure output data rate(5)
Hz
Temperature sensor characteristics
Top
Tsens
Tacc
Operating temperature range
Temperature sensitivity
-40
+85
°C
LSB/°C
°C
100
±1.5
1
Temperature absolute accuracy
T = 0 to 65 °C
10
ODRT
Output temperature data rate(5)
25
Hz
50
75
1. Typical specifications are not guaranteed.
2. Parameter not tested at final test
3. OPC: One Point Calibration, see registers RPDS_L/H (18h,19h).
4. Pressure noise RMS evaluated in a controlled environment, based on the average standard deviation of 32 measurements
at highest ODR.
5. Output data rate is configured acting on ODR[2:0] in CTRL_REG1 (10h)
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Mechanical and electrical specifications
2.2
Electrical characteristics
VDD = 1.8 V, T = 25 °C, unless otherwise noted.
Table 4. Electrical characteristics
Symbol
Parameter
Supply voltage
Test condition
Min.
Typ.(1)
Max.
Unit
VDD
1.7
1.7
3.6
V
V
Vdd_IO IO supply voltage
Vdd+0.1
@ ODR 1 Hz
LC_EN bit = 0
15
Idd
Supply current
μA
μA
@ ODR 1 Hz
LC_EN bit = 1
4
1
IddPdn Supply current in power-down mode
1. Typical specifications are not guaranteed.
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Mechanical and electrical specifications
LPS22HB
2.3
Communication interface characteristics
2.3.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T
.
OP
Table 5. SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min
Max
tc(SPC)
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
SPI clock cycle
100
ns
SPI clock frequency
CS setup time
10
MHz
6
8
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
5
15
ns
tv(SO)
th(SO)
tdis(SO)
50
50
9
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on
characterization results, not tested in production.
Figure 3. SPI slave timing diagram
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
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Mechanical and electrical specifications
2
2.3.2
I C - inter-IC control interface
Subject to general operating conditions for Vdd and T
.
OP
2
Table 6. I C slave timing values
I²C standard mode(1)
(1)
I²C fast mode
(1)
Parameter
Symbol
Unit
Min
0
Max
Min
Max
f
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
100
0
1.3
400
kHz
(SCL)
t
4.7
4.0
250
0.01
w(SCLL)
μs
t
0.6
w(SCLH)
t
100
ns
su(SDA)
t
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
3.45
1000
300
0
0.9
300
300
μs
h(SDA)
(2)
(2)
tr(SDA)
tf(SDA)
t
t
t
20 + 0.1Cb
20 + 0.1Cb
0.6
r(SCL)
ns
f(SCL)
4
h(ST)
Repeated START condition
setup time
t
4.7
4
0.6
0.6
1.3
su(SR)
μs
t
STOP condition setup time
su(SP)
Bus free time between STOP
t
4.7
w(SP:SR)
and START condition
2
1. Data based on standard I C protocol requirement, not tested in production.
2. C = total capacitance of one bus line, in pF.
b
2
Figure 4. I C slave timing diagram
REPEATED
START
START
tsu(SR)
START
tw(SP:SR)
SDA
SCL
tsu(SDA)
th(SDA)
tf(SDA)
tr(SDA)
STOP
tsu(SP)
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
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Mechanical and electrical specifications
LPS22HB
2.4
Absolute maximum ratings
Stress above those listed as “Absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 7. Absolute maximum ratings
Symbol
Ratings
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
-0.3 to 4.8
-0.3 to Vdd_IO +0.3
2
V
V
Vdd_IO I/O pins supply voltage
Vin
P
Input voltage on any control pin
Overpressure
V
MPa
°C
kV
TSTG
ESD
Storage temperature range
Electrostatic discharge protection
-40 to +125
2 (HBM)
Note:
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.
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Functionality
3
Functionality
The LPS22HB is a high resolution, digital output pressure sensor packaged in an HLGA full-
mold package. The complete device includes a sensing element based on a piezoresistive
Wheatstone bridge approach, and an IC interface which communicates a digital signal from
the sensing element to the application.
3.1
3.2
Sensing element
An ST proprietary process is used to obtain a silicon membrane for MEMS pressure
sensors. When pressure is applied, the membrane deflection induces an imbalance in the
Wheatstone bridge piezoresistances whose output signal is converted by the IC interface.
Intrinsic mechanical stoppers prevent breakage in case of excessive pressure, ensuring
measurement repeatability.
I2C interface
The complete measurement chain is composed of a low-noise amplifier which converts the
resistance unbalance of the MEMS sensors (pressure and temperature) into an analog
voltage using an analog-to-digital converter.
The pressure and temperature data may be accessed through an I²C/SPI interface thus
making the device particularly suitable for direct interfacing with a microcontroller.
The LPS22HB features a Data-Ready signal which indicates when a new set of measured
pressure and temperature data are available, thus simplifying data synchronization in the
digital system that uses the device.
3.3
Factory calibration
The IC interface is factory calibrated at three temperatures and two pressures for sensitivity
and accuracy.
The trimming values are stored inside the device in a non-volatile structure. When the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during normal operation which allows the device to be used without requiring any
further calibration.
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FIFO
LPS22HB
4
FIFO
The LPS22HB embeds 32-slot data FIFO to store the pressure and temperature output values.
The FIFO allows consistent power saving for the system, since the host processor does not
need to continuously poll data from the sensor, but it can wake up only when needed and
burst the significant data out from the FIFO.
This buffer can work according to six different modes: Bypass mode, FIFO mode, Stream
mode, Stream-to-FIFO mode, Bypass-to-Stream mode and Bypass-to-FIFO mode.
The FIFO buffer is enabled when the FIFO_EN bit in CTRL_REG2 (11h) is set to ‘1’ and
each mode is selected by the FIFO_MODE[2:0] bits in FIFO_CTRL (14h).
FIFO threshold status, FIFO overrun events and the number of unread samples stored are
available in the FIFO_STATUS (26h) register and can be set to generate dedicated
interrupts on the INT_DRDY pin using the CTRL_REG3 (12h) register.
4.0.1
4.0.2
Bypass mode
In Bypass mode (F_MODE[2:0] in FIFO_CTRL (14h) set to ‘000’), the FIFO is not
operational and it remains empty.
FIFO mode
In FIFO mode (F_MODE[2:0] in FIFO_CTRL (14h) set to ‘001’), the data from
PRESS_OUT_H (2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL (28h) and
TEMP_OUT_H (2Ch) and TEMP_OUT_L (2Bh) are stored in the FIFO.
A watermark interrupt can be enabled (STOP_ON_FTH bit set to ‘1’ in CTRL_REG2 (11h))
in order to be raised when the FIFO is filled to the level specified by the WTM[4:0] bits of
FIFO_CTRL (14h). The FIFO continues filling until it is full (32 slots of data for pressure and
temperature output). When full, the FIFO stops collecting data.
4.0.3
4.0.4
Stream mode
In Stream mode (F_MODE[2:0] in FIFO_CTRL (14h) set to ‘010’), the data from
PRESS_OUT_H (2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL (28h) and
TEMP_OUT_H (2Ch) and TEMP_OUT_L (2Bh) are stored in the FIFO. The FIFO continues
filling until it’s full (32 slots of data for pressure and temperature output). When full, the FIFO
discards the older data as the new arrive. A watermark interrupt can be enabled and set as
in FIFO mode.
Stream-to-FIFO mode
In Stream-to-FIFO mode (F_MODE[2:0] in FIFO_CTRL (14h) set to ‘011’), the data from
PRESS_OUT_H (2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL (28h) and
TEMP_OUT_H (2Ch) and TEMP_OUT_L (2Bh) are stored in the FIFO.
A Watermark interrupt can be enabled (STOP_ON_FTH bit set to ‘1’ in CTRL_REG2 (11h))
in order to be raised when the FIFO is filled to the level specified by the WTM[4:0] bits of
FIFO_CTRL (14h).The FIFO continues filling until it’s full (32 slots of data for pressure and
temperature output). When full, the FIFO discards the older data as the new arrive. Once a
trigger event occurs, the FIFO starts operating in FIFO mode. A trigger event can be configured in
INTERRUPT_CFG (0Bh).
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FIFO
4.0.5
Bypass-to-Stream mode
In Bypass-to-Stream mode (F_MODE[2:0] in FIFO_CTRL (14h) set to ‘100’), the FIFO is in
Bypass mode until a trigger event occurs and the FIFO starts operating in Stream mode. A
trigger event can be configured in INTERRUPT_CFG (0Bh).
4.0.6
4.0.7
Bypass-to-FIFO mode
In Bypass-to-FIFO (F_MODE[2:0] in FIFO_CTRL (14h) set to ‘001’), the FIFO is in Bypass
mode until a trigger event occurs and the FIFO starts operating in FIFO mode. A trigger event
can be configured in INTERRUPT_CFG (0Bh).
Retrieving data from FIFO
When the FIFO is enabled, FIFO data are read from PRESS_OUT_H (2Ah),
PRESS_OUT_L (29h), PRESS_OUT_XL (28h), TEMP_OUT_H (2Ch) and TEMP_OUT_L
(2Bh) registers.
Each time data is read from the FIFO, the oldest data are placed in the PRESS_OUT_H
(2Ah), PRESS_OUT_L (29h), PRESS_OUT_XL (28h), TEMP_OUT_H (2Ch) and
TEMP_OUT_L (2Bh) registers and both single-read and read-burst operations can be used.
The reading address is automatically updated by the device and it rolls back to 28h when
register 2Ch is reached. In order to read all FIFO levels in a multiple byte reading, 160 bytes
(5 output registers by 32 levels) must be read.
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Application hints
LPS22HB
5
Application hints
Figure 5. LPS22HB electrical connections (top view)
GND
C2
GND
C1
VDD
GND
10
9
4
8
Vdd_IO
SCL/SPC
1
2
7
6
INT_DRDY
CS
3
5
GND
Power supply decoupling capacitors C (100nF) and C (4.7μF) should be placed as near as
1
2
possible to the supply pad of the device (common design practice).
The functionality of the device and the measured data outputs are selectable and accessible
2
through the I²C/SPI interface. When using the I C, CS must be tied to Vdd_IO.
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove VDD while maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
5.1
Soldering information
The HLGA package is compliant with the ECOPACK® standard and it is qualified for
soldering heat resistance according to JEDEC J-STD-020.
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Digital interfaces
6
Digital interfaces
6.1
I2C serial interface
The registers embedded in the LPS22HB may be accessed through both the I²C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
Table 8. Serial interface pin description
Pin name
Pin description
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI
CS
communication mode / I2C disabled)
I²C serial clock (SCL)
SCL/SPC
SPI serial port clock (SPC)
SDA
SDI
I²C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input /output (SDI/SDO)
SDI/SDO
SDO
SAO
SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)
6.2
I2C serial interface (CS = High)
The LPS22HB I²C is a bus slave. The I²C is employed to write data into registers whose
content can also be read back.
The relevant I²C terminology is given in Table 9.
2
Table 9. I C terminology
Term
Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
Slave
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the
normal mode.
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Digital interfaces
2
LPS22HB
6.2.1
I C operation
The transaction on the bus is started through a START (ST) signal. A start condition is
defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next data byte
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed by
the master.
The slave address (SAD) associated to the LPS22HB is 101110xb. The SDO/SA0 pad can
be used to modify the less significant bit of the device address. If the SA0 pad is connected
to voltage supply, LSb is ‘1’ (address 1011101b), otherwise if the SA0 pad is connected to
ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect and
address two different LPS22HB devices to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data received.
2
The I C embedded inside the ASIC behaves like a slave device and the following protocol
must be adhered to. After the start condition (ST) a slave address is sent, once a slave
acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the
7 LSB represent the actual register address while the MSB has no meaning. The
IF_ADD_INC bit in CTRL2 register (11h) enables sub-address auto increment
(IF_ADD_INC is '1' by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be
automatically increased to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 10 explains how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
Table 10. SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
Write
Read
Write
101110
101110
101110
101110
0
0
1
1
1
0
1
0
10111001 (B9h)
10111000 (B8h)
10111011 (BBh)
10111010 (BAh)
Table 11. Transfer when master is writing one byte to slave
Master
Slave
ST
SAD + W
SUB
DATA
SP
SAK
SAK
SAK
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Digital interfaces
Table 12. Transfer when master is writing multiple bytes to slave
Master
Slave
ST
SAD + W
SUB
DATA
DATA
SP
SAK
SAK
SAK
SAK
Table 13. Transfer when master is receiving (reading) one byte of data from slave
Master
Slave
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
SAK
SAK
SAK
DATA
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
Slave
SUB
SR SAD+R
MAK
MAK
NMAK SP
SAK
SAK
SAK DATA
DATA
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be kept HIGH by
the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes incrementing the register address, it is necessary to assert
the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1
while SUB(6-0) represents the address of the first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is no
master acknowledge.
6.3
SPI bus interface
The LPS22HB SPI is a bus slave. The SPI allows writing to and reading from the registers of
the device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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Digital interfaces
LPS22HB
Figure 6. Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and returns to high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before
the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the
IF_ADD_INC bit is 0, the address used to read/write data remains the same for every block.
When the IF_ADD_INC bit is 1, the address used to read/write data is incremented at every
block.
The function and the behavior of SDI and SDO remain unchanged.
6.3.1
SPI read
Figure 7. SPI read protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7DO6 DO5DO4 DO3DO2 DO1DO0
The SPI read command is performed with 16 clock pulses. The multiple byte read command
is performed by adding blocks of 8 clock pulses to the previous one.
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Digital interfaces
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
Figure 8. Multiple byte SPI read protocol (2-byte example)
CS
SPC
SDI
SDO
6.3.2
SPI write
Figure 9. SPI write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI write command is performed with 16 clock pulses. The multiple byte write command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written in the device (MSb first).
bit 16-...: data DI(...-8). Further data in multiple byte writes.
Figure 10. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15DI14DI13DI12DI11 DI10DI9 DI8
RW
AD6 AD5 AD4AD3 AD2 AD1 AD0
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LPS22HB
6.3.3
SPI read in 3-wire mode
A 3-wire mode is entered by setting bit SIM to ‘1’ (SPI serial interface mode selection) in
CTRL_REG1.
Figure 11. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
AD5 AD4 AD3 AD2 AD1 AD0
AD6
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
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Register mapping
7
Register mapping
Table 15 provides a quick overview of the 8-bit registers embedded in the device.
Table 15. Registers address map
Register
Default
Address
Function and
comment
Name
Type
Hex
Binary
Reserved
00 - 0A
-
Reserved
INTERRUPT_CFG
THS_P_L
R/W
R/W
R/W
0B
0C
0D
0E
0F
10
00000000
00000000
THS_P_H
00000000
Reserved
-
Reserved
Who am I
WHO_AM_I
CTRL_REG1
CTRL_REG2
CTRL_REG3
Reserved
R
10110001
R/W
R/W
R/W
00000000
11
00010000
12
00000000
Interrupt control
Reserved
13
-
FIFO_CTRL
REF_P_XL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
00000000
15
00000000
REF_P_L
16
00000000
REF_P_H
17
00000000
RPDS_L
18
00000000
RPDS_H
19
00000000
RES_CONF
Reserved
1A
1B - 24
25
00000000
-
-
-
-
-
-
-
-
-
Reserved
INT_SOURCE
FIFO_STATUS
STATUS
R
R
R
R
R
R
R
R
26
27
PRESS_OUT_XL
PRESS_OUT_L
PRESS_OUT_H
TEMP_OUT_L
TEMP_OUT_H
28
29
2A
2B
2C
Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.
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Register mapping
LPS22HB
To guarantee the proper behavior of the device, all register addresses not listed in the above
table must not be accessed and the content stored in those registers must not be changed.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
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Register description
8
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
pressure and temperature data. The register address, made up of 7 bits, is used to identify
them and to read/write the data through the serial interface.
8.1
INTERRUPT_CFG (0Bh)
Interrupt configuration
7
6
5
4
3
2
1
0
AUTORIFP
RESET_ARP
AUTOZERO
RESET_AZ
DIFF_EN
LIR
PLE
PHE
AUTORIFP
AUTORIFP: AutoRifP enable. Default value: 0.
(0: normal mode; 1: AutoRifP enabled)
RESET_ARP Reset AutoRifP function. Default value: 0.
(0: normal mode; 1: reset AutoRifP function)
AUTOZERO Autozero enable. Default value: 0.
(0: normal mode; 1: Autozero enabled)
RESET_AZ
DIFF_EN
LIR
Reset Autozero function. Default value: 0.
(0: normal mode; 1: reset Autozero function)
Interrupt generation enable. Default value: 0
(0: interrupt generation disabled; 1: interrupt generation enabled)
Latch interrupt request to the INT_SOURCE register. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
PLE
Enable interrupt generation on differential pressure low event. Default value: 0.
(0: disable interrupt request; 1: enable interrupt request on measured differential
pressure value lower than preset threshold)
PHE
Enable interrupt generation on differential pressure high event. Default value: 0.
(0: disable interrupt request; 1: enable interrupt request on measured differential
pressure value higher than preset threshold)
AUTORIFP, when written to ‘1’, an internal register is set with current pressure values and
the bit is forced to ‘0’. When the bit is enabled, the content of the internal register is
subtracted from the pressure output value and result is used for the interrupt generation.
The output registers (PRESS_OUT_H (2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL
(28h)) are updated with the actual pressure value.
The RESET_ARP bit is used to disable the AUTORIFP function. RESET_ARP is self-
cleared.
AUTOZERO, when set to ‘1’, the actual pressure output value is copied in REF_P_H (17h),
REF_P_L (16h) and REF_P_XL (15h). When this bit is enabled, the register content of
REF_P is subtracted from the pressure output value. To disable autozero, the REF_P
registers have to be cleared.
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Register description
LPS22HB
The RESET_AZ bit is used to reset the AutoZero function. Resetting REF_P_H (17h),
REF_P_L (16h) and REF_P_XL (15h) sets the pressure reference registers RPDS_H (19h)
and RPDS_L (18h) to the default values. RESET_AZ is self-cleared.
The DIFF_EN bit is used to enable the computing of differential pressure output. It is
recommended to enable DIFF_EN after the configuration of REF_P_H (17h), REF_P_L
(16h), REF_P_XL (15h), THS_P_H (0Dh) and THS_P_L (0Ch).
8.2
THS_P_L (0Ch)
Least significant bits of the threshold value for pressure interrupt generation.
7
6
5
4
3
2
1
0
THS7
THS6
THS5
THS4
THS3
THS2
THS1
THS0
This register contains the low part of threshold value for pressure interrupt genera-
tion.
THS[7:0]
The threshold value for pressure interrupt generation is a 16-bit register composed of
THS_P_H (0Dh) and THS_P_L (0Ch). The value is expressed as unsigned number: Interrupt
threshold(hPA) = (THS_P)/16.
8.3
THS_P_H (0Dh)
Most significant bits of the threshold value for pressure interrupt generation.
7
6
5
4
3
2
1
0
THS15
THS14
THS13
THS12
THS11
THS10
THS9
THS8
This register contains the high part of threshold value for pressure interrupt genera-
tion. Refer to THS_P_L (0Ch).
THS[15:8]
8.4
8.5
WHO_AM_I
Device Who am I
7
1
6
0
5
1
4
1
3
0
2
0
1
0
0
1
CTRL_REG1 (10h)
Control register 1
7
6
5
4
3
2
1
0
0(1)
ODR2
ODR1
ODR0
EN_LPFP
LPF_CFG
BDU
SIM
1. This bit must be set to ‘0’ for proper operation of the device
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Register description
ODR [2:0]
EN_LPFP
LPF_CFG
BDU
Output data rate selection. Default value: 000
Refer to Table 16.
Enable low-pass filter on pressure data. Default value: 0
(0: Low-pass filter disabled; 1: Low-pass filter enabled)
LPF_CFG: Low-pass configuration register. Default value:0
Refer to Table 17.
Block data update. Default value: 0
(0: continuous update;
1: output registers not updated until MSB and LSB have been read)
SIM
SPI Serial Interface Mode selection.Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
Table 16. Output data rate bit configurations
ODR2
ODR1
ODR0
Pressure (Hz)
Temperature (Hz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
One shot mode enabled
1
Hz
1 Hz
10 Hz
25 Hz
50 Hz
75 Hz
10 Hz
25 Hz
50 Hz
75 Hz
When ODR[2,0] are set to ‘000’ the device enables One-Shot Mode. When the
ONE_SHOT bit in CTRL_REG2 (11h) is set to ‘1’, a new set of data for pressure and
temperature is acquired.
Table 17. Low-pass filter configurations
LPF_CFG
FIlter cutoff
0
1
ODR/9
ODR/20
The BDU bit is used to inhibit the update of the output registers between the reading of upper
and lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are
updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output
registers is not updated until both MSB and LSB are read, avoiding the reading of values
related to different samples.
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Register description
LPS22HB
8.6
CTRL_REG2 (11h)
Control register 2
7
6
5
4
3
2
1
0
0(1)
BOOT
FIFO_EN
STOP_ON_FTH
IF_ADD_INC
I2C_DIS
SWRESET
ONE_SHOT
1. This bit must be set to ‘0’ for proper operation of the device
BOOT
Reboot memory content. Default value: 0.
(0: normal mode; 1: reboot memory content). The bit is self-cleared when the BOOT
is completed.
FIFO_EN
FIFO enable. Default value: 0.
(0: disable; 1: enable)
STOP_ON_FTH Stop on FIFO threshold. Enable FIFO watermark level use. Default value 0
(0: disable; 1: enable)
IF_ADD_INC
Register address automatically incremented during a multiple byte access with a
serial interface (I2C or SPI). Default value 1.
(0: disable; 1 enable)
I2C_DIS
Disable I2C interface. Default value 0.
(0: I2C enabled;1: I2C disabled)
SWRESET
Software reset. Default value: 0.
(0: normal mode; 1: software reset).
The bit is self-cleared when the reset is completed.
ONE_SHOT
One-shot enable. Default value: 0.
(0: idle mode; 1: a new dataset is acquired)
The BOOT bit is used to refresh the content of the internal registers stored in the Flash
memory block. At device power-up the content of the Flash memory block is transferred to
the internal registers related to the trimming functions to allow correct behavior of the device
itself. If for any reason the content of the trimming registers is modified, it is sufficient to use
this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the
internal Flash is copied inside the corresponding internal registers and is used to calibrate
the device. These values are factory trimmed and they are different for every device. They
allow correct behavior of the device and normally they should not be changed. At the end of
the boot process the BOOT bit is set again to ‘0’ by hardware. The BOOT bit takes effect
after one ODR clock cycle.
SWRESET is the software reset bit. The device is reset to the power-on configuration if the
SWRESET bit is set to ‘1’ and BOOT is set to ‘1’.
The ONE_SHOT bit is used to start a new conversion when the ODR[2,0] bits in
CTRL_REG1 (10h) are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single
measurement of pressure and temperature. Once the measurement is done, the
ONE_SHOT bit will self-clear, the new data are available in the output registers, and the
STATUS_REG bits are updated.
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Register description
8.7
CTRL_REG3 (12h)
Control register 3 - INT_DRDY pin control register
7
6
5
4
3
2
1
0
INT_H_L
PP_OD
F_FSS5
F_FTH
F_OVR
DRDY
INT_S2
INT_S1
INT_H_L
PP_OD
F_FSS5
F_FTH
Interrupt active-high/low. Default value: 0.
(0: active high; 1: active low)
Push-pull/open drain selection on interrupt pads. Default value: 0.
(0: push-pull; 1: open drain)
FIFO full flag on INT_DRDY pin. Default value: 0.
(0: Disable; 1: Enable)
FIFO threshold (Watermark) status on INT_DRDY pin. Default value: 0.
(0: Disable; 1: Enable)
F_OVR
DRDY
FIFO overrun interrupt on INT_DRDY pin. Default value: 0.
(0: Disable; 1: Enable)
Data-ready signal on INT_DRDY pin. Default value: 0.
(0: Disable; 1: Enable)
INT_S[2:1]
Data signal on INT_DRDY pin control bits. Default value: 00.
Refer to Table 18.
Table 18. Interrupt configurations
INT_S2
INT_S1
INT_DRDY pin configuration
Data signal (in order of priority: PTH_DRDY or F_FTH or
F_OVR or F_FSSS5
0
0
0
1
1
1
0
1
Pressure high (P_high)
Pressure low (P_low)
Pressure low OR high
8.8
FIFO_CTRL (14h)
FIFO control register
7
6
5
4
3
2
1
0
F_MODE2
F_MODE1
F_MODE0
WTM4
WTM3
WTM2
WTM1
WTM0
F_MODE[2:0] FIFO mode selection. Default value: 000.
Refer to Table 19 and Section 4 for additional details.
WTM[4:0]
FIFO watermark level selection.
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Register description
LPS22HB
Table 19. FIFO mode selection
F_MODE2 F_MODE1 F_MODE0
FIFO mode selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bypass mode
FIFO mode
Stream mode
Stream-to-FIFO mode
Bypass-to-Stream mode
Reserved
Reserved
Bypass-to-FIFO mode
8.9
REF_P_XL (15h)
Reference pressure (LSB data)
7
6
5
4
3
2
1
0
REFL7
REFL6
REFL5
REFL4
REFL3
REFL2
REFL1
REFL0
REFL[7:0]
This register contains the low part of the reference pressure value.
The Reference pressure value is a 24-bit data added to the sensor output measurement and
it is composed of REF_P_H (17h), REF_P_L (16h) and REF_P_XL (15h). The value is
expressed as 2’s complement.
The reference pressure value is added to the sensor output measurement, to detect a
measured pressure beyond programmed limits (refer to the CTRL_REG3 (12h) register)
and for the Autozero function (refer to the INTERRUPT_CFG (0Bh) register).
8.10
REF_P_L (16h)
Reference pressure (middle part)
7
6
5
4
3
2
1
0
REFL15
REFL14
REFL13
REFL12
REFL11
REFL10
REFL9
REFL8
REFL[15:8]
This register contains the mid part of the reference pressure value.
Refer to REF_P_XL (15h).
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Register description
8.11
REF_P_H (17h)
Reference pressure (MSB part)
7
6
5
4
3
2
1
0
REFL23
REFL22
REFL21
REFL20
REFL19
REFL18
REFL17
REFL16
REFL[23:16] This register contains the high part of the reference pressure value.
Refer to REF_P_XL (15h).
8.12
RPDS_L (18h)
Pressure offset (LSB data)
7
6
5
4
3
2
1
0
RPDS7
RPDS6
RPDS5
RPDS4
RPDS3
RPDS2
RPDS1
RPDS0
RPDS[7:0]
This register contains the low part of the pressure offset value.
The pressure offset value is a 16-bit data that can be used to implement the one-point
calibration (OPC) after soldering, This value is composed of RPDS_H (19h) and RPDS_L
(18h). The value is expressed as 2’s complement.
8.13
RPDS_H (19h)
Pressure offset (MSB data)
7
6
5
4
3
2
1
0
RPDS15
RPDS14
RPDS13
RPDS12
RPDS11
RPDS10
RPDS9
RPDS8
RPDS[15:8]
This register contains the high part of the pressure offset value.
Refer to RPDS_L (18h).
8.14
RES_CONF (1Ah)
Low-power mode configuration
7
6
5
4
3
2
1
0
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
reserved(2)
LC_EN
1. These bits must be set to ‘0’ for proper operation of the device.
2. The content of this bit must not be modified for proper operation of the device
LC_EN
Low current mode enable. Default 0.
0: Normal mode (low-noise mode); 1: Low-current mode).
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Register description
LPS22HB
8.15
INT_SOURCE (25h)
Interrupt source
7
6
0
5
0
4
0
3
0
2
1
0
BOOT_STATUS
IA
PL
PH
BOOT_STATUS If ‘1’ indicates that the Boot (Reboot) phase is running.
IA
Interrupt active.
(0: no interrupt has been generated;
1: one or more interrupt events have been generated).
PL
PH
Differential pressure Low.
(0: no interrupt has been generated;
1: Low differential pressure event has occurred).
Differential pressure High.
(0: no interrupt has been generated;
1: High differential pressure event has occurred).
8.16
FIFO_STATUS (26h)
FIFO status
7
6
5
4
3
2
1
0
FTH_FIFO
OVR
FSS5
FSS4
FSS3
FSS2
FSS1
FSS0
FTH_FIFO
OVR
FIFO threshold status.
(0: FIFO filling is lower than FTH level,
1: FIFO filling is equal or higher than FTH level).
Overrun bit status.
(0: FIFO not full;
1: FIFO is full and at least one sample in the FIFO has been overwritten).
FSS[5:0]
FIFO stored data level.
(000000: FIFO empty, 100000: FIFO is full and has 32 unread samples).
8.17
STATUS (27h)
Status register
7
6
5
4
3
2
1
0
--
--
T_OR
P_OR
--
--
T_DA
P_DA
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Register description
T_OR
P_OR
T_DA
P_DA
Temperature data overrun.
(0: no overrun has occurred;
1: a new data for temperature has overwritten the previous one)
Pressure data overrun.
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous one)
Temperature data available.
(0: new data for temperature is not yet available;
1: new data for temperature is available)
Pressure data available.
(0: new data for pressure is not yet available;
1: new data for pressure is available)
This register is updated every ODR cycle.
T_OR is set to ‘1’ when a new temperature data is generated before the previous one has
been read.
P_OR is set to ‘1’ when a new pressure data is generated before the previous one has been
read.
8.18
PRESS_OUT_XL (28h)
Pressure output value (LSB)
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
POUT[7:0]
This register contains the low part of the pressure output value.
The pressure output value is a 24-bit data that contains the measured pressure. It is
composed of PRESS_OUT_H (2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL (28h).
The value is expressed as 2’s complement.
8.19
PRESS_OUT_L (29h)
Pressure output value (mid part)
7
6
5
4
3
2
1
0
POUT15
POUT14
POUT13
POUT12
POUT11
POUT10
POUT9
POUT8
POUT[15:8]
This register contains the mid part of the pressure output value.
Refer to PRESS_OUT_XL (28h).
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Register description
LPS22HB
8.20
PRESS_OUT_H (2Ah)
Pressure output value (MSB)
7
6
5
4
3
2
1
0
POUT23
POUT22
POUT21
POUT20
POUT19
POUT18
POUT17
POUT16
POUT[23:16] This register contains the low part of the pressure output value.
Refer to PRESS_OUT_XL (28h).
8.21
TEMP_OUT_L (2Bh)
Temperature output value (LSB)
7
6
5
4
3
2
1
0
TOUT7
TOUT6
TOUT5
TOUT4
TOUT3
TOUT2
TOUT1
TOUT0
TOUT[7:0]
This register contains the low part of the temperature output value.
The temperature output value is a 16-bit data that contains the measured temperature. It is
composed of TEMP_OUT_H (2Ch), and TEMP_OUT_L (2Bh). The value is expressed as
2’s complement.
8.22
TEMP_OUT_H (2Ch)
Temperature output value (MSB)
7
6
5
4
3
2
1
0
TOUT15
TOUT14
TOUT13
TOUT12
TOUT11
TOUT10
TOUT9
TOUT8
TOUT[15:8]
This register contains the high part of the temperature output value.
The temperature output value is a 24-bit data that contains the measured temperature. It is
composed of PRESS_OUT_H (2Ah), and PRESS_OUT_XL (28h). The value is expressed
as 2’s complement.
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Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 12. HLGA - 10L (2.0 x 2.0 x 0.76 mm typ.) outline and mechanical data
8577439
Dimensions are in millimeter unless otherwise specified
OUTER DIMENSIONS
ITEM
DIMENSION [mm]
TOLERANCE [mm]
Length [L]
Width [W]
Height [H]
Land size
Pitch X
2
0.1
0.1
2
0.8 max
0.25 x 0.275
0.5
/
0.05
0.05
0.05
0.05
Pitch Y
Pad Inset
1
0.10
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Revision history
LPS22HB
10
Revision history
Table 20. Document revision history
Date
Revision
Changes
29-Oct-2014
1
Initial release.
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