M2201VM6TR [STMICROELECTRONICS]
128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8;
| 型号： | M2201VM6TR |
| 厂家： | 
ST |
| 描述： | 128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M2201
2-Wires 1 Kbit (x8) Serial EEPROM
TWO WIRE SERIAL INTERFACE
100.000 ERASE/WRITECYCLES with
100 YEARS DATA RETENTION at 55°C
SINGLE SUPPLYVOLTAGE:
– 4.5V to 5.5V for M2201 version
– 2.7V to 5.5V for M2201V version
HARDWARE WRITE CONTROL
100 KBIT TRANSFER RATE
8
8
1
1
PSDIP8 (B)
0.25mm Frame
SO8 (M)
150mil Width
BYTE WRITE
PAGE WRITE (up to 4 BYTES)
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
8
DESCRIPTION
1
TheM2201 is a simplified2-wire bus 1 Kbitelectri-
cally erasableprogrammable memory(EEPROM),
organized as 128 x8 bits. It is manufactured in
STMicroelectronics’s Hi-Endurance Advanced
CMOS technologywhich guaranteesa data reten-
tion of 100 years at 55°C.
TSSOP8 (DW)
169 mil width
The M2201 is available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages.
Figure 1. Logic Diagram
The memory is compatible with a two wire serial
interface which uses a bi-directional data bus and
serial clock. Read and write operations are initi-
ated by a START condition generated by the bus
master and ended by a STOP condition.
V
CC
Address bits and RW bit are defined in one single
byte,insteadof two(orthree)bytesforthestandard
I2C protocol.
SCL
WC
SDA
M2201
Table 1. Signal Names
SDA
SCL
WC
VCC
VSS
Serial Data Input/Output
Serial Clock
Write Control
Supply Voltage
Ground
V
SS
AI01321
July 1999
1/15
M2201
Figure 2A. DIP Pin Connections
Figure 2B. SO and TSSOP Pin Connections
M2201
M2201
NC
NC
NC
1
2
3
4
8
V
NC
NC
NC
1
2
3
4
8
V
CC
WC
CC
7
6
WC
7
6
SCL
SDA
SCL
SDA
V
SS
5
V
5
SS
AI01322
AI01323
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
Ambient Operating Temperature
Storage Temperature
–40 to 85
C
°
TSTG
–65 to 150
°C
TLEAD
Lead Temperature,Soldering
(SO8 package)
(PSDIP8 package)
(TSSOP8 package)
40 sec
10 sec
t.b.c.
215
260
t.b.c.
°C
VO
VI
Output Voltage
Input Voltage
Supply Voltage
–0.6 to 6.5
–0.6 to 6.5
–0.3 to 6.5
4000
V
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
VESD
500
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratingsonly and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operationsare disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Whenwritingdata to thememory,it respondstothe
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master,it acknowledgesthe receipt ofthe data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
2/15
M2201
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
synchronize all data in and out of the memory. A
resistorcan be connectedfrom the SCLlineto VCC
to act as a pull up (see Figure 3).
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. ASTART conditionmust
precede any command for data transfer. Except
during a programming cycle, the M2201 continu-
ously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
The SCL input pin is used to
Serial Data (SDA).
The SDA pin is bi-directional
andis usedtotransferdata in or outof thememory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
thebus. AresistormustbeconnectedfromtheSDA
bus line to VCC to act as pull up (see Figure 3).
StopCondition. STOPis identifiedby alowtohigh
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the M2201 and the
busmaster. ASTOPconditionatthe endof a Read
commandforcesthe standby state. ASTOPcondi-
tion at the end of a Write command triggers the
internal EEPROMwrite cycle.
Write Control (WC). An hardware Write Control
feature (WC) is offered on pin 7. This feature is
usefull to protect the contents of the memory from
anyerroneouserase/writecycle. TheWriteControl
signal is used to enable(WC = VIH) or disable (WC
= VIL) the internal write protection. When uncon-
nected,the WC input is internally read as VIL (WC
is disabled).
Acknowledge Bit (ACK).
An acknowledgesignal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
theSDAbus aftersending8 bitsof data.During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledgethe receipt of the 8 bits of
data.
DEVICE OPERATION
Data Input. During data input the M2201 sample
the SDA bus signal on the rising edge of the clock
SCL.Notethatfor correctdeviceoperationtheSDA
signal must be stable during the clock low to high
transition and the data must change ONLY when
the SCL line is low.
Thedevice that controls the data transferis known
asthe master.Themasterwillalwaysinitiatea data
transfer and will provide the serial clock for syn-
chronisation. The M2201 is always a slave device
in all communications.
Figure 3. MaximumRL Value versus Bus Capacitance (CBUS
)
20
V
CC
16
12
8
R
R
L
L
SDA
SCL
C
BUS
MASTER
C
BUS
4
0
V
= 5V
CC
100
200
(pF)
300
400
C
AI01100
BUS
3/15
M2201
Table 3. Input Parameters (TA = 25 °C, f = 100 kHz )
Symbol
CIN
Parameter
Input Capacitance (SDA)
Test Condition
Min
Max
8
Unit
pF
CIN
Input Capacitance (other pins)
WC Input Impedance
6
pF
(1)
ZWCL
VIN 0.3 V
5
20
k
Ω
≤
CC
(1)
ZWCH
WC Input Impedance
V
IN ≥ 0.7 VCC
500
kΩ
Low-pass filter input time constant
(SDA and SCL)
(1)
tLP
100
ns
Note: 1. The results come from simulation, actual results may vary. These figures are not guaranteed.
Table 4. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.7V to 5.5V)
Symbol
Parameter
Test Condition
0V
Min
Max
Unit
Input Leakage Current
(SCL, SDA)
ILI
V
IN
V
CC
2
2
A
A
≤
≤
±
µ
µ
0V
V
V
≤
CC
≤
OUT
ILO
Output Leakage Current
±
SDA in Hi-Z
VCC = 5V; fC = 100kHz
(Rise/Fall time < 30ns)
Supply Current (M2201)
Supply Current (M2201V)
2
mA
mA
µA
ICC
VCC = 2.7V; fC = 100kHz
1
V
IN = VSS or VCC
VCC = 5V
,
100
Supply Current (Standby)
(M2201)
ICC1
VIN = VSS or VCC
CC = 5V, fC = 100kHz
,
300
5
A
A
A
µ
µ
µ
V
VIN = VSS or VCC
CC = 2.7V
,
V
Supply Current (Standby)
(M2201V)
ICC2
V
IN = VSS or VCC
,
50
VCC = 2.7V; fC = 100kHz
VIL
VIH
VIL
VIH
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage (WC)
–0.3
0.7 VCC
–0.3
0.3 VCC
VCC + 1
0.5
V
V
V
V
V
V
Input High Voltage (WC)
VCC – 0.5
VCC + 1
0.4
Output Low Voltage (M2201)
Output Low Voltage (M2201V)
IOL = 3mA, VCC = 5V
IOL = 2mA, VCC = 2.7V
VOL
0.4
4/15
M2201
Table 5. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.7V to 5.5V)
Symbol
tCH1CH2
tCL1CL2
tDH1DH2
tDL1DL1
Alt
tR
Parameter
Min
Max
1
Unit
Clock Rise Time
Clock Fall Time
Input Rise Time
Input Fall Time
s
µ
tF
300
1
ns
tR
s
µ
tF
300
ns
(1)
tCHDX
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
tSU:DAT
tSU:STO
tBUF
tAA
Clock High to Input Transition
Clock Pulse Width High
4.7
4
s
s
s
s
s
µ
µ
µ
µ
µ
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
4
0
4.7
250
4.7
4.7
0.3
300
Input Transitionto Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
ns
s
s
s
µ
µ
µ
(2)
tCLQV
3.5
tCLQX
fC
tDH
ns
kHz
ms
fSCL
tWR
Clock Frequency
100
10
tW
Write Time
Notes: 1. For a reSTARTcondition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted STARTand/or STOP
conditions.
Table 6. AC MeasurementConditions
MemoryAddressing.
Tostart communication be-
tween the bus master and the slave M2201, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the 7th bit byte-ad-
dressand a READor WRITE bit. This 8th bit is set
to’1’for read and ’0’ for write operations.If a match
is found, the corresponding memory will acknow-
ledge the identificationon the SDA bus during the
9th bit time.
Input Rise and Fall Times
Input Pulse Voltages
50ns
≤
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and Output Timing Ref.
Voltages
Figure 4. AC Testing Input Output Waveforms
Write Operations
Followinga STARTconditionthe master sends the
byte address with the RW bit reset to ’0’. The
memory acknowledges this and waits for a data
byte. Any write command with WC = 1 (during a
period of time from the START condition until the
end of the Byte Address) will not modify data and
will NOT be acknowledged on data bytes, as in
Figure 8.
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825
5/15
M2201
Figure 5. AC Waveforms
tCHCL
tDLCL
tCLCH
SCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795B
6/15
M2201
Byte Write.
In the Byte Write mode the master
dress counter ’roll-over’ which could result in data
being overwritten.
It must be noticed that, for any write mode, the
generation by the master of the STOP condition
startsthe internalmemoryprogramcycle. Allinputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
Minimizing System Delays by Polling On ACK.
During the internalwrite cycle, thememory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
sendsone databyte,whichis acknowledgedbythe
memory. The master then terminates the transfer
by generatinga STOPcondition.
Page Write. The Page Write mode allows up to 4
bytes to be written in a singlewrite cycle, provided
that they are all located in the same ’row’ in the
memory: that is the 5 most significant memory
address bits (A6-A2) are the same. The master
sends from one up to fourbytes of data, which are
each acknowledged by the memory. After each
byteis transfered,the internalbyteaddresscounter
(2 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad-
Figure 6. I2C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
7/15
M2201
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond withan ACK, indicating that the mem-
ory is ready to receive the second part of the
next instruction (the first byte of this instruc-
tion was already sent during Step 1).
DEVICE OPERATION
(cont’d)
duced by an ACK polling sequence issued by the
master. The sequenceis as follows:
– Initial condition: a Write is in progress (see Fig-
ure 7).
– Step 1: the Master issues a STARTcondition
followed by a Device Select byte (1st byte of
the new instruction).
Figure 7. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
Byte Address
with RW = 0
ACK
Returned
NO
YES
Next
Operation is
WRITE
NO
YES
Send
DATA BYTE
ReSTART
STOP
STOP
AI01049
8/15
M2201
Read Operation
terminated by a STOP condition issued by the
master (instead of the ACK bit). The output data is
from consecutivebyte addresses, with the internal
byte address counter automatically incremented
after each byte output. After a count of the last
memory address, the address counter will ’roll-
over to address ’00’ and the memory will continue
to output data.
Byte Read. The master sends a START condition
followed by seven bits of address and the RW bit
(setto’1’). TheM2201acknowledgesitand outputs
the corresponding data byte. The read operation
is terminated by a STOP condition issued by the
master (instead of the ACK bit).
Sequential Read. The master sends a START
conditionfollowed byseven bitsof addressand the
RW bit(set to ’1’). The M2201acknowledgesit and
outputs the corresponding data byte. The master
does acknowledge this byte and reads the next
data byte (at address + 1). The read operation is
Acknowledge in Read Mode. In all read modes
theM2201waitsfor anacknowledgeduringthe 9th
bittime.If themasterdoes notpull the SDAline low
during this time, the M2201 terminates the data
transfer and switches to a standby state.
Figure 8. Write Modes Sequences with Write Control = 1 (M2201 and M2201V)
WC
ACK
NO ACK
DATA IN
BYTE WRITE
BYTEADDR
R/W = 0
WC
ACK
NO ACK
DATA IN 1
NO ACK
NO ACK
PAGE WRITE
BYTEADDR
DATA IN 4
R/W = 0
AI01324
9/15
M2201
Figure 9. Write Modes Sequences (M2201 and M2201V)
ACK
ACK
ACK
BYTE WRITE
Byte-Address
Data-In
R/W=0
ACK
ACK
PAGE WRITE
Byte-Address
Data-In1
Data-In 2
Data-In 3
R/W=0
ACK
ACK
Data-In N
AI03128
Figure 10. Read Modes Sequences
ACK
NO ACK
BYTE READ
BYTEADDR
DATA OUT
R/W = 1
ACK
ACK
DATA OUT 1
ACK
NO ACK
SEQUENTIAL READ
BYTEADDR
DATA OUT N
R/W = 1
AI01325
10/15
M2201
ORDERING INFORMATION SCHEME
Example:
M2201
V
M
1
TR
Operating Voltage
Package
Temperature Range
Option
blank 4.5V to 5.5V
B
PSDIP8
0.25mm Frame
1
6
0 to 70 °C
–40 to 85 C
TR Tape & Reel
Packing
V
2.7V to 5.5V
°
M
SO8
150mil Width
DW
TSSOP8
169mil width
Devices are shipped from the factory with the memory content set at all ”1’s” (FFh).
For a list of availableoptions (OperatingVoltage,Package, etc...)or for further information please contact
the STMicroelectronics Sales Office nearest to you.
11/15
M2201
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min
Symb
Typ
Max
5.90
–
Typ
Max
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale.
12/15
M2201
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
0.069
0.010
0.020
0.010
0.197
0.157
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
6.20
0.50
0.90
0.228
0.010
0.016
0.244
0.020
0.035
L
0
°
8
°
0
°
8
°
α
N
CP
8
8
0.10
0.004
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale.
13/15
M2201
TSSOP8 - 8 lead Plastic Thin Shrink Small Outline, 169 mils body width
mm
Min
inches
Min
Symb
Typ
Max
1.10
0.15
0.95
0.30
0.20
3.10
6.50
4.50
–
Typ
Max
0.043
0.006
0.037
0.012
0.008
0.122
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
2.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.114
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0.70
0.020
0.028
0
°
8
°
0
°
8
°
α
N
8
8
CP
0.08
0.003
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Drawing is not to scale.
14/15
M2201
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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15/15
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