M24128-WMN6T [STMICROELECTRONICS]
256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines; 一百二十八分之二百五十六千位串行IC总线EEPROM没有芯片使能线
| 型号： | M24128-WMN6T |
| 厂家： | 
ST |
| 描述： | 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines |
| 文件： | 总17页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24256
M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
2
■ Compatible with I C Extended Addressing
2
■ Two Wire I C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24xxx
8
– 2.5V to 5.5V for M24xxx-W
■ Hardware Write Control
1
■ BYTE and PAGE WRITE (up to 64 Bytes)
PDIP8 (BN)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
0.25 mm frame
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ More than 100,000 Erase/Write Cycles
■ More than 40 Year Data Retention
8
8
1
1
SO8 (MN)
150 mil width
SO8 (MW)
200 mil width
DESCRIPTION
2
These I C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
Figure 1. Logic Diagram
The M24256B, M24128B and M24256A are also
available, and offer the extra functionality of the
chip enable inputs. Please see the separate data
sheets for details of these products.
V
CC
The M24256 and M24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
2
I C extended memory standard. This is a two wire
SCL
WC
SDA
M24256
M24128
Table 1. Signal Names
SDA
Serial Data/Address Input/
Output
SCL
WC
Serial Clock
Write Control
Supply Voltage
Ground
V
SS
AI01882
V
V
CC
SS
June 2001
1/17
M24256, M24128
Figure 2B. SO Connections
Figure 2A. DIP Connections
M24256
M24128
M24256
M24128
NC
NC
NC
1
2
3
4
8
V
CC
WC
NC
NC
NC
1
2
3
4
8
V
CC
WC
7
6
7
6
SCL
SDA
SCL
SDA
V
5
SS
V
5
SS
AI01883
AI01884
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
2
accordance with the I C bus definition.
2
The memory behaves as a slave device in the I C
held active until the V
voltage has reached the
CC
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when V drops from the
CC
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
When writing data to the memory, the memory in-
th
serts an acknowledge bit during the 9 bit time,
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
1
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature
Value
Unit
°C
–40 to 125
–65 to 150
TSTG
Storage Temperature
°C
PDIP: 10 seconds
260
235
TLEAD
Lead Temperature during Soldering
°C
2
SO: 20 seconds (max)
VIO
VCC
Input or Output range
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
4000
V
V
V
3
VESD
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
2/17
M24256, M24128
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
the SCL line to V . (Figure 3 indicates how the
CC
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Start Condition
Serial Data (SDA)
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V . (Figure 3 indicates how the value of the
CC
pull-up resistor can be calculated).
Stop Condition
Write Control (WC)
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V ) or disable (WC=V )
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
IL
IH
V , and write operations are allowed.
IL
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
th
sending eight bits of data. During the 9 clock
DEVICE OPERATION
The memory device supports the I C protocol.
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
2
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
2
Figure 3. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/17
M24256, M24128
2
Figure 4. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, 0, 0).
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Memory Addressing
th
The 8 bit is the RW bit. This is set to ‘1’ for read
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
th
ing the 9 bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
1
Table 3. Device Select Code
Device Type Identifier
Chip Enable
RW
b0
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
0
Device Select Code
RW
Note: 1. The most significant bit, b7, is sent first.
4/17
M24256, M24128
Table 4. Operating Modes
Mode
1
RW bit
Data Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = ‘1’
X
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 64
START, Device Select, RW = ‘0’
Note: 1. X = VIH or VIL.
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120C
5/17
M24256, M24128
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106B
Table 5. Most Significant Byte
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
b15
b14
b13 b12
b11 b10 b9
b8
Note: 1. b15 is treated as Don’t Care on the M24256 series.
b15 and b14 are Don’t Care on the M24128 series.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Table 6. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for two address bytes. The memory re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256 and b13-b6 for the
M24128) are the same. If more bytes are sent than
6/17
M24256, M24128
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become over-
written (in a way not formally specified in this data
sheet).
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t ) is shown in Table 10, but the
w
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10 bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
th
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
7/17
M24256, M24128
Figure 8. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
Read Operations
Current Address Read
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
internal address counter. The counter is then in-
8/17
M24256, M24128
Table 7. DC Characteristics
(T = –40 to 85 °C; V = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
0 V ≤ VIN ≤ VCC
± 2
µA
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
± 2
2
µA
mA
mA
µA
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
ICC
Supply Current
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
-W series:
1
c
VIN = VSS or VCC , VCC = 5 V
10
2
Supply Current
(Stand-by)
ICC1
-W series:
V
IN = VSS or VCC , VCC = 2.5 V
µA
Input Low Voltage
(SCL, SDA)
VIL
VIH
0.3VCC
VCC+1
–0.3
V
V
Input High Voltage
(SCL, SDA)
0.7VCC
VIL
VIH
Input Low Voltage (WC)
Input High Voltage (WC)
–0.3
0.5
VCC+1
0.4
V
V
V
V
0.7VCC
I
OL = 3 mA, VCC = 5 V
Output Low
Voltage
VOL
I
OL = 2.1 mA, VCC = 2.5 V
-W series:
0.4
1
Table 8. Input Parameters (T = 25 °C, f = 400 kHz)
A
Symbol
CIN
Parameter
Test Condition
Min.
Max.
Unit
Input Capacitance (SDA)
Input Capacitance (other pins)
Input Impedance (WC)
Input Impedance (WC)
8
6
pF
pF
kΩ
kΩ
CIN
Z
V
IN ≤ 0.5 V
5
L
Z
V
IN ≥ 0.7VCC
500
H
Low Pass Filter Input Time
Constant (SCL and SDA)
tNS
100
ns
Note: 1. Sampled only, not 100% tested.
Table 9. AC Measurement Conditions
Figure 9. AC Testing Input Output Waveforms
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.2V to 0.8V
0.8V
CC
0.7V
CC
CC
CC
CC
0.3V
CC
0.2V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
CC
AI00825
9/17
M24256, M24128
Table 10. AC Characteristics
M24256 / M24128
=4.5 to 5.5 V =2.5 to 5.5 V
V
V
CC
CC
Symbol
Alt.
Parameter
Unit
T =–40 to 85°C
T =–40 to 85°C
A
A
Min
Max
300
300
300
300
Min
Max
300
300
300
300
tCH1CH2
tCL1CL2
tR
tF
tR
tF
Clock Rise Time
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
kHz
ms
Clock Fall Time
SDA Rise Time
SDA Fall Time
2
20
20
20
20
tDH1DH2
2
tDL1DL2
1
tSU:STA Clock High to Input Transition
600
600
600
0
600
600
600
0
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
tHIGH
Clock Pulse Width High
tHD:STA
Input Low to Clock Low (START)
tHD:DAT Clock Low to Input Transition
tLOW Clock Pulse Width Low
1.3
100
600
1.3
200
200
1.3
100
600
1.3
200
200
tSU:DAT Input Transition to Clock Transition
tSU:STO Clock High to Input High (STOP)
tBUF
tAA
Input High to Input Low (Bus Free)
Clock Low to Data Out Valid
Data Out Hold Time After Clock Low
Clock Frequency
3
900
900
tCLQV
tCLQX
fC
tDH
fSCL
tWR
400
10
400
10
tW
Write Time
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
10/17
M24256, M24128
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
11/17
M24256, M24128
Table 11. Ordering Information Scheme
Example:
M24256
–
W
MN
1
T
Memory Capacity
Option
256
128
256 Kbit (32K x 8)
128 Kbit (16K x 8)
T
Tape and Reel Packing
Temperature Range
–40 °C to 85 °C
6
5
–20 °C to 85 °C
Operating Voltage
4.5 V to 5.5 V
1
Package
blank
W
2.5 V to 5.5 V
BN PDIP8 (0.25 mm frame)
2
SO8 (150 mil width)
SO8 (200 mil width)
MN
3
MW
Note: 1. Available only on request.
2. Available for M24128 only.
3. Available for M24256 only.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
12/17
M24256, M24128
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
E
b2
A2
A
L
A1
c
b
e
eA
eB
D
8
1
E1
PDIP-8
Note: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
mm
inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
10.16
8.26
7.11
–
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
13/17
M24256, M24128
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
C
A
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
14/17
M24256, M24128
SO8 wide – 8 lead Plastic Small Outline, 200 mils body width
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
SO8 wide – 8 lead Plastic Small Outline, 200 mils body width
mm
inches
Symb.
Typ.
Min.
Max.
2.03
0.25
1.78
0.45
–
Typ.
Min.
Max.
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
1.27
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
15/17
M24256, M24128
Table 12. Revision History
Date
Rev.
Description of Revision
References added to the M24256B and M24128B products
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
30-Mar-2001
01-Jun-2001
2.2
2.3
Document promoted from “Preliminary Data” to “Full Data Sheet”
16/17
M24256, M24128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 2001 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
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17/17
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