M24512-WLA5G [STMICROELECTRONICS]
64KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LGA-8;
| 型号： | M24512-WLA5G |
| 厂家： | 
ST |
| 描述： | 64KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, LGA-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总24页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24512
512 Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
2
■ Two Wire I C Serial Interface
Figure 1. Packages
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24512
– 2.5V to 5.5V for M24512-W
– 1.8V to 3.6V for M24512-S
■ Write Control Input
8
■ BYTE and PAGE WRITE (up to 128 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ More than 100,000 Erase/Write Cycles
■ More than 40 Year Data Retention
1
PDIP8 (BN)
8
1
SO8 (MW)
200 mil width
LGA
LGA8 (LA)
October 2003
1/24
M24512
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and LGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus. . . . . . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=0 (data write enabled). . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/24
M24512
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Operating Conditions (M24512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Operating Conditions (M24512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M24512-S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. DC Characteristics (M24512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. DC Characteristics (M24512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. DC Characteristics (M24512-S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 19
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . . 19
Figure 13. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline . . . . . 20
Table 17. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
20
Figure 14. LGA8 - 8 lead Land Grid Array, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 18. LGA8 - 8 lead Land Grid Array, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 23
3/24
M24512
SUMMARY DESCRIPTION
2
These I C-compatible electrically erasable
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
programmable memory (EEPROM) devices are
organized as 64K x 8 bits.
When writing data to the memory, the device in-
th
serts an acknowledge bit during the 9 bit time,
Figure 2. Logic Diagram
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
V
CC
3
Power On Reset: V
Lock-Out Write Protect
CC
E0-E2
SCL
WC
SDA
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V has reached
the POR threshold value, and all operations are
M24512
CC
disabled – the device will not respond to any
command. In the same way, when V drops from
CC
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable and
V
SS
AI02275
valid V
must be applied before applying any
CC
logic signal.
Figure 3. DIP, SO and LGA Connections
Table 1. Signal Names
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
M24512
SCL
E0
E1
E2
1
2
3
4
8
V
CC
WC
WC
7
V
6
5
SCL
SDA
CC
V
SS
V
SS
AI04035B
2
I C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
2
(1010) in accordance with the I C bus definition.
The device behaves as a slave in the I C protocol,
Note: 1. See page 19 (onwards) for package dimensions, and how
to identify pin-1.
2
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
4/24
M24512
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to V
or V , to establish the Device Select
CC
SS
Code. When not connected (left floating), these in-
puts are read as Low (0,0,0).
Clock (SCL) to V . (Figure 4 indicates how the
CC
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
nected, the signal is internally read as V , and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
IL
rial Data (SDA) to V . (Figure 4 indicates how the
CC
value of the pull-up resistor can be calculated).
2
Figure 4. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
5/24
M24512
2
Figure 5. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
1
2
RW
Device Type Identifier
Chip Enable Address
b7
b6
0
b5
1
b4
0
b3
E2
b2
E1
b1
E0
b0
Device Select Code
1
RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3. Most Significant Byte
Table 4. Least Significant Byte
b15
b14
b13 b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
6/24
M24512
DEVICE OPERATION
2
The device supports the I C protocol. This is sum-
marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The M24512 device is always a
slave in all communication.
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Start Condition
Memory Addressing
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Up to eight memory devices can be connected on
2
a single I C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the de-
vice only responds if the Chip Enable Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is
Acknowledge Bit (ACK)
set to 1 for Read and 0 for Write operations.
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
th
on Serial Data (SDA) during the 9 bit time. If the
(SDA) after sending eight bits of data. During the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
th
9
clock pulse period, the receiver pulls Serial
Table 5. Operating Modes
Mode
1
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
Random Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 128
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
7/24
M24512
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120C
Write Operations
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 3) is sent first, followed by the Least Significant
Byte (Table 4). Bits b15 to b0 form the address of
the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10 bit” time
After the Stop condition, the delay t , and the suc-
W
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in Figure 7.
th
slot), either at the end of a Byte Write or a Page
8/24
M24512
Page Write
The bus master sends from 1 to 128 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 7 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
The Page Write mode allows up to 128 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits (b
-b7 for , and b15-b7 for M24512) are the same. If
more bytes are sent than will fit up to the end of the
row, a condition known as ‘roll-over’ occurs. This
should be avoided, as data starts to become over-
written in an implementation dependent way.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106C
9/24
M24512
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
Minimizing System Delays by Polling On ACK
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
The maximum Write time (t ) is shown in Table
w
15, but the typical time is shorter. To make use of
this, a polling sequence can be used by the bus
master.
The sequence, as shown in Figure 8, is:
– Initial condition: a Write cycle is in progress.
10/24
M24512
Figure 9. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
Read Operations
puts the contents of the addressed byte. The bus
master must not acknowledge the byte, and termi-
nates the transfer with a Stop condition.
Read operations are performed independently of
the state of the Write Control (WC) signal.
Current Address Read
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 9, without acknowledging the
byte.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 9) but without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and out-
11/24
M24512
Sequential Read
Acknowledge in Read Mode
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9.
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9 bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
th
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
12/24
M24512
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 6. Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature
Min.
–40
–65
Max.
125
Unit
°C
TSTG
Storage Temperature
150
°C
2
PDIP
SO
260
1
3
TLEAD
°C
Lead Temperature during Soldering
260
3
LGA
260
VIO
VCC
VESD
Input or Output range
Supply Voltage
–0.6
–0.3
6.5
6.5
V
V
V
4
–4000
4000
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with the ECOPACK 7191395 specifiication for lead-free soldering processes
2. No longer than 10 seconds
3. Not exceeding 250°C for more than 30 seconds, and peaking at 260°C
4. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
13/24
M24512
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 7. Operating Conditions (M24512)
Symbol
Parameter
Min.
4.5
Max.
5.5
85
Unit
V
V
CC
Supply Voltage
–40
–20
°C
°C
TA
Ambient Operating Temperature
85
Table 8. Operating Conditions (M24512-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
85
Unit
V
V
Supply Voltage
CC
–40
–20
°C
°C
TA
Ambient Operating Temperature
85
Table 9. Operating Conditions (M24512-S)
Symbol
Parameter
Min.
1.8
Max.
3.6
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–20
85
°C
Table 10. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
Input Levels
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Levels
V
CC
Figure 10. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
14/24
M24512
Table 11. Input Parameters
1,2
Symbol
CIN
Test Condition
Min.
Max.
Unit
pF
Parameter
Input Capacitance (SDA)
8
6
CIN
Input Capacitance (other pins)
pF
Input Impedance
(E2, E1, E0, WC)
ZL
ZH
tNS
VIN < 0.5 V
VIN > 0.7VCC
Single glitch
30
kΩ
kΩ
ns
Input Impedance
(E2, E1, E0, WC)
500
Pulse width ignored
(Input Filter on SCL and SDA)
100
Note: 1. T = 25 °C, f = 400 kHz
A
2. Sampled only, not 100% tested.
Table 12. DC Characteristics (M24512)
Test Condition
(in addition to those in Table 7)
Symbol
Parameter
Min.
Max.
Unit
V
IN = VSS or VCC
Input Leakage Current
(SCL, SDA)
ILI
± 2
µA
device in Stand-by mode
ILO
ICC
V
OUT = VSS or VCC, SDA in Hi-Z
Output Leakage Current
Supply Current
± 2
2
µA
mA
µA
V
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
ICC1
Stand-by Supply Current
Input Low Voltage (SCL, SDA)
VIN = VSS or VCC , VCC = 5 V
10
–0.45
–0.45
0.3VCC
VIL
Input Low Voltage
(E2, E1, E0, WC)
0.5
V
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
V
V
VOL
Output Low Voltage
IOL = 3 mA, VCC = 5 V
Table 13. DC Characteristics (M24512-W)
Test Condition
(in addition to those in Table 8)
Symbol
Parameter
Max.
Unit
Min.
V
IN = VSS or VCC
Input Leakage Current
(SCL, SDA)
ILI
± 2
µA
device in Stand-by mode
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
µA
mA
µA
V
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
1
2
c
ICC1
Stand-by Supply Current
Input Low Voltage (SCL, SDA)
VIN = VSS or VCC , VCC = 2.5 V
–0.45
–0.45
0.3VCC
VIL
Input Low Voltage
(E2, E1, E0, WC)
0.5
V
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
V
V
VOL
Output Low Voltage
IOL = 2.1 mA, VCC = 2.5 V
15/24
M24512
Table 14. DC Characteristics (M24512-S)
Test Condition
(in addition to those in Table 9)
Symbol
Parameter
Max.
Unit
Min.
Input Leakage Current
(SCL, SDA)
VIN = VSS or VCC
device in Stand-by mode
ILI
± 2
± 2
µA
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
µA
mA
µA
V
1
V
CC =1.8V, f =400kHz (rise/fall time < 30ns)
c
0.8
1
ICC1
VIN = VSS or VCC , VCC = 1.8 V
Stand-by Supply Current
Input Low Voltage (SCL, SDA)
1
–0.45
–0.45
0.3 VCC
0.5
VIL
Input Low Voltage
(E2, E1, E0, WC)
V
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+0.6
V
V
1
VOL
IOL = 0.7 mA, VCC = 1.8 V
Output Low Voltage
0.2
Note: 1. Preliminary data
16/24
M24512
Table 15. AC Characteristics
Test conditions specified in Table 10 and Table 7 or 8 or 9
4
4
Symbol
fC
Alt.
fSCL
Parameter
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
Max.
Clock Frequency
400
tCHCL
tHIGH
tLOW
tR
Clock Pulse Width High
Clock Pulse Width Low
Clock Rise Time
600
tCLCH
1300
tCH1CH2
tCL1CL2
300
300
300
300
tF
Clock Fall Time
2
tR
SDA Rise Time
20
20
tDH1DH2
2
tF
SDA Fall Time
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
100
0
Data Out Hold Time
200
200
600
600
600
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
900
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tCHDX
tDLCL
tCHDH
Time between Stop Condition and Next Start
Condition
tDHDL
tW
tBUF
tWR
1300
ns
Write Time
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. For the M24512-S, this is preliminary data
17/24
M24512
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
18/24
M24512
PACKAGE MECHANICAL
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Notes: 1. Drawing is not to scale.
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
19/24
M24512
Figure 13. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 17. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
2.03
0.25
1.78
0.45
–
Typ.
Max.
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
1.27
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
20/24
M24512
Figure 14. LGA8 - 8 lead Land Grid Array, Package Outline
CONTACT 1
D
D1
T3
E1
k
E
E2
T1
T2
E3
A
A2
A1
ddd
LGA-Z01B
Notes: 1. Drawing is not to scale.
Table 18. LGA8 - 8 lead Land Grid Array, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
Max.
A
A1
A2
D
1.040
0.340
0.700
8.000
0.100
5.000
1.270
3.810
0.390
0.100
0.410
0.670
0.970
0.100
0.940
1.140
0.0409
0.0134
0.0276
0.3150
0.0039
0.1969
0.0500
0.1500
0.0154
0.0039
0.0161
0.0264
0.0382
0.0039
0.0370
0.0449
0.300
0.380
0.0118
0.0150
0.640
0.760
0.0252
0.0299
7.900
8.100
0.3110
0.3189
D1
E
–
–
–
–
4.900
5.100
0.1929
0.2008
E1
E2
E3
k
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
T1
T2
T3
ddd
21/24
M24512
PART NUMBERING
Table 19. Ordering Information Scheme
Example:
M24512
–
W MW
6
T
P
Device Type
2
M24 = I C serial access EEPROM
Device Function
512 = 512 Kbit (64K x 8)
Operating Voltage
blank = V = 4.5 to 5.5V
CC
W = V = 2.5 to 5.5V
CC
1
S = V = 1.8 to 3.6V
CC
Package
BN = PDIP8
MW = SO8 (200 mil width)
LA = LGA8 (Land Grid Array)
Temperature Range
6 = –40 to 85 °C
5 = –20 to 85 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Pb-Free, RoHS compliant
G = Green package
Note: 1. The -S version (V range 1.8 V to 3.6 V) is only available in temperature range 5.
CC
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
22/24
M24512
REVISION HISTORY
Table 20. Document Revision History
Date
Rev.
Description of Revision
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
29-Jan-2001
1.1
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
LGA8 Package Mechanical data and illustration updated
SO16 package removed
10-Apr-2001
1.2
16-Jul-2001
1.3
LGA8 Package given the designator “LA”
02-Oct-2001
1.4
LGA8 Package mechanical data updated
Document becomes Preliminary Data
13-Dec-2001
12-Jun-2001
22-Oct-2003
1.5
1.6
4.0
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
Document becomes Full Datasheet
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.
V (min) improved to -0.45V.
IL
23/24
M24512
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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24/24
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