M24C01-WBN6G/W中文资料_数据手册_规格书

M24C16, M24C08

M24C04, M24C02, M24C01

16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM

FEATURES SUMMARY

■

Two-Wire I²C Serial Interface

Figure 1. Packages

Supports 400kHz Protocol

■

Single Supply Voltage:

–

2.5 to 5.5V for M24Cxx-W

1.8 to 5.5V for M24Cxx-R

8

■

Write Control Input

BYTE and PAGE WRITE (up to 16 Bytes)

RANDOM and SEQUENTIAL READ Modes

Self-Timed Programming Cycle

Automatic Address Incrementing

Enhanced ESD/Latch-Up Protection

More than 1 Million Erase/Write Cycles

More than 40-Year Data Retention

Packages

1

PDIP8 (BN)

8

–

ECOPACK® (RoHS compliant)

1

SO8 (MN)

150 mil width

Table 1. Product List

Reference

Part Number

M24C16-W

M24C16

M24C08

M24C04

M24C02

M24C01

M24C16-R

M24C08-W

M24C08-R

M24C04-W

M24C04-R

M24C02-W

M24C02-R

M24C01-W

M24C01-R

TSSOP8 (DW)

169 mil width

TSSOP8 (DS)

3x3mm² body size (MSOP)

UFDFPN8 (MB)

2x3mm² (MLP)

October 2005

1/25

M24C16, M24C08, M24C04, M24C02, M24C01

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Device internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/25

M24C16, M24C08, M24C04, M24C02, M24C01

SUMMARY DESCRIPTION

These I²C-compatible electrically erasable pro-

grammable memory (EEPROM) devices are orga-

nized as 2048/1024/512/256/128 x 8 (M24C16,

M24C08, M24C04, M24C02 and M24C01).

scribed in Table 3.), terminated by an acknowl-

edge bit.

When writing data to the memory, the device in-

th

serts an acknowledge bit during the 9 bit time,

In order to meet environmental requirements, ST

offers these devices in ECOPACK® packages.

ECOPACK® packages are Lead-free and RoHS

compliant.

ECOPACK is an ST trademark. ECOPACK speci-

fications are available at: www.st.com.

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Table 2. Signal Names

Figure 2. Logic Diagram

E0, E1, E2

SDA

Chip Enable

Serial Data

Serial Clock

Write Control

Supply Voltage

Ground

V

CC

SCL

WC

3

V

CC

SS

E0-E2

SDA

Device internal reset

In order to prevent inadvertent Write operations

during Power-up, a Power On Reset (POR) circuit

M24Cxx

SCL

WC

is included. At Power-up (continuous rise of V ),

CC

the device will not respond to any instructions until

the V

has reached the Power On Reset

CC

threshold voltage (this threshold is lower than the

min. operating voltage defined in DC and AC

V

SS

V

CC

AI02033

PARAMETERS). When V has passed over the

CC

POR threshold, the device is reset and is in

Standby

Power

mode.

At

Power-down

(continuous decay of V ), as soon as V drops

CC

I²C uses a two-wire serial interface, comprising a

bi-directional data line and a clock line. The devic-

es carry a built-in 4-bit Device Type Identifier code

(1010) in accordance with the I²C bus definition.

The device behaves as a slave in the I²C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are initiat-

ed by a Start condition, generated by the bus mas-

ter. The Start condition is followed by a Device

Select Code and Read/Write bit (RW) (as de-

from the normal operating voltage to below the

Power On Reset threshold voltage, the device

stops responding to any instruction sent to it.

Prior to selecting and issuing instructions to the

memory, a valid and stable V

voltage must be

CC

applied. This voltage must remain stable and valid

until the end of the transmission of the instruction

and, for a Write instruction, until the completion of

the internal write cycle (t ).

W

Figure 3. 8-Pin Package Connections (Top View)

M24Cxx

16Kb/8Kb/4Kb/2Kb

NC / NC / NC/ E0

NC / NC/ E1/ E1

NC/ E2/ E2/ E2

/1Kb

/ E0

/ E1

/ E2

1

2

3

4

8

7

6

5

V

CC

WC

SCL

SDA

V

SS

AI02034E

Note: 1. NC = Not Connected

2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.

3/25

M24C16, M24C08, M24C04, M24C02, M24C01

SIGNAL DESCRIPTION

Serial Clock (SCL). This input signal is used to

strobe all data in and out of the device. In applica-

tions where this signal is used by slave devices to

synchronize the bus to a slower clock, the bus

master must have an open drain output, and a

pull-up resistor can be connected from Serial

Figure 4. Device Select Code

V

CC

M24Cxx

Clock (SCL) to V . (Figure 5. indicates how the

CC

E

i

value of the pull-up resistor can be calculated). In

most applications, though, this method of synchro-

nization is not employed, and so the pull-up resis-

tor is not necessary, provided that the bus master

has a push-pull (rather than open drain) output.

V

SS

Ai11650

Serial Data (SDA). This bi-directional signal is

used to transfer data in or out of the device. It is an

open drain output that may be wire-OR’ed with

other open drain or open collector signals on the

bus. A pull up resistor must be connected from Se-

Write Control (WC). This input signal is useful

for protecting the entire contents of the memory

from inadvertent write operations. Write opera-

tions are disabled to the entire memory array when

Write Control (WC) is driven High. When uncon-

rial Data (SDA) to V . (Figure 5. indicates how

CC

nected, the signal is internally read as V , and

IL

the value of the pull-up resistor can be calculated).

Write operations are allowed.

Chip Enable (E0, E1, E2). These input signals

are used to set the value that is to be looked for on

the three least significant bits (b3, b2, b1) of the 7-

bit Device Select Code. These inputs must be tied

When Write Control (WC) is driven High, Device

Select and Address bytes are acknowledged,

Data bytes are not acknowledged.

to V or V , to establish the Device Select Code

CC

SS

as shown in Figure 4.

Figure 5. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I²C Bus

V

CC

20

16

R_P

12

8

SDA

SCL

MASTER

C

fc = 100kHz

4

0

fc = 400kHz

C

10

100

C (pF)

1000

AI01665b

4/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 6. I²C Bus Protocol

SCL

SDA

Input

SDA

Change

START

Condition

STOP

Condition

1

2

3

7

8

9

SCL

SDA

ACK

MSB

START

Condition

1

2

3

7

8

9

SCL

SDA

MSB

ACK

STOP

Condition

AI00792B

Table 3. Device Select Code

1

2,3

RW

b0

Device Type Identifier

Chip Enable

b7

b6

0

b5

1

b4

0

b3

E2

b2

E1

A9

b1

E0

A8

M24C01 Select Code

M24C02 Select Code

M24C04 Select Code

M24C08 Select Code

M24C16 Select Code

1

RW

0

1

0

E2

0

1

0

E2

0

1

0

E2

0

1

0

A10

Note: 1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

3. A10, A9 and A8 represent most significant bits of the address.

5/25

M24C16, M24C08, M24C04, M24C02, M24C01

DEVICE OPERATION

The device supports the I²C protocol. This is sum-

marized in Figure 6.. Any device that sends data

on to the bus is defined to be a transmitter, and

any device that reads the data to be a receiver.

The device that controls the data transfer is known

as the bus master, and the other as the slave de-

vice. A data transfer can only be initiated by the

bus master, which will also provide the serial clock

for synchronization. The M24Cxx device is always

a slave in all communication.

Clock (SCL), and the Serial Data (SDA) signal

must change only when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus master must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 3.

(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address”

(E2, E1, E0). To address the memory array, the 4-

bit Device Type Identifier is 1010b.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not respond unless one is given.

Each device is given a unique 3-bit code on the

Chip Enable (E0, E1, E2) inputs. When the Device

Select Code is received, the device only responds

if the Chip Enable Address is the same as the val-

ue on the Chip Enable (E0, E1, E2) inputs. How-

ever, those devices with larger memory capacities

(the M24C16, M24C08 and M24C04) need more

address bits. E0 is not available for use on devices

that need to use address line A8; E1 is not avail-

able for devices that need to use address line A9,

and E2 is not available for devices that need to use

address line A10 (see Figure 3. and Table 3. for

details). Using the E0, E1 and E2 inputs, up to

eight M24C02 (or M24C01), four M24C04, two

M24C08 or one M24C16 devices can be connect-

ed to one I²C bus. In each case, and in the hybrid

cases, this gives a total memory capacity of

16 Kbits, 2 KBytes (except where M24C01 devic-

es are used).

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminates communica-

tion between the device and the bus master. A

Read command that is followed by NoAck can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a Write command triggers the internal Write

cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-

ful byte transfer. The bus transmitter, whether it be

bus master or slave device, releases Serial Data

th

The 8 bit is the Read/Write bit (RW). This bit is

(SDA) after sending eight bits of data. During the

th

set to 1 for Read and 0 for Write operations.

9

clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SDA) during the 9 bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

th

Table 4. Operating Modes

1

Mode

RW bit

Bytes

Initial Sequence

WC

X

Current Address Read

1

0

1

0

1

START, Device Select, RW = 1

X

START, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

Similar to Current or Random Address Read

START, Device Select, RW = 0

Random Address Read

1

X

Sequential Read

Byte Write

X

≥ 1

1

V_IL

Page Write

≤16

START, Device Select, RW = 0

Note: 1. X = V_IHor V_IL.

6/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 7. Write Mode Sequences with WC=1 (data write inhibited)

WC

ACK

NO ACK

DATA IN

Byte Write

DEV SEL

BYTE ADDR

R/W

WC

ACK

NO ACK

DATA IN 3

Page Write

DEV SEL

BYTE ADDR

DATA IN 1 DATA IN 2

R/W

WC (cont'd)

NO ACK

Page Write

(cont'd)

DATA IN N

AI02803C

Write Operations

the Start condition until the end of the address

byte), the device replies to the data byte with

NoAck, as shown in Figure 7., and the location is

not modified. If, instead, the addressed location is

not Write-protected, the device replies with Ack.

The bus master terminates the transfer by gener-

ating a Stop condition, as shown in Figure 8..

Following a Start condition the bus master sends

a Device Select Code with the Read/Write bit

(RW) reset to 0. The device acknowledges this, as

shown in Figure 8., and waits for an address byte.

The device responds to the address byte with an

acknowledge bit, and then waits for the data byte.

Page Write

When the bus master generates a Stop condition

immediately after the Ack bit (in the “10 bit” time

th

The Page Write mode allows up to 16 bytes to be

written in a single Write cycle, provided that they

are all located in the same page in the memory:

that is, the most significant memory address bits

are the same. If more bytes are sent than will fit up

to the end of the page, a condition known as ‘roll-

over’ occurs. This should be avoided, as data

starts to become overwritten in an implementation

dependent way.

The bus master sends from 1 to 16 bytes of data,

each of which is acknowledged by the device if

Write Control (WC) is Low. If the addressed loca-

tion is Write-protected, by Write Control (WC) be-

ing driven High (during the period from the Start

slot), either at the end of a Byte Write or a Page

Write, the internal Write cycle is triggered. A Stop

condition at any other time slot does not trigger the

internal Write cycle.

During the internal Write cycle, Serial Data (SDA)

and Serial Clock (SCL) are ignored, and the de-

vice does not respond to any requests.

Byte Write

After the Device Select code and the address byte,

the bus master sends one data byte. If the ad-

dressed location is Write-protected, by Write Con-

trol (WC) being driven High (during the period from

7/25

M24C16, M24C08, M24C04, M24C02, M24C01

condition until the end of the address byte), the de-

vice replies to the data bytes with NoAck, as

shown in Figure 7., and the locations are not mod-

ified. After each byte is transferred, the internal

byte address counter (the 4 least significant ad-

dress bits only) is incremented. The transfer is ter-

minated by the bus master generating a Stop

condition.

Figure 8. Write Mode Sequences with WC=0 (data write enabled)

WC

ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

R/W

WC

ACK

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

DATA IN 3

R/W

WC (cont'd)

ACK

PAGE WRITE

(cont'd)

DATA IN N

AI02804B

8/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 9. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

NO

First byte of instruction

with RW = 0 already

decoded by the device

YES

Addressing the

Memory

NO

YES

Send Address

and Receive ACK

ReSTART

START

NO

YES

STOP

Condition

DATA for the

WRITE Operation

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

WRITE Operation

AI01847C

Minimizing System Delays by Polling On ACK

–

Initial condition: a Write cycle is in progress.

During the internal Write cycle, the device discon-

nects itself from the bus, and writes a copy of the

data from its internal latches to the memory cells.

Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first

byte of the new instruction).

The maximum Write time (t ) is shown in Table

w

–

Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the

bus master goes back to Step 1. If the device

has terminated the internal Write cycle, it

responds with an Ack, indicating that the

device is ready to receive the second part of

the instruction (the first byte of this instruction

having been sent during Step 1).

13. and Table 14., but the typical time is shorter.

To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in Figure 9., is:

9/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 10. Read Mode Sequences

ACK

NO ACK

DATA OUT

CURRENT

ADDRESS

READ

DEV SEL

R/W

ACK

NO ACK

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

BYTE ADDR

DEV SEL *

R/W

ACK

NO ACK

DATA OUT N

SEQUENTIAL

CURRENT

READ

DEV SEL

DATA OUT 1

R/W

ACK

SEQUENTIAL

RANDOM

READ

DEV SEL *

BYTE ADDR

DEV SEL * DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

AI01942

st

rd

Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.

Read Operations

Read operations are performed independently of

the state of the Write Control (WC) signal.

dressed byte. The bus master must not

acknowledge the byte, and terminates the transfer

with a Stop condition.

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read.

Random Address Read

A dummy Write is first performed to load the ad-

dress into this address counter (as shown in Fig-

ure 10.) but without sending a Stop condition.

Then, the bus master sends another Start condi-

tion, and repeats the Device Select Code, with the

Read/Write bit (RW) set to 1. The device acknowl-

edges this, and outputs the contents of the ad-

For the Current Address Read operation, following

a Start condition, the bus master only sends a De-

vice Select Code with the Read/Write bit (RW) set

to 1. The device acknowledges this, and outputs

the byte addressed by the internal address

counter. The counter is then incremented. The bus

master terminates the transfer with a Stop condi-

tion, as shown in Figure 10., without acknowledg-

ing the byte.

10/25

M24C16, M24C08, M24C04, M24C02, M24C01

Acknowledge in Read Mode

Sequential Read

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master does acknowledge the data byte output,

and sends additional clock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must not acknowledge the last byte, and must

generate a Stop condition, as shown in Figure 10..

For all Read commands, the device waits, after

each byte read, for an acknowledgment during the

9 bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the device termi-

nates the data transfer and switches to its Stand-

by mode.

th

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’,

and the device continues to output data from

memory address 00h.

INITIAL DELIVERY STATE

The device is delivered with all bits in the memory

array set to 1 (each byte contains FFh).

11/25

M24C16, M24C08, M24C04, M24C02, M24C01

MAXIMUM RATING

Stressing the device outside the ratings listed in

Table 5. may cause permanent damage to the de-

vice. These are stress ratings only, and operation

of the device at these, or any other conditions out-

side those indicated in the Operating sections of

this specification, is not implied. Exposure to Ab-

solute Maximum Rating conditions for extended

periods may affect device reliability. Refer also to

the STMicroelectronics SURE Program and other

relevant quality documents.

Table 5. Absolute Maximum Ratings

Symbol

T_A

Parameter

Ambient Operating Temperature

Min.

–40

–65

Max.

125

Unit

°C

V

T_STG

T_LEAD

V_IO

Storage Temperature

150

1

Lead Temperature during Soldering

Input or Output range

–0.50

–4000

6.5

V_CC

Supply Voltage

V

2

V_ESD

4000

V

Electrostatic Discharge Voltage (Human Body model)

®

Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)

12/25

M24C16, M24C08, M24C04, M24C02, M24C01

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 6. Operating Conditions (M24Cxx-W)

Symbol

Parameter

Min.

2.5

Max.

5.5

Unit

V

Supply Voltage

CC

Ambient Operating Temperature (Device Grade 6)

Ambient Operating Temperature (Device Grade 3)

–40

85

°C

T_A

125

Table 7. Operating Conditions (M24Cxx-R)

Symbol

Parameter

Min.

1.8

Max.

5.5

Unit

V

Supply Voltage

Ambient Operating Temperature

CC

T_A

–40

85

°C

Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)

Test Condition

(in addition to those in Table 6.)

Symbol

Parameter

Min.

Max.

Unit

Input Leakage Current

(SCL, SDA, E0, E1,and E2)

I_LI

V

_IN= V_SSor V_CC

± 2

µA

I_LO

Output Leakage Current

V

_OUT= V_SSor V_CC,SDA in Hi-Z

± 2

µA

mA

µA

V

_CC=5V, f =400kHz (rise/fall time < 30ns)

2

1

c

I_CC

Supply Current

V_CC=2.5V, f =400kHz (rise/fall time < 30ns)

c

V_IN= V_SSor V_CC, V_CC= 5 V

1

I_CC1

Stand-by Supply Current

V

_IN= V_SSor V_CC, V_CC= 2.5 V

0.5

0.3V_CC

(1)

V_IL

V_IH

V_OL

–0.45

Input Low Voltage

(1)

0.7V_CC

V_CC+1

0.4

V

Input High Voltage

Output Low Voltage

I_OL= 2.1 mA, V_CC= 2.5 V

Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.

13/25

M24C16, M24C08, M24C04, M24C02, M24C01

Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)

Test Condition

(in addition to those in Table 6.)

Symbol

Parameter

Unit

Min.

Max.

Input Leakage Current

(SCL, SDA, E0, E1,and E2)

I_LI

V

_IN= V_SSor V_CC

± 2

µA

I_LO

Output Leakage Current

Supply Current

V_OUT= V_SSor V_CC,SDA in Hi-Z

± 2

3

µA

V_CC=5V, f =400kHz (rise/fall time < 30ns)

mA

C

I_CC

V

_CC=2.5V, f =400kHz

C

3

mA

(rise/fall time < 30ns)

V_IN= V_SSor V_CC, V_CC= 5 V

V_IN= V_SSor V_CC, V_CC= 2.5 V

5

2

µA

V

I_CC1

Stand-by Supply Current

(1)

V_IL

V_IH

V_OL

–0.45

0.3V_CC

Input Low Voltage

(1)

0.7V_CC

V_CC+1

0.4

V

Input High Voltage

Output Low Voltage

I_OL= 2.1 mA, V_CC= 2.5 V

Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.

Table 10. DC Characteristics (M24Cxx-R)

Test Condition

Symbol

Parameter

Min.

Max.

Unit

(in addition to those in Table 7.)

Input Leakage Current

(SCL, SDA, E0, E1,and E2)

I_LI

V

_IN= V_SSor V_CC

± 2

µA

I_LO

I_CC

Output Leakage Current

Supply Current

V

_OUT= V_SSor V_CC,SDA in Hi-Z

± 2

0.8

µA

mA

µA

V

_CC=1.8V, f =400kHz (rise/fall time < 30ns)

c

I_CC1

Stand-by Supply Current

V

_IN= V_SSor V_CC, V_CC= 1.8 V

2.5 V ≤V_CC

0.3

–0.45

0.3 V_CC

0.25 V_CC

V_CC+1

0.2

(1)

V_IL

Input Low Voltage

1.8 V ≤V_CC< 2.5 V

V

(1)

V_IH

0.7V_CC

V

Input High Voltage

V_OL

Output Low Voltage

I_OL= 0.7 mA, V_CC= 1.8 V

V

Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.

Table 11. AC Measurement Conditions

Symbol

Parameter

Min.

Max.

Unit

C

Load Capacitance

100

pF

ns

V

L

Input Rise and Fall Times

Input Levels

50

0.2V to 0.8V

CC

0.3V to 0.7V

Input and Output Timing Reference Levels

V

CC

14/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 11. AC Measurement I/O Waveform

Input Levels

Input and Output

Timing Reference Levels

0.8V

CC

0.7V

CC

0.3V

CC

0.2V

CC

AI00825B

Table 12. Input Parameters

1,2

Symbol

C_IN

Test Condition

Min.

Max.

8

Unit

pF

Parameter

Input Capacitance (SDA)

Input Capacitance (other pins)

WC Input Impedance

C_IN

6

pF

Z_WCL

Z_WCH

V

_IN< 0.3 V

15

70

kΩ

WC Input Impedance

V

_IN> 0.7V_CC

500

Pulse width ignored

(Input Filter on SCL and SDA)

t_NS

Single glitch

100

ns

Note: 1. T = 25°C, f = 400kHz

A

2. Sampled only, not 100% tested.

15/25

M24C16, M24C08, M24C04, M24C02, M24C01

Table 13. AC Characteristics (M24Cxx-W)

Test conditions specified in Table 6. and Table 11.

Parameter

Symbol

f_C

Alt.

f_SCL

Min.

Max.

Unit

kHz

ns

Clock Frequency

400

t_CHCL

t_CLCH

t_HIGH

t_LOW

t_F

Clock Pulse Width High

Clock Pulse Width Low

SDA Fall Time

600

1300

20

ns

2

300

900

ns

t_DL1DL2

t_DXCX

t_CLDX

t_CLQX

t_SU:DAT

t_HD:DAT

t_DH

Data In Set Up Time

Data In Hold Time

Data Out Hold Time

100

0

ns

200

600

1300

ns

3

t_AA

Clock Low to Next Data Valid (Access Time)

Start Condition Set Up Time

ns

t_CLQV

1

t_SU:STA

t_HD:STA

t_SU:STO

t_BUF

ns

ms

t_CHDX

t_DLCL

t_CHDH

t_DHDL

Start Condition Hold Time

Stop Condition Set Up Time

Time between Stop Condition and Next Start Condition

Write Time

4

t_WR

5

t_W

Note: 1. For a reSTART condition, or following a Write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-

mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/

EE/0061 and 0062 (PCEE0061 and PCEE0062).

Table 14. AC Characteristics (M24Cxx-R)

Test conditions specified in Table 7. and Table 10.

4

Symbol

f_C

Alt.

f_SCL

Parameter

Unit

kHz

ns

Min.

Max.

Clock Frequency

400

t_CHCL

t_CLCH

t_HIGH

t_LOW

t_F

Clock Pulse Width High

Clock Pulse Width Low

SDA Fall Time

600

1300

20

ns

2

300

900

ns

t_DL1DL2

t_DXCX

t_CLDX

t_CLQX

t_SU:DAT

t_HD:DAT

t_DH

Data In Set Up Time

Data In Hold Time

Data Out Hold Time

100

0

ns

200

600

1300

ns

3

t_AA

Clock Low to Next Data Valid (Access Time)

Start Condition Set Up Time

ns

t_CLQV

1

t_SU:STA

t_HD:STA

t_SU:STO

t_BUF

ns

t_CHDX

t_DLCL

t_CHDH

t_DHDL

t_W

Start Condition Hold Time

ns

Stop Condition Set Up Time

ns

Time between Stop Condition and Next Start Condition

Write Time

ns

t_WR

10

ms

Note: 1. For a reSTART condition, or following a Write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This is preliminary information.

16/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 12. AC Waveforms

tCHCL

tCLCH

SCL

tDLCL

SDA In

tCHDX

tCLDX

tDXCX

SDA

tCHDH tDHDL

Change

START

Condition

START

Condition

SDA

Input

STOP

Condition

SCL

SDA In

tCHDH

STOP

tCHDX

START

Condition

tW

Write Cycle

Condition

SCL

tCLQV

tCLQX

Data Valid

SDA Out

AI00795C

17/25

M24C16, M24C08, M24C04, M24C02, M24C01

PACKAGE MECHANICAL

Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline

E

b2

A2

A1

A

L

c

b

e

eA

eB

D

8

1

E1

PDIP-B

Note: Drawing is not to scale.

Table 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

mm

inches

Min.

Symb.

Typ.

Min.

Max.

Typ.

Max.

A

A1

A2

b

5.33

0.210

0.38

2.92

0.36

1.14

0.20

9.02

7.62

6.10

–

0.015

0.115

0.014

0.045

0.008

0.355

0.300

0.240

–

3.30

0.46

1.52

0.25

9.27

7.87

6.35

2.54

7.62

4.95

0.56

1.78

0.36

10.16

8.26

7.11

–

0.130

0.018

0.060

0.010

0.365

0.310

0.250

0.100

0.300

0.195

0.022

0.070

0.014

0.400

0.325

0.280

–

b2

c

D

E

E1

e

eA

eB

L

–

10.92

3.81

0.430

0.150

3.30

2.92

0.130

0.115

18/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

h x 45˚

A

C

B

CP

e

D

N

E

H

1

A1

α

L

SO-a

Note: Drawing is not to scale.

Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

mm

Min.

1.35

0.10

0.33

0.19

4.80

3.80

–

inches

Min.

0.053

0.004

0.013

0.007

0.189

0.150

–

Symb.

Typ.

Max.

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ.

Max.

0.069

0.010

0.020

0.010

0.197

0.157

–

A

A1

B

C

D

E

e

1.27

0.050

H

h

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

L

α

N

CP

8

0.10

0.004

19/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 15. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline

e

b

D

L1

L3

E

E2

L

A

D2

ddd

A1

UFDFPN-01

Note: 1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V . It must not be allowed to be connected to

SS

any other voltage or signal line on the PCB, for example during the soldering process.

Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data

mm

Min.

0.50

0.00

0.20

inches

Min.

Symbol

Typ.

Max.

0.60

0.05

0.30

Typ.

Max.

0.024

0.002

0.012

A

A1

b

0.55

0.022

0.020

0.000

0.008

0.25

2.00

0.010

0.079

D

D2

ddd

E

1.55

1.65

0.05

0.061

0.065

0.002

3.00

0.118

E2

e

0.15

–

0.25

–

0.006

–

0.010

–

0.50

0.45

0.020

0.018

L

0.40

0.50

0.15

0.016

0.020

0.006

L1

L3

N

0.30

0.012

8

20/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline

D

8

5

c

E1

E

1

4

α

A1

L

A

A2

L1

CP

b

e

TSSOP8AM

Note: Drawing is not to scale.

Table 18. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

mm

inches

Min.

Symbol

Typ.

Min.

Max.

1.200

0.150

1.050

0.300

0.200

0.100

3.100

–

Typ.

Max.

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

–

A

A1

A2

b

0.050

0.800

0.190

0.090

0.0020

0.0315

0.0075

0.0035

1.000

0.0394

c

CP

D

3.000

0.650

6.400

4.400

0.600

1.000

2.900

–

0.1181

0.0256

0.2520

0.1732

0.0236

0.0394

0.1142

–

e

E

6.200

4.300

0.450

6.600

4.500

0.750

0.2441

0.1693

0.0177

0.2598

0.1772

0.0295

E1

L

L1

α

0°

8°

0°

8°

21/25

M24C16, M24C08, M24C04, M24C02, M24C01

Figure 17. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline

D

8

1

5

4

c

E1

E

α

A1

L

A

A2

L1

CP

b

e

TSSOP8BM

Note: Drawing is not to scale.

Table 19. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data

mm

inches

Min.

Symbol

Typ.

Min.

Max.

1.100

0.150

0.950

0.400

0.230

3.100

5.150

3.100

–

Typ.

Max.

0.0433

0.0059

0.0374

0.0157

0.0091

0.1220

0.2028

0.1220

–

A

A1

A2

b

0.050

0.750

0.250

0.130

2.900

4.650

2.900

–

0.0020

0.0295

0.0098

0.0051

0.1142

0.1831

0.1142

–

0.850

0.0335

c

D

3.000

4.900

3.000

0.650

0.1181

0.1929

0.1181

0.0256

E

E1

e

CP

L

0.100

0.700

0.0039

0.0276

0.550

0.950

0.400

0°

0.0217

0.0374

0.0157

0°

L1

α

6°

22/25

M24C16, M24C08, M24C04, M24C02, M24C01

PART NUMBERING

Table 20. Ordering Information Scheme

Example:

M24C16

–

W DW

3

T

P

/W

Device Type

2

M24 = I C serial access EEPROM

Device Function

16 = 16 Kbit (2048 x 8)

08 = 8 Kbit (1024 x 8)

04 = 4 Kbit (512 x 8)

02 = 2 Kbit (256 x 8)

01 = 1 Kbit (128 x 8)

Operating Voltage

W = V = 2.5 to 5.5V (400 kHz)

CC

R = V = 1.8 to 5.5V (400 kHz)

CC

Package

BN = PDIP8

MN = SO8 (150 mil width)

MB = UDFDFPN8 (MLP8)

DW = TSSOP8 (169 mil width)

DS = TSSOP8 (3x3mm² body size, MSOP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

1

3 = Device tested with High Reliability Certified Flow .

Automotive temperature range (–40 to 125 °C)

Option

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

P or G = ECOPACK® (RoHS compliant)

2

Process

/W or /S = F6SP36%

Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-

tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.

2. Used only for Device Grade 3.

For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-

fice.

The category of second Level Interconnect is

marked on the package and on the inner box label,

in compliance with JEDEC Standard JESD97. The

maximum ratings related to soldering conditions

are also marked on the inner box label.

23/25

M24C16, M24C08, M24C04, M24C02, M24C01

REVISION HISTORY

Table 21. Document Revision History

Date

Version

Description of Revision

TSSOP8 Turned-Die package removed (p 2 and order information)

Lead temperature added for TSSOP8 in table 2

10-Dec-1999

2.4

18-Apr-2000

05-May-2000

2.5

2.6

Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13

Extra labelling to Fig-2D

SBGA package information removed to an annex document

-R range changed to being the -S range, and the new -R range added

23-Nov-2000

3.0

SBGA package information put back in this document

Lead Soldering Temperature in the Absolute Maximum Ratings table amended

Write Cycle Polling Flow Chart using ACK illustration updated

References to PSDIP changed to PDIP and Package Mechanical data updated

Wording brought in to line with standard glossary

19-Feb-2001

3.1

20-Apr-2001

08-Oct-2001

3.2

3.3

Revision of DC and AC characteristics for the -S series

Ball numbers added to the SBGA connections and package mechanical illustrations

Specification of Test Condition for Leakage Currents in the DC Characteristics table

improved

09-Nov-2001

3.4

Document reformatted using new template. SBGA5 package removed

TSSOP8 (3x3mm² body size) package (MSOP8) added. -L voltage range added

30-Jul-2002

04-Feb-2003

3.5

3.6

Document title spelt out more fully. “W”-marked devices with tw=5ms added.

-R voltage range upgraded to 400kHz working, and no longer preliminary data.

5V voltage range at temperature range 3 (-xx3) no longer preliminary data.

-S voltage range removed. -Wxx3 voltage+temp ranged added as preliminary data.

05-May-2003

07-Oct-2003

3.7

4.0

Table of contents, and Pb-free options added. Minor wording changes in Summary

Description, Power-On Reset, Memory Addressing, Read Operations. V (min) improved to

IL

-0.45V. t (max) value for -R voltage range corrected.

W

MLP package added. Absolute Maximum Ratings for V (min) and V (min) changed.

IO

CC

Soldering temperature information clarified for RoHS compliant devices. Device grade

information clarified. Process identification letter “G” information added. 2.2-5.5V range is

removed, and 4.5-5.5V range is now Not for New Design

17-Mar-2004

7-Oct-2005

5.0

6.0

Product List summary table added. AEC-Q100-002 compliance. Device Grade informaton

clarified. Updated Device internal reset section, Figure 4., Figure 5., Table 14. and Table

20. Added Ecopack® information. Updated tW=5ms for the M24Cxx-W.

24/25

M24C16, M24C08, M24C04, M24C02, M24C01

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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25/25

型号	制造商	描述	价格	文档
M24C01-WBN6P	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6P/S	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6P/W	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6T	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6T/G	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6T/S	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6T/W	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6TG	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6TG/G	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格
M24C01-WBN6TG/S	STMICROELECTRONICS	16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM	获取价格

M24C01-WBN6G/W

M24C01-WBN6G/W 概述

M24C01-WBN6G/W 数据手册

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