M24C02-SMN1T [STMICROELECTRONICS]
IC,SERIAL EEPROM,256X8,CMOS,SOP,8PIN,PLASTIC;
| 型号： | M24C02-SMN1T |
| 厂家： | 
ST |
| 描述： | IC,SERIAL EEPROM,256X8,CMOS,SOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总19页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C16, M24C08
M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
2
■ Two Wire I C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 5.5V for M24Cxx-R
– 1.8V to 3.6V for M24Cxx-S
■ Hardware Write Control
8
1
PSDIP8 (BN)
0.25 mm frame
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
8
8
■ Enhanced ESD/Latch-Up Behavior
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
1
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
DESCRIPTION
2
These I C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 bit
(M24C16, M24C08, M24C04, M24C02, M24C01),
and operate with a power supply down to 2.5 V (for
the -W version of each device), and down to 1.8 V
(for the -R and -S versions of each device).
Figure 1. Logic Diagram
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small
Outline packages.
V
CC
3
E0-E2
SDA
Table 1. Signal Names
M24Cxx
SCL
WC
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
SCL
V
WC
SS
AI02033
V
V
CC
SS
November 2000
1/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
M24Cxx
16Kb/8Kb/4Kb/2Kb
NC / NC / NC/ E0
NC / NC/ E1/ E1
NC/ E2/ E2/ E2
/1Kb
/ E0
/ E1
/ E2
1
2
3
4
8
7
6
5
V
CC
WC
SCL
SDA
V
SS
AI02034D
Note: 1. NC = Not Connected
Figure 2B. SO Connections
M24Cxx
16Kb/8Kb/4Kb/2Kb
/1Kb
/ E0
/ E1
/ E2
NC / NC / NC/ E0
NC / NC/ E1/ E1
NC/ E2/ E2/ E2
1
2
3
4
8
7
6
5
V
CC
WC
SCL
SDA
V
SS
AI02035D
Note: 1. NC = Not Connected
Figure 2C. Standard-TSSOP Connections
M24Cxx
16Kb/8Kb/4Kb/2Kb
NC / NC / NC/ E0
NC / NC/ E1/ E1
NC/ E2/ E2/ E2
/1Kb
/ E0
/ E1
/ E2
1
8
7
6
5
V
CC
WC
2
3
4
SCL
SDA
V
SS
AI02036D
Note: 1. NC = Not Connected
These memory devices are compatible with the
I C memory standard. This is a two wire serial
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
2
interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
unique Device Type Identifier code (1010) in
2
accordance with the I C bus definition.
The memory behaves as a slave device in the I C
2
Power On Reset: V
Lock-Out Write Protect
CC
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V
voltage has reached
CC
the POR threshold value, and all operations are
disabled – the device will not respond to any
When writing data to the memory, the memory
inserts an acknowledge bit during the 9 bit time,
command. In the same way, when V drops from
the operating voltage, below the POR threshold
CC
th
2/19
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
–40 to 125
°C
Storage
Temperature
TSTG
–65 to 150
°C
°C
PSDIP8: 10 sec
SO8: 40 sec
TSSOP8: 40 sec
260
215
215
Lead Temperature
during Soldering
TLEAD
VIO
Input or Output range
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
V
V
VCC
4000
2
VESD
V
Electrostatic Discharge Voltage (Human Body model )
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
value, all operations are disabled and the device
will not respond to any command. A stable and
synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
valid V
must be applied before applying any
CC
logic signal.
Serial Data (SDA)
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to V . (Figure 3 indicates how the value of
CC
the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
from the SCL line to V . (Figure 3 indicates how
CC
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
2
Figure 3. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/19
M24C16, M24C08, M24C04, M24C02, M24C01
2
Figure 4. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
bits (b3, b2, b1) of the 7-bit device select code (but
see the description of memory addressing, on
page 5, for more details). These inputs may be
DEVICE OPERATION
The memory device supports the I C protocol.
driven dynamically or tied to V
or V
to
CC
SS
2
establish the device select code (but note that the
and V levels for the inputs are CMOS
V
IL
IH
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
compatible, not TTL compatible).
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V ) or disable (WC=V )
IL
IH
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
device is always
communication.
a
slave device in all
V , and write operations are allowed.
IL
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not
acknowledged.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
4/19
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 3. Device Select Code
Device Type Identifier
Chip Enable
RW
b0
b7
b6
0
b5
1
b4
0
b3
E2
b2
E1
E1
E1
A9
A9
b1
E0
E0
A8
A8
A8
M24C01 Select Code
M24C02 Select Code
M24C04 Select Code
M24C08 Select Code
M24C16 Select Code
1
1
1
1
1
RW
RW
RW
RW
RW
0
1
0
E2
0
1
0
E2
0
1
0
E2
0
1
0
A10
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent high significant bits of the address.
data transfer command. The memory device
continuously monitors (except during
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change only when
the SCL line is low.
a
Memory Addressing
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0).
state.
A
STOP
condition
terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
Up to eight memory devices can be connected on
2
a single I C bus. Each one is given a unique 3-bit
th
bus after sending eight bits of data. During the 9
code on its Chip Enable inputs. When the Device
Select Code is received, the memory only
responds if the Chip Enable Code (shown in Table
3) is the same as the pattern applied to its Chip
Enable pins.
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.
Data Input
Those devices with larger memory capacities (the
M24C16, M24C08 and M24C04) need more
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
Table 4. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = ‘1’
X
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 16
START, Device Select, RW = ‘0’
Note: 1. X = VIH or VIL.
5/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
NO ACK
DATA IN
Byte Write
DEV SEL
BYTE ADDR
R/W
WC
ACK
ACK
NO ACK
NO ACK
DATA IN 3
Page Write
DEV SEL
BYTE ADDR
DATA IN 1 DATA IN 2
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
DATA IN N
AI02803C
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not
available for devices that need to use address line
A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2A to Figure 2C
and Table 3 for details). Using the E0, E1 and E2
inputs pins, up to eight M24C02 (or M24C01), four
M24C04, two M24C08 or one M24C16 device can
later. A communication between the master and
the slave is ended with a STOP condition.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high (Figure 5). Any write
command with WC=1 (during a period of time from
the START condition until the end of the address
byte) will not modify the memory contents, and the
2
be connected to one I C bus. In each case, and in
the hybrid cases, this gives a total memory
capacity of 16 Kbits, 2 KBytes (except where
M24C01 devices are used).
th
The 8 bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
accompanying data bytes will
acknowledged.
not
be
th
bus during the 9 bit time. If the memory does not
Byte Write
match the Device Select Code, it deselects itself
from the bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 4 and described
In the Byte Write mode, after the Device Select
Code and the address, the master sends one data
byte. If the addressed location is write protected by
6/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
DATA IN 3
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI02804
the WC pin, the memory replies with a NoAck, and
the location is not modified. If, instead, the WC pin
has been held at 0, as shown in Figure 6, the
memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.
byte address counter (the 4 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition
th
immediately after the Ack bit (in the “10 bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll-
over’ occurs. Data starts to become overwritten, or
otherwise altered.
The master sends from one up to 16 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (t ) is shown in Table 6A
w
and Table 6B, but the typical time is shorter. To
make use of this, an Ack polling sequence can be
used by the master.
7/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
START
NO
YES
STOP
Condition
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01847B
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW bit
set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must not acknowledge the byte output, and
terminates the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as
shown in Figure 8, without acknowledging the byte
output.
8/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Read Mode Sequences
ACK
NO ACK
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
st
rd
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.
Sequential Read
counter ‘rolls-over’ and the memory continues to
output data from memory address 00h.
Acknowledge in Read Mode
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
In all read modes, the memory waits, after each
th
byte read, for an acknowledgment during the 9
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
9/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 5A. DC Characteristics
(T = 0 to 70 °C, or –40 to 85 °C; V = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
CC
(T = 0 to 70 °C, or –40 to 85 °C; V = 1.8 to 5.5 V or 1.8 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
0 V ≤ VIN ≤ VCC
± 2
µA
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
± 2
2
µA
mA
mA
mA
VCC=5V, f =400kHz (rise/fall time < 30ns)
c
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
-W series:
-R series:
-S series:
1
c
ICC
Supply Current
1
V
CC =1.8V, f =100kHz (rise/fall time < 30ns)
c
0.8
1
V
CC =1.8V, f =400kHz (rise/fall time < 30ns)
mA
µA
µA
µA
c
0.8
VIN = VSS or VCC , VCC = 5 V
1
-W series:
-R series:
-S series:
V
V
V
IN = VSS or VCC , VCC = 2.5 V
IN = VSS or VCC , VCC = 1.8 V
0.5
Supply Current
(Stand-by)
ICC1
1
0.3
1
IN = VSS or VCC , VCC = 1.8 V
4.5 V ≤ VCC ≤ 5.5 V
µA
V
0.1
0.3 VCC
0.3 VCC
– 0.3
– 0.3
– 0.3
2.5 V ≤ VCC ≤ 5.5 V
-W series:
-R series:
V
Input Low
Voltage
(E0, E1, E2,
1
1.8 V ≤ VCC < 2.5 V
V
0.25 VCC
VIL
1
SCL, SDA)
2.5 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC ≤ 3.6 V
– 0.3
– 0.3
V
V
0.3 VCC
0.3 VCC
1
-S series:
Input High Voltage
VIH
0.7VCC
VCC+1
V
(E0, E1, E2, SCL, SDA)
Input Low Voltage (WC)
Input High Voltage (WC)
VIL
VIH
– 0.3
0.5
VCC+1
0.4
V
V
V
V
V
0.7VCC
IOL = 3 mA, VCC = 5 V
-W series:
I
I
I
OL = 2.1 mA, VCC = 2.5 V
OL = 0.7 mA, VCC = 1.8 V
OL = 0.7 mA, VCC = 1.8 V
0.4
Output Low
Voltage
VOL
1
-R series:
-S series:
0.2
1
V
0.2
Note: 1. This is preliminary data.
10/19
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 5B. DC Characteristics
(T = –40 to 125 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
± 2
Unit
µA
ILI
Input Leakage Current (SCL, SDA)
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
± 2
µA
VCC=5V, f =400kHz (rise/fall
c
ICC
Supply Current
3
mA
time < 30ns)
ICC1
VIL
Supply Current (Stand-by)
VIN = VSS orVCC , VCC = 5 V
5
µA
V
Input Low Voltage (E0, E1, E2, SCL, SDA)
Input High Voltage (E0, E1, E2, SCL, SDA)
Input Low Voltage (WC)
– 0.3
0.7VCC
– 0.3
0.3 VCC
VCC+1
0.5
VIH
VIL
V
V
VIH
VOL
0.7VCC
VCC+1
0.4
Input High Voltage (WC)
V
Output Low Voltage
IOL = 3 mA, VCC = 5 V
V
Note: 1. This is preliminary data.
Table 6A. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01
V
=4.5 to 5.5 V
CC
V
=4.5 to 5.5 V;
CC
Symbol
Alt.
Parameter
T =0 to 70°C or
Unit
A
4
T =–40 to 125°C
A
–40 to 85°C
Min
Max
300
300
300
300
Min
Max
300
300
300
300
tCH1CH2
tCL1CL2
tR
tF
tR
Clock Rise Time
ns
ns
ns
ns
Clock Fall Time
2
SDA Rise Time
20
20
20
20
tDH1DH2
2
tF
SDA Fall Time
tDL1DL2
1
tSU:STA
tHIGH
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
600
600
600
0
600
600
600
0
ns
ns
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
tHD:STA
ns
tHD:DAT Clock Low to Input Transition
tLOW
tSU:DAT Input Transition to Clock Transition
µs
Clock Pulse Width Low
1.3
100
600
1.3
200
200
1.3
100
600
1.3
200
200
µs
ns
tSU:STO
tBUF
tAA
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Data Out Valid
Data Out Hold Time After Clock Low
Clock Frequency
ns
µs
3
900
900
ns
tCLQV
tCLQX
fC
tDH
ns
fSCL
tWR
400
5
400
10
kHz
ms
tW
Write Time
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
11/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 6B. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01
V
=1.8 to 5.5 V =1.8 to 3.6 V
V
CC
V
=2.5 to 5.5 V
CC
CC
T =0 to 70°C or T =0 to 70°C or
Symbol
Alt.
Parameter
T =0 to 70°C or
–40 to 85°C
Unit
A
A
A
4
4
–40 to 85°C
–40 to 85°C
Min
Max
300
300
300
300
Min
Max
1000
300
Min
Max
300
300
300
300
tCH1CH2
tCL1CL2
tR
tF
Clock Rise Time
ns
ns
ns
ns
Clock Fall Time
2
tR
SDA Rise Time
20
20
20
20
1000
300
20
20
tDH1DH2
2
tF
SDA Fall Time
tDL1DL2
1
tSU:STA
Clock High to Input Transition
600
600
600
0
4700
4000
4000
0
600
600
600
0
ns
ns
ns
µs
µs
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tHIGH Clock Pulse Width High
tHD:STA
tHD:DAT Clock Low to Input Transition
Input Low to Clock Low (START)
tLOW
Clock Pulse Width Low
1.3
4.7
1.3
Input Transition to Clock
Transition
tDXCX
tCHDH
tDHDL
tSU:DAT
100
600
1.3
250
4000
4.7
100
600
1.3
ns
ns
µs
ns
ns
tSU:STO Clock High to Input High (STOP)
Input High to Input Low (Bus
Free)
tBUF
3
tAA
tDH
Clock Low to Data Out Valid
200
200
900
200
200
3500
200
200
900
tCLQV
Data Out Hold Time After Clock
Low
tCLQX
fC
fSCL
tWR
Clock Frequency
Write Time
400
10
100
10
400
10
kHz
ms
tW
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
Figure 9. AC Testing Input Output Waveforms
Table 7. AC Measurement Conditions
0.8V
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
CC
0.7V
0.3V
CC
CC
0.2V to 0.8V
CC
CC
0.2V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
CC
CC
AI00825
1
Table 8. Input Parameters (T = 25 °C, f = 400 kHz)
A
Symbol
CIN
Parameter
Test Condition
Min.
Max.
8
Unit
pF
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
CIN
6
pF
ZWCL
ZWCH
VIN < 0.5 V
5
70
kΩ
kΩ
V
IN > 0.7VCC
WC Input Impedance
500
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
ns
Note: 1. Sampled only, not 100% tested.
12/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
13/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 9. Ordering Information Scheme
Example:
M24C08
–
W
DW
1
T
Memory Capacity
Option
16
08
04
16 Kbit (2048 x 8)
8 Kbit (1024 x 8)
4 Kbit (512 x 8)
T
Tape and Reel Packing
Temperature Range
0 °C to 70 °C
1
02
01
2 Kbit (256 x 8)
1 Kbit (128 x 8)
1
6
3
–40 °C to 85 °C
–40 °C to 125 °C
Operating Voltage
blank 4.5 V to 5.5 V (400 kHz)
Package
W
R
S
2.5 V to 5.5 V (400 kHz)
1.8 V to 5.5 V (100 kHz)
1.8 V to 3.6 V (400 kHz)
BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width)
DW TSSOP8 (169 mil width)
Note: 1. Temperature range 1 available only on request.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 9. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
14/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 10. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min.
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min.
Symb.
Typ.
Max.
5.90
–
Typ.
Max.
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
Figure 11. PSDIP8 (BN)
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Note: 1. Drawing is not to scale.
15/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 12. SO8 narrow (MN)
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: 1. Drawing is not to scale.
16/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 12. TSSOP8 - 8 lead Thin Shrink Small Outline
mm
inches
Min.
Symb.
Typ.
Min.
Max.
1.10
0.15
0.95
0.30
0.20
3.10
6.50
4.50
–
Typ.
Max.
0.043
0.006
0.037
0.012
0.008
0.122
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
2.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.114
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
8
8
CP
0.08
0.003
Figure 13. TSSOP8 (DW)
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
17/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. Revision History
Date
Description of Revision
TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2
10-Dec-1999
18-Apr-2000
Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13
Extra labelling to Fig-2D
05-May-2000
SBGA package information removed to an annex document
-R range changed to being the -S range, and the new -R range added
23-Nov-2000
18/19
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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19/19
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