M24C02-WDW5P [STMICROELECTRONICS]
I2C/2-WIRE SERIAL EEPROM;
| 型号： | M24C02-WDW5P |
| 厂家： | 
ST |
| 描述： | I2C/2-WIRE SERIAL EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总37页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C08-W M24C08-R
M24C08-F
8-Kbit serial I²C bus EEPROM
Datasheet − production data
Features
2
■ Compatible with all I C bus modes:
– 400 kHz
– 100 kHz
■ Memory array:
TSSOP8 (DW)
169 mil width
– 8 Kbit (1 Kbyte) of EEPROM
– Page size: 16 bytes
■ Single supply voltage:
– M24C08-W: 2.5 V to 5.5 V
– M24C08-R: 1.8 V to 5.5 V
– M24C08-F: 1.7 V to 5.5 V
SO8 (MN)
150 mil width
■ Write:
– Byte Write within 5 ms
– Page Write within 5 ms
■ Operating temperature range: from -40 °C up
to +85 °C
■ Random and sequential Read modes
■ Write protect of the whole memory array
■ Enhanced ESD/Latch-Up protection
■ More than 1 million Write cycles
(1)
PDIP8 (BN)
■ More than 40-year data retention
■ Packages:
– RoHS compliant and halogen-free
®
(ECOPACK )
UFDFPN8
(MC)
WLCSP (CS)
December 2012
Doc ID 023924 Rev 1
1/37
This is information on a product in full production.
www.st.com
1
Contents
M24C08-W M24C08-R M24C08-F
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.1
2.6.2
2.6.3
2.6.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
5.1.2
5.1.3
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17
5.2
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1
5.2.2
5.2.3
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Contents
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
8
9
10
11
Doc ID 023924 Rev 1
3/37
List of tables
M24C08-W M24C08-R M24C08-F
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (M24C08-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (M24C08-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics (M24C08-F, device ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
100 kHz AC characteristics (I C Standard mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 27
SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 28
PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 29
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5-bump WLCSP package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thin 5-bump WLCSP package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20.
Table 21.
Table 22.
Table 23.
4/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Maximum R value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
C
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 28
Figure 15. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 29
Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 30
Figure 17. 5-bump WLCSP package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Thin 5-bump WLCSP package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 023924 Rev 1
5/37
Description
M24C08-W M24C08-R M24C08-F
1
Description
2
The M24C08 is an 8-Kbit I C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 1 K × 8 bits.
The M24C08-W can be accessed with a supply voltage from 2.5 V to 5.5 V, the M24C08-R
can be accessed with a supply voltage from 1.8 V to 5.5 V, and the M24C08-F can be
accessed with a supply voltage from 1.7 V to 5.5 V. All these devices operate with a clock
frequency of 400 kHz (or less), over an ambient temperature range of -40 °C / +85 °C.
Figure 1.
Logic diagram
6
##
%ꢆ
3$!
-ꢆꢇXXX
3#,
7#
6
33
-3ꢀꢁꢂꢃꢄ6ꢅ
Table 1.
Signal names
Signal name
Function
Direction
E2
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Input
I/O
SDA
SCL
WC
VCC
VSS
Input
Input
Figure 2.
8-pin package connections
.#
.#
%ꢆ
ꢅ
ꢆ
ꢀ
ꢇ
ꢃ
ꢄ
ꢈ
ꢉ
6
##
7#
3#,
3$!
6
33
-3ꢀꢁꢂꢃꢃ6ꢅ
1. NC: not connected.
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
6/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Description
Figure 3. WLCSP connections (top view, marking side, with balls on the underside)
VCC
WC
SDA
VSS
SCL
ai14908
1. The E2 input is not connected to a ball, therefore E2 input is decoded as “0” (see also Section 2.4: Write
Control (WC)).
Caution:
As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Doc ID 023924 Rev 1
7/37
Signal description
M24C08-W M24C08-R M24C08-F
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull-up resistor must be connected from Serial Data (SDA) to V (Figure 11
CC
indicates how to calculate the value of the pull-up resistor).
2.3
2.4
Chip Enable (E2)
This input signal is used to set the value that is to be looked for on the bit b3 of the device
select code. This input must be tied to V or V , to establish the device select code as
shown in Table 2. When not connected (left floating), this input is read as low (0).
CC
SS
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
2.5
VSS (ground)
V
is the reference for the V supply voltage.
CC
SS
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the V line with a suitable capacitor (usually of the order of
CC
10 nF to 100 nF) close to the V /V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (t ).
W
8/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Signal description
2.6.2
Power-up conditions
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V has reached the
CC
internal reset threshold voltage. This threshold is lower than the minimum V operating
CC
voltage (see Operating conditions in Section 8: DC and AC parameters). When V passes
CC
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until V reaches a valid and stable DC voltage within the
CC
specified [V (min), V (max)] range (see Operating conditions in Section 8: DC and AC
CC
CC
parameters).
In a similar way, during power-down (continuous decrease in V ), the device must not be
CC
accessed when V drops below V (min). When V drops below the threshold voltage,
CC
CC
CC
the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in V ), the device must be in the Standby Power
CC
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Doc ID 023924 Rev 1
9/37
Memory organization
M24C08-W M24C08-R M24C08-F
3
Memory organization
The memory is organized as shown below.
Figure 4.
Block diagram
7#
%ꢆ
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)ꢊ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
ꢅ PAGE
8 DECODER
-3ꢀꢁꢂꢃꢂ6ꢅ
10/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Device operation
4
Device operation
2
The device supports the I C protocol. This is summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
2
Figure 5.
I C bus protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Doc ID 023924 Rev 1
11/37
Device operation
M24C08-W M24C08-R M24C08-F
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
4.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
12/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Device operation
4.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2.
Device select code
Device type identifier(1)
Chip Enable address
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
A9
A8
RW
1. The most significant bit, b7, is sent first.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Doc ID 023924 Rev 1
13/37
Instructions
M24C08-W M24C08-R M24C08-F
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 6, and waits for the address
byte. The device responds to each address byte with an acknowledge bit, and then waits for
the data byte.
Table 3.
Address byte
A7
A6
A5
A4
A3
A2
A1
A0
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t is triggered. A Stop condition at any other time slot does not trigger the internal
W
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t ), the
W
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 7.
14/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Instructions
5.1.1
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 6.
Figure 6.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
ACK
Byte Write
Dev Select
Byte address
Data in
R/W
WC
ACK
ACK
ACK
ACK
Page Write
Dev Select
Byte address
Data in 1
Data in 2
Data in 3
R/W
WC (cont'd)
ACK
ACK
Page Write
(cont'd)
Data in N
AI02804c
Doc ID 023924 Rev 1
15/37
Instructions
M24C08-W M24C08-R M24C08-F
5.1.2
Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A9/A4, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 7. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 7.
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
NO ACK
Byte Write
Dev select
Byte address
Data in
R/W
WC
ACK
ACK
NO ACK
NO ACK
Data in 3
Page Write
Dev select
Byte address
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
Data in N
AI02803d
16/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Instructions
5.1.3
Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 8, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 8.
Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
ACK
NO
returned
First byte of instruction
YES
with RW = 0 already
decoded by the device
Next
Operation is
addressing the
memory
NO
YES
Send Address
and Receive ACK
ReStart
NO
YES
Stop
StartCondition
Data for the
Write cperation
Device select
with RW = 1
Continue the
Continue the
Random Read operation
Write operation
AI01847de
Doc ID 023924 Rev 1
17/37
Instructions
M24C08-W M24C08-R M24C08-F
5.2
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 9.
Read mode sequences
ACK
NO ACK
Current
Address
Read
Dev select
Data out
R/W
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev select *
Byte address
Dev select *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequentila
Current
Read
Dev select
Data out 1
R/W
ACK
ACK
ACK
R/W
ACK
Sequential
Random
Read
Dev select *
Byte address
Dev select *
Data out 1
R/W
ACK
NO ACK
Data out N
AI01942b
18/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Initial delivery state
5.2.1
5.2.2
5.2.3
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 9) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 9, without acknowledging the byte.
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
6
Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
Doc ID 023924 Rev 1
19/37
Maximum rating
M24C08-W M24C08-R M24C08-F
7
Maximum rating
Stressing the device outside the ratings listed in Table 4 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
°C
mA
V
TSTG
Lead temperature during soldering
PDIP-specific lead temperature during soldering
DC output current (SDA = 0)
Input or output range
see note(1)
TLEAD
-
260(2)
IOL
VIO
-
5
–0.50
–0.50
-
6.5
VCC
VESD
Supply voltage
6.5
V
Electrostatic pulse (Human Body model)(3)
4000
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. TLEAD max must not be applied for more than 10 s.
3. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω).
20/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 5.
Symbol
Operating conditions (voltage range W)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
–40
-
5.5
85
V
Ambient operating temperature
Operating clock frequency
°C
fC
400
kHz
Table 6.
Symbol
Operating conditions (voltage range R)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.8
–40
-
5.5
85
V
Ambient operating temperature
Operating clock frequency
°C
fC
400
kHz
Table 7.
Symbol
Operating conditions (voltage range F)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.7
–20
-
5.5
85
V
Ambient operating temperature
Operating clock frequency
°C
fC
400
kHz
Table 8.
Symbol
AC measurement conditions
Parameter
Min.
Max.
Unit
Cbus
Load capacitance
100
pF
ns
V
SCL input rise/fall time, SDA input fall time
Input levels
-
50
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference levels
V
Figure 10. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
)NPUT AND OUTPUT
4IMING REFERENCE LEVELS
ꢁꢋꢃ6
##
ꢁꢋꢄ6
##
ꢁꢋꢀ6
##
ꢁꢋꢆ6
##
-3ꢅꢂꢄꢄꢇ6ꢅ
Doc ID 023924 Rev 1
21/37
DC and AC parameters
M24C08-W M24C08-R M24C08-F
Table 9.
Symbol
Input parameters
Parameter(1)
Test condition
Min. Max. Unit
CIN
CIN
ZL
Input capacitance (SDA)
-
-
-
-
8
6
pF
pF
kΩ
kΩ
Input capacitance (other pins)
V
IN < 0.3 VCC
15
500
70
-
Input impedance (WC)
ZH
VIN > 0.7 VCC
1. Characterized only, not tested in production.
Table 10. Memory cell data retention
Parameter
Test condition
TA = 55 °C
Min.
40
Unit
Data retention(1)
Year
1. The data retention behavior is checked in production. The 40-year limit is defined from characterization and
qualification results.
Table 11. DC characteristics (M24C08-W, device grade 6)
Test conditions (in addition to those
Symbol
Parameter
Min.
Max.
Unit
in Table 5 and Table 8)
Input leakage current VIN = VSS or VCC, device in Standby
ILI
-
-
2
2
µA
µA
(SCL, SDA, E2)
mode
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
ILO
V
CC = 5 V, fc = 400 kHz
-
-
2(1)
1
mA
mA
ICC
Supply current (Read)
VCC = 2.5 V, fc = 400 kHz
Standby supply
current
Device not selected(2), VIN = VSS or
VCC, for 2.5 V < VCC < 5.5 V
ICC1
VIL
-
1
µA
V
Input low voltage
(SCL, SDA, WC)
–0.45
0.3 VCC
Input high voltage
(SCL, SDA, WC)
VIH
VOL
0.7 VCC VCC +1
V
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
Output low voltage
-
0.4
V
1. 2 mA for devices identified by process letter G or S.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
22/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
DC and AC parameters
Table 12. DC characteristics (M24C08-R, device grade 6)
Test conditions(1) (in addition
to those in Table 6 and
Table 8)
Symbol
Parameter
Min.
Max.
Unit
Input leakage current
(E2, SCL, SDA)
VIN = VSS or VCC, device in
Standby mode
ILI
-
-
-
-
2
2
µA
µA
mA
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
ICC
ICC1
Output leakage current
Supply current (Read)
Standby supply current
VCC = 1.8 V, fc= 400 kHz
0.8
1
Device not selected(2)
,
VIN = VSS or VCC, VCC = 1.8 V
2.5 V ≤ VCC
–0.45
–0.45
0.3 VCC
V
V
Input low voltage
(SCL, SDA, WC)
VIL
1.8 V ≤ VCC < 2.5 V
0.25 VCC
Input high voltage
(SCL, SDA, WC)
VIH
0.7 VCC
-
VCC+1
0.2
V
V
VOL
Output low voltage
IOL = 0.7 mA, VCC = 1.8 V
1. If the application uses the voltage range R device with 2.5 V ≥ Vcc < 5.5 V, please refer to Table 11 instead
of this table.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Table 13. DC characteristics (M24C08-F, device )
Test conditions(1) (in addition
Symbol
Parameter
to those in Table 7 and
Table 8)
Min.
Max.
Unit
Input leakage current
(E2, SCL, SDA)
VIN = VSS or VCC, device in
Standby mode
ILI
-
-
-
-
2
2
µA
µA
mA
µA
ILO
ICC
ICC1
Output leakage current
Supply current (Read)
Standby supply current
VOUT = VSS or VCC, SDA in Hi-Z
VCC = 1.7 V, fc= 400 kHz
0.8
1
Device not selected(2)
IN = VSS or VCC, VCC = 1.7 V
,
V
2.5 V ≤ VCC
–0.45
–0.45
0.3 VCC
V
V
Input low voltage
(SCL, SDA, WC)
VIL
1.7 V ≤ VCC < 2.5 V
0.25 VCC
Input high voltage
(SCL, SDA, WC)
VIH
0.7 VCC
-
VCC+1
0.2
V
V
VOL
Output low voltage
IOL = 0.7 mA, VCC = 1.7 V
1. If the application uses the voltage range F device with 2.5 V ≥ Vcc < 5.5 V, please refer to Table 11 instead
of this table.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 023924 Rev 1
23/37
DC and AC parameters
M24C08-W M24C08-R M24C08-F
Table 14. 400 kHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tF
Clock frequency
-
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
SDA (out) fall time
600
-
-
1300
20(2)
300
(1)
tQL1QL2
tXH1XH2
tXL1XL2
tDXCX
(3)
(3)
tR
Input signal rise time
Input signal fall time
(3)
(3)
tF
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
(4)
tCLQX
tDH
tAA
Data out hold time
100
-
-
(5)
tCLQV
Clock low to next data valid (access time)
900
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
600
600
600
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
tWR
1300
-
5
ns
ms
ns
Write time
-
-
Pulse width ignored (input filter on SCL and
SDA) - single glitch
(1)
tNS
100
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
4. The min value for tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the
undefined region of the falling edge SCL.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 11.
24/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
DC and AC parameters
2
(1)
Table 15. 100 kHz AC characteristics (I C Standard mode)
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
-
4
100
kHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
tCHCL
tHIGH Clock pulse width high
tLOW Clock pulse width low
-
tCLCH
4.7
-
-
tXH1XH2
tXL1XL2
tR
tF
tF
Input signal rise time
Input signal fall time
SDA fall time
1
-
300
(2)
tQL1QL2
tDXCX
tCLDX
-
300
tSU:DAT Data in setup time
tHD:DAT Data in hold time
250
0
-
-
(3)
tCLQX
tCLQV
tCHDL
tDH
tAA
Data out hold time
200
-
-
(4)
(5)
Clock low to next data valid (access time)
3450
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
4.7
4
-
-
-
tDLCL
tCHDH
4
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
tWR
4.7
-
5
µs
ms
ns
Write time
-
-
Pulse width ignored (input filter on SCL and
SDA), single glitch
(2)
tNS
100
1. Values recommended by the I2C bus Standard-mode specification for a robust design of the I2C bus
application. Note that the M24xxx devices decode correctly faster timings as specified in Table 14:
400 kHz AC characteristics.
2. Characterized only.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, taking into account the Rbus × Cbus time constant specific to the end application.
5. For a reStart condition, or following a Write cycle.
Doc ID 023924 Rev 1
25/37
DC and AC parameters
Figure 11. Maximum R
M24C08-W M24C08-R M24C08-F
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz
C
ꢅꢁꢁ
4HE 2
X # TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢇꢁꢁ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢋ
6
##
ꢅꢁ
2
BUS
(ERE 2
BUS
§ # ꢏ ꢅꢆꢁ NS
BUS
ꢇ K½
3#,
3$!
)£# BUS
MASTER
-ꢆꢇXXX
ꢅ
ꢀꢁ P&
#
BUS
ꢅꢁ
ꢅꢁꢁ
"US LINE CAPACITOR ꢌP&ꢍ
ꢅꢁꢁꢁ
AIꢅꢇꢄꢂꢈB
Figure 12. AC waveforms
T8,ꢅ8,ꢆ
T#(#,
T8(ꢅ8(ꢆ
3#,
T#,#(
T$,#,
T8,ꢅ8,ꢆ
3$! )N
T#($,
3TART
CONDITION
T#,$8
T$8#(
3$!
#HANGE
T8(ꢅ8(ꢆ
T#($( T$($,
3TOP
3TART
3$!
)NPUT
CONDITION
CONDITION
3#,
3$! )N
T7
7RITE CYCLE
T#($(
T#($,
3TOP
CONDITION
3TART
CONDITION
T#(#,
3#,
T#,16
T#,18
$ATA VALID
T1,ꢅ1,ꢆ
$ATA VALID
3$! /UT
!)ꢁꢁꢄꢂꢉF
26/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 023924 Rev 1
27/37
Package mechanical data
M24C08-W M24C08-R M24C08-F
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 17. SO8N – 8-lead plastic small outline, 150 mils body width, package data
millimeters
inches (1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
1.750
0.250
0.0689
0.0098
A1
A2
b
0.100
1.250
0.280
0.170
0.0039
0.0492
0.0110
0.0067
0.480
0.230
0.100
5.000
6.200
4.000
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
c
ccc
D
4.900
6.000
3.900
1.270
4.800
5.800
3.800
0.1929
0.2362
0.1535
0.0500
0.1890
0.2283
0.1496
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
L
0.400
1.270
0.0157
0.0500
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
28/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Package mechanical data
Figure 15. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
1. Drawing is not to scale.
2. Not recommended for new designs.
Table 18. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
5.33
0.2098
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.0150
0.1150
0.0142
0.0449
0.0079
0.3551
0.3000
0.2402
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.1299
0.0181
0.0598
0.0098
0.3650
0.3098
0.2500
0.1000
0.3000
0.1949
0.0220
0.0701
0.0142
0.4000
0.3252
0.2799
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.4299
0.1500
3.30
2.92
0.1299
0.1150
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 023924 Rev 1
29/37
Package mechanical data
M24C08-W M24C08-R M24C08-F
Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline
E
B
$
,ꢅ
,ꢀ
0IN ꢅ
%ꢆ
+
%
,
!
$ꢆ
EEE
!ꢅ
1. Drawing is not to scale.
:7?-%E6ꢆ
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 19. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.020
0.250
2.000
0.450
0.000
0.200
1.900
1.200
2.900
1.200
0.600
0.050
0.300
2.100
1.600
3.100
1.600
0.0217
0.0008
0.0098
0.0787
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
A1
b
D
D2 (rev MC)
E
3.000
0.500
0.1181
0.0197
E2 (rev MC)
e
K (rev MC)
0.300
0.300
0.0118
0.0118
L
L1
0.500
0.150
0.0197
0.0059
L3
0.300
0.080
0.0118
0.0031
eee(2)
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
30/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Figure 17. 5-bump WLCSP package outline
Package mechanical data
/RIENTATION REFERENCE
/RIENTATION REFERENCE
BBB
:
Eꢅ
$
Eꢆ
'
X
9
!
$ETAIL !
E
"
#
%
&
ꢅ
ꢆ
ꢀ
!ꢆ
!
7AFER BACK SIDE
"UMP
3IDE VIEW
"UMP SIDE
$ETAIL !
ROTATED BY ꢂꢁ
!ꢅ
CCC -
DDD -
8 9
:
:
B
ꢅ#K?-%?6ꢅ
1. Drawing is not to scale.
Doc ID 023924 Rev 1
31/37
Package mechanical data
M24C08-W M24C08-R M24C08-F
inches(1)
Table 20. 5-bump WLCSP package data
millimeters
Min
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
0.545
0.190
0.355
0.270
1.215
1.025
0.400
0.693
0.346
0.313
0.261
0.490
0.600
0.0215
0.0075
0.0140
0.0106
0.0478
0.0404
0.0157
0.0273
0.0136
0.0123
0.0103
0.0192
0.0236
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D
1.340
0.0528
E
1.150
-
-
-
-
-
-
0.0453
e
-
-
-
-
-
-
-
-
-
-
e1
e2
F
G
N (number
of terminals)
5
aaa
bbb
ccc
ddd
eee
0.110
0.110
0.110
0.060
0.060
-
-
-
-
-
-
-
-
-
-
0.0043
0.0043
0.0043
0.0024
0.0024
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
32/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Figure 18. Thin 5-bump WLCSP package outline
Package mechanical data
/RIENTATION REFERENCE
/RIENTATION REFERENCE
BBB
:
Eꢅ
$
Eꢆ
'
X
9
!
$ETAIL !
E
"
#
%
&
ꢅ
ꢆ
ꢀ
!ꢆ
!
3IDE VIEW
7AFER BACK SIDE
"UMP
"UMP SIDE
$ETAIL !
ROTATED BY ꢂꢁ
!ꢅ
CCC -
DDD -
8 9
:
:
B
ꢌ6?-%?6ꢆ
1. Drawing is not to scale.
Doc ID 023924 Rev 1
33/37
Package mechanical data
M24C08-W M24C08-R M24C08-F
inches(1)
Table 21. Thin 5-bump WLCSP package data
millimeters
Min
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
0.300
0.100
0.200
0.160
1.215
1.025
0.400
0.693
0.346
0.313
0.261
0.270
0.330
0.0118
0.0039
0.0079
0.0063
0.0478
0.0404
0.0157
0.0273
0.0136
0.0123
0.0103
0.0106
0.0130
-
-
-
-
-
-
-
-
-
-
D
1.340
0.0528
0.0453
E
1.150
e
-
-
-
-
-
e1
e2
F
G
N
5
aaa
bbb
ccc
ddd
eee
0.110
0.110
0.110
0.060
0.060
-
-
-
-
-
-
-
-
-
-
0.0043
0.0043
0.0043
0.0024
0.0024
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
34/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Part numbering
10
Part numbering
Table 22. Ordering information scheme
Example:
M24C08
W
MC 6
T
P
Device type
M24 = I2C serial access EEPROM
Device function
C08 = 8 Kbit (1 K x 8 bit)
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
BN = PDIP8(1)(2)
MN = SO8 (150 mil width)(3)
DW = TSSOP8 (169 mil width)(3)
MC = UFDFPN8 (MLP8)(3)
CS = Standard WLCSP (chip scale package)(3)
CT = Thin WLCSP (chip scale package)(3)
Device grade
5 = Consumer: device tested with standard test flow over –20 to 85°C
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
1. RoHS-compliant (ECOPACK1®)
2. Not recommended for new designs.
3. RoHS-compliant and halogen-free (ECOPACK2®)
Doc ID 023924 Rev 1
35/37
Revision history
M24C08-W M24C08-R M24C08-F
11
Revision history
Table 23. Document revision history
Date
Revision
Changes
New single product M24C08 datasheet resulting from splitting the
previous datasheet M24C08-x M24C04-x M24C02-x M24C01-x
(revision 18) into separate datasheets.
17-Dec-2012
1
36/37
Doc ID 023924 Rev 1
M24C08-W M24C08-R M24C08-F
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 023924 Rev 1
37/37
相关型号：
M24C02-WDW5TG
256X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.169 INCH, ROHS COMPLIANT, TSSOP-8
STMICROELECTR
M24C02-WDW5TP
256X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.169 INCH, ROHS COMPLIANT, TSSOP-8
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明