M24C08-TMN6T [STMICROELECTRONICS]
8KX1 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8;
| 型号： | M24C08-TMN6T |
| 厂家： | 
ST |
| 描述： | 8KX1 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总17页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C16, M24C08
M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
2
■ Two Wire I C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
■ Hardware Write Control
8
1
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
PSDIP8 (BN)
0.25 mm frame
■ Automatic Address Incrementing
8
8
■ Enhanced ESD/Latch-Up Behaviour
■ 1 Million Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
1
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are fabricated with STMi-
croelectronics’
High
Endurance,
Single
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of
40 years. The memories are organised as 2048/
1024 x 8 bit (M24C16, M24C08) and 512/256/128
x 8 bit (M24C04, M24C02, M24C01), and operate
with a power supply down to 2.5 V (for the -W ver-
Figure 1. Logic Diagram
V
CC
3
Table 1. Signal Names
E0-E2
SDA
E0, E1, E2
SDA
Chip Enable Inputs
M24Cxx
Serial Data/Address Input/
Output
SCL
WC
SCL
WC
Serial Clock
Write Control
Supply Voltage
Ground
V
V
CC
SS
V
SS
AI02033
March 1999
1/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
Figure 2C. Standard-TSSOP Connections
M24C01/02/04
M24C01/02/04 - W
M24C01/02/04 - R
M24C08/16 - R
M24Cxx
M24Cxx - W
M24Cxx - R
E0
E1
E2
1
2
3
4
8
V
CC
WC
E0
E1
E2
1
2
3
4
8
V
CC
WC
7
7
6
5
SCL
SDA
6
5
SCL
SDA
V
SS
V
SS
AI02034B
AI02036B
Note: 1. xx = 01, 02, 04, 08 or 16
2. Pin 1 is Not Connected for 4 Kbit devices
3. Pins 1 and 2 are Not Connected for 8 Kbit devices
4. Pins 1, 2 and 3 are Not Connected for 16 Kbit devices
Note: 1. Pin 1 is Not Connected for 4 Kbit devices
2. Pins 1 and 2 are Not Connected for 8 Kbit devices
3. Pins 1, 2 and 3 are Not Connected for 16 Kbit devices
Figure 2B. SO Connections
Figure 2D. Turned-TSSOP Connections
M24Cxx
M24Cxx - W
M24Cxx - R
M24C08/16 - T
M24C08/16 - TW
WC
1
2
3
4
8
SCL
SDA
E0
E1
E2
1
2
3
4
8
V
CC
WC
V
7
CC
NC
7
6
5
V
SS
E2/NC
6
5
SCL
SDA
NC
V
SS
AI02216B
AI02035B
Note: 1. xx = 01, 02, 04, 08 or 16
Note: 1. NC = Not Connected
2. Pin 1 is Not Connected for 4 Kbit devices
3. Pins 1 and 2 are Not Connected for 8 Kbit devices
4. Pins 1, 2 and 3 are Not Connected for 16 Kbit devices
2. Pin 5 is Not Connected for 16 Kbit devices
1
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature
Value
Unit
°C
-40 to 125
-65 to 150
TSTG
Storage Temperature
°C
PSDIP8: 10 sec
SO8: 40 sec
260
215
TLEAD
Lead Temperature during Soldering
°C
TSSOP8: t.b.c.
t.b.c.
VIO
Input or Output range
Supply Voltage
-0.6 to 6.5
-0.3 to 6.5
4000
V
V
V
VCC
2
Electrostatic Discharge Voltage (Human Body model)
VESD
3
500
V
Electrostatic Discharge Voltage (Machine model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
3. EIAJ IC-121 (Condition C) (200 pF, 0 Ω)
2/17
M24C16, M24C08, M24C04, M24C02, M24C01
sion of each device), and down to 1.8 V (for the -R
version of each device).
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages.
all operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
These memory devices are compatible with the
I C memory standard. This is a two wire serial in-
2
terface that uses a bi-directional data bus and se-
rial clock. The memory carries a built-in 4-bit
unique Device Type Identifier code (1010) in ac-
2
the SCL line to V . (Figure 3 indicates how the
cordance with the I C bus definition.
The memory behaves as a slave device in the I C
CC
2
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
When writing data to the memory, the memory in-
th
serts an acknowledge bit during the 9 bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
to V . (Figure 3 indicates how the value of the
CC
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code (but
see the description of memory addressing, on
page 5, for more details). These inputs may be
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
driven dynamically or tied to V
or V to estab-
held active until the V
voltage has reached the
CC
SS
CC
lish the device select code (but note that the V
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
IL
and V levels for the inputs are CMOS compati-
IH
ble, not TTL compatible).
mand. In the same way, when V drops from the
CC
operating voltage, below the POR threshold value,
2
Figure 3. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/17
M24C16, M24C08, M24C04, M24C02, M24C01
2
Figure 4. I C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V ) or disable (WC=V )
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
IL
IH
V , and write operations are allowed.
IL
Start Condition
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
DEVICE OPERATION
The memory device supports the I C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
2
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
4/17
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 3. Device Select Code
Device Type Identifier
Chip Enable
RW
b0
b7
b6
0
b5
1
b4
0
b3
E2
b2
E1
E1
E1
A9
A9
b1
E0
E0
A8
A8
A8
M24C01 Select Code
M24C02 Select Code
M24C04 Select Code
M24C08 Select Code
M24C16 Select Code
1
1
1
1
1
RW
RW
RW
RW
RW
0
1
0
E2
0
1
0
E2
0
1
0
E2
0
1
0
A10
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent high significant bits of the address.
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Acknowledge Bit (ACK)
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a sin-
gle I C bus. Each one is given a unique 3-bit code
on its Chip Enable inputs. When the Device Se-
lect Code is received on the SDA bus, the memory
only responds if the Chip Select Code is the same
as the pattern applied to its Chip Enable pins.
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9 clock
pulse period, the receiver pulls the SDA bus low to
2
th
acknowledge the receipt of the eight data bits.
Data Input
Those devices with larger memory capacities (the
M24C16, M24C08) need more address bits. E0 is
not available for use on devices that need to use
address line A8; E1 is not available for devices
that need to use address line A9, and E2 is not
available for devices that need to use address line
A10 (see Figure 2A to Figure 2D for details). Using
the E0, E1 and E2 inputs pins, up to eight M24C02
(or M24C01), four M24C04, two M24C08 or one
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
2
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
M24C16 device can be connected to one I C bus.
In each case, and in the hybrid cases, this gives a
total memory capacity of 16 Kbits, 2 KBytes (ex-
cept where M24C01 devices are used).
Table 4. Operating Modes
1
Mode
RW bit
‘1’
Bytes
Initial Sequence
WC
X
Current Address Read
1
START, Device Select, RW = ‘1’
‘0’
X
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
Random Address Read
1
‘1’
X
Sequential Read
Byte Write
‘1’
X
≥ 1
1
‘0’
VIL
VIL
Page Write
‘0’
≤ 16
START, Device Select, RW = ‘0’
Note: 1. X = VIH or VIL.
5/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
R/W
WC
ACK
ACK
NO ACK
NO ACK
DATA IN 3
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1 DATA IN 2
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI02803B
th
The 8 bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
th
ing the 9 bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the address byte) will not
modify the memory contents, and the accompany-
ing data bytes will not be acknowledged (as shown
in Figure 5).
Byte Write
In the Byte Write mode, after the Device Select
Code and the address, the master sends one data
byte. If the addressed location is write protected by
the WC pin, the memory replies with a NoAck, and
the location is not modified. If, instead, the WC pin
has been held at 0, as shown in Figure 6, the
6/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
DATA IN 3
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI02804
memory replies with an Ack. The master termi-
nates the transfer by generating a STOP condi-
tion.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10 bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
th
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll-
over’ occurs. Data starts to become overwritten (in
a way not formally specified in this data sheet).
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
The master sends from one up to 16 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 4 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
7/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by M24xxx
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01847
Minimizing System Delays by Polling On ACK
Read Operations
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
Read operations are performed independently of
the state of the WC pin.
Random Address Read
mum write time (t ) is shown in Table 6, but the
w
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
8/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Read Mode Sequences
ACK
NO ACK
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
st
rd
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from the
start of the memory block.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
th
byte read, for an acknowledgment during the 9
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its standby state.
9/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 5. DC Characteristics
(T = 0 to 70 °C, or -40 to 85 °C; V = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
CC
(T = 0 to 70 °C, or -40 to 85 °C; V = 1.8 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
0 V ≤ VIN ≤ VCC
± 2
µA
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
± 2
2
µA
mA
mA
mA
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
-W series:
-R series:
1
ICC
Supply Current
c
1
V
CC =1.8V, f =400kHz (rise/fall time < 30ns)
c
0.8
Supply Current
(Stand-by)
ICC1
ICC2
ICC3
VIL
VIN = VSS or VCC , VCC = 5 V
1
µA
µA
µA
V
Supply Current
(Stand-by)
V
IN = VSS or VCC , VCC = 2.5 V
IN = VSS or VCC , VCC = 1.8 V
-W series:
-R series:
0.5
Supply Current
(Stand-by)
1
V
0.1
Input Low Voltage
(E0, E1, E2, SCL, SDA)
0.3 VCC
VCC+1
- 0.3
Input High Voltage
(E0, E1, E2, SCL, SDA)
VIH
0.7VCC
V
VIL
VIH
Input Low Voltage (WC)
Input High Voltage (WC)
- 0.3
0.5
VCC+1
0.4
V
V
V
V
V
0.7VCC
I
OL = 3 mA, VCC = 5 V
Output Low
I
OL = 2.1 mA, VCC = 2.5 V
-W series:
-R series:
0.4
VOL
Voltage
1
IOL = 1 mA, VCC = 1.8 V
0.4
Note: 1. This is preliminary data.
10/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 6. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01
V
=2.5 to 5.5 V
CC
=1.8 to 3.6 V
V
=4.5 to 5.5 V
V
CC
CC
T =0 to 70°C or
Symbol
Alt.
Parameter
T =0 to 70°C or T =0 to 70°C or
A
Unit
A
A
4
-40 to 85°C
-40 to 85°C
-40 to 85°C
Min
Max
300
300
300
300
Min
Max
300
300
300
300
Min
Max
300
300
300
300
tR
tF
tR
tF
Clock Rise Time
ns
ns
ns
ns
ns
ns
ns
µs
µs
tCH1CH2
tCL1CL2
Clock Fall Time
SDA Rise Time
SDA Fall Time
2
20
20
20
20
20
20
tDH1DH2
2
tDL1DL2
1
tSU:STA Clock High to Input Transition
600
600
600
0
600
600
600
0
600
600
600
0
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tHIGH
Clock Pulse Width High
tHD:STA
Input Low to Clock Low (START)
tHD:DAT Clock Low to Input Transition
tLOW Clock Pulse Width Low
1.3
1.3
1.3
Input Transition to Clock
Transition
tDXCX
tCHDH
tDHDL
tSU:DAT
100
600
1.3
100
600
1.3
100
600
1.3
ns
ns
µs
ns
ns
tSU:STO Clock High to Input High (STOP)
Input High to Input Low (Bus
Free)
tBUF
3
tAA
tDH
Clock Low to Data Out Valid
200
200
900
200
200
900
200
200
900
tCLQV
Data Out Hold Time After Clock
Low
tCLQX
fC
fSCL
tWR
Clock Frequency
Write Time
400
5
400
10
400
10
kHz
ms
tW
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
Figure 9. AC Testing Input Output Waveforms
Table 7. AC Measurement Conditions
0.8V
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
CC
0.7V
0.3V
CC
CC
0.2V to 0.8V
CC
CC
0.2V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
CC
CC
AI00825
11/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795B
1
Table 8. Input Parameters (T = 25 °C, f = 400 kHz)
A
Symbol
CIN
Parameter
Test Condition
Min.
Max.
8
Unit
pF
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
CIN
6
pF
ZWCL
ZWCH
tNS
VIN < 0.3VCC
VIN > 0.7VCC
5
20
kΩ
kΩ
WC Input Impedance
500
Low Pass Filter Input Time
Constant (SCL and SDA)
200
500
ns
Note: 1. Sampled only, not 100% tested.
12/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 9. Ordering Information Scheme
Example:
M24C08
–
T
W
DW
1
T
Memory Capacity
Option
16
08
04
02
01
16 Kbit (2048 x 8)
8 Kbit (1024 x 8)
4 Kbit (512 x 8)
2 Kbit (256 x 8)
1 Kbit (128 x 8)
T
Tape and Reel Packing
Temperature Range
0 °C to 70 °C
1
1
6
–40 °C to 85 °C
TSSOP Pin-Out
Standard (as shown in Figure 2C) for:
M24C01, M24C01-W, M24C01-R,
blank M24C02, M24C02-W, M24C02-R,
M24C04, M24C04-W, M24C04-R,
M24C08-R, M24C16-R.
Turned (as shown in Figure 2D) for
T
M24C08-T, M24C08-TW,
M24C16-T, M24C16-TW
Operating Voltage
Package
blank 4.5 V to 5.5 V
BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width)
W
R
2.5 V to 5.5 V
1.8 V to 3.6 V
TSSOP8 (169 mil width)
DW
Note: 1. Temperature range 1 available only on request.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 9. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
13/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 10. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
inches
Min.
Symb.
Typ.
Min.
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
Max.
5.90
–
Typ.
Max.
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
Figure 11. PSDIP8 (BN)
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Note: 1. Drawing is not to scale.
14/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 12. SO8 narrow (MN)
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: 1. Drawing is not to scale.
15/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 12. TSSOP8 - 8 lead Thin Shrink Small Outline
mm
inches
Min.
Symb.
Typ.
Min.
Max.
1.10
0.15
0.95
0.30
0.20
3.10
6.50
4.50
–
Typ.
Max.
0.043
0.006
0.037
0.012
0.008
0.122
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
2.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.114
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
8
8
CP
0.08
0.003
Figure 13. TSSOP8 (DW)
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
16/17
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 1999 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore -
Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
17/17
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
©2020 ICPDF网 联系我们和版权申明