M24C16-SEA6T [STMICROELECTRONICS]
2KX8 I2C/2-WIRE SERIAL EEPROM, PBGA5, 0.075 INCH, SBGA-5;
| 型号： | M24C16-SEA6T |
| 厂家： | 
ST |
| 描述： | 2KX8 I2C/2-WIRE SERIAL EEPROM, PBGA5, 0.075 INCH, SBGA-5 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总21页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C16, M24C08
M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
2
■ Two Wire I C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 5.5V for M24Cxx-R
– 1.8V to 3.6V for M24Cxx-S
■ Write Control Input
SBGA
SBGA5 (EA)
75 mil width
8
1
PDIP8 (BN)
0.25 mm frame
■ BYTE and PAGE WRITE (up to 16 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
8
8
■ Enhanced ESD/Latch-Up Behavior
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
1
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
DESCRIPTION
2
These I C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 bit
(M24C16, M24C08, M24C04, M24C02, M24C01),
and operate with a power supply down to 2.5 V (for
the -W version of each device), and down to 1.8 V
(for the -R and -S versions of each device).
Figure 1. Logic Diagram
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small
Outline packages. The M24C16-S is also
available in a Chip Scale package.
V
CC
3
E0-E2
SDA
Table 1. Signal Names
M24Cxx
SCL
WC
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
SCL
V
WC
SS
AI02033
V
V
CC
SS
February 2001
1/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
M24Cxx
16Kb/8Kb/4Kb/2Kb
NC / NC / NC/ E0
NC / NC/ E1/ E1
NC/ E2/ E2/ E2
/1Kb
/ E0
/ E1
/ E2
1
2
3
4
8
7
6
5
V
CC
WC
SCL
SDA
V
SS
AI02034D
Note: 1. NC = Not Connected
Figure 2B. SO Connections
M24Cxx
16Kb/8Kb/4Kb/2Kb
/1Kb
/ E0
/ E1
/ E2
NC / NC / NC/ E0
NC / NC/ E1/ E1
NC/ E2/ E2/ E2
1
2
3
4
8
7
6
5
V
CC
WC
SCL
SDA
V
SS
AI02035D
Note: 1. NC = Not Connected
Figure 2C. TSSOP Connections
M24Cxx
16Kb/8Kb/4Kb/2Kb
NC / NC / NC/ E0
NC / NC/ E1/ E1
NC/ E2/ E2/ E2
/1Kb
/ E0
/ E1
/ E2
1
8
7
6
5
V
CC
WC
2
3
4
SCL
SDA
V
SS
AI02036D
Note: 1. NC = Not Connected
Figure 2D. SBGA Connections (top view, marking side, with balls on the underside)
M24C16
WC
V
CC
Ball "1"
SDA
SCL
V
SS
AI02796E
2/21
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
TA
Ambient Operating Temperature
–40 to 125
–65 to 150
TSTG
Storage Temperature
°C
PDIP8: 10 seconds
260
235
235
Lead Temperature during
Soldering
2
TLEAD
SO8: 20 seconds (max)
°C
2
TSSOP8: 20 seconds (max)
VIO
Input or Output range
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
V
V
VCC
4000
3
VESD
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
When writing data to the memory, the device
inserts an acknowledge bit during the 9 bit time,
2
th
These devices are compatible with the I C
memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
2
Identifier code (1010) in accordance with the I C
bus definition.
The device behaves as a slave in the I C protocol,
2
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 3),
terminated by an acknowledge bit.
Power On Reset: V
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
has reached the POR
CC
2
Figure 3. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
SCL
MASTER
C
BUS
8
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/21
M24C16, M24C08, M24C04, M24C02, M24C01
2
Figure 4. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
this method of synchronization is not employed,
and so the pull-up resistor is not necessary,
provided that the bus master has a push-pull
(rather than open drain) output.
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
drops from the operating
CC
voltage, below the POR threshold value, all
operations are disabled and the device will not
Serial Data (SDA)
respond to any command. A stable and valid V
CC
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
must be applied before applying any logic signal.
be connected from Serial Data (SDA) to V
(Figure 3 indicates how the value of the pull-up
resistor can be calculated).
.
CC
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to V or V , to establish the
CC
SS
connected from Serial Clock (SCL) to V . (Figure
CC
Device Select Code.
3 indicates how the value of the pull-up resistor
can be calculated). In most applications, though,
4/21
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 3. Device Select Code
Device Type Identifier
Chip Enable
RW
b0
b7
b6
0
b5
1
b4
0
b3
E2
b2
E1
E1
E1
A9
A9
b1
E0
E0
A8
A8
A8
M24C01 Select Code
M24C02 Select Code
M24C04 Select Code
M24C08 Select Code
M24C16 Select Code
1
1
1
1
1
RW
RW
RW
RW
RW
0
1
0
E2
0
1
0
E2
0
1
0
E2
0
1
0
A10
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
Write Control (WC)
Start Condition
This input signal is useful for protecting the entire
contents of the memory from inadvertent write
operations. Write operations are disabled to the
entire memory array when Write Control (WC) is
driven High. When unconnected, the signal is
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
internally read as V , and Write operations are
IL
allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and
driven High.
A
Stop condition terminates
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
the internal EEPROM Write cycle.
DEVICE OPERATION
The device supports the I C protocol. This is
2
summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a
receiver. The device that controls the data transfer
is known as the bus master, and the other as the
slave device. A data transfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M24Cxx
device is always a slave in all communication.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
th
During the 9 clock pulse period, the receiver pulls
Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.
Table 4. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = ‘1’
X
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 16
START, Device Select, RW = ‘0’
Note: 1. X = VIH or VIL.
5/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
NO ACK
DATA IN
Byte Write
DEV SEL
BYTE ADDR
R/W
WC
ACK
ACK
NO ACK
NO ACK
DATA IN 3
Page Write
DEV SEL
BYTE ADDR
DATA IN 1 DATA IN 2
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
DATA IN N
AI02803C
Data Input
Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8 bit is the Read/Write bit (RW). This bit is
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is
driven Low.
th
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
th
on Serial Data (SDA) during the 9 bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Devices with larger memory capacities (the
M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not
available for devices that need to use address line
A9, and E2 is not available for devices that need to
use address line A10 (see Figures 2A to 2D and
Table 3 for details). Using the E0, E1 and E2
inputs pins, up to eight M24C02 (or M24C01), four
M24C04, two M24C08 or one M24C16 device can
When the Device Select Code is received on
Serial Data (SDA), the device only responds if the
2
be connected to one I C bus. In each case, and in
6/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
DATA IN 3
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI02804
the hybrid cases, this gives a total memory
capacity of 16 Kbits, 2 KBytes (except where
M24C01 devices are used).
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not
respond to any requests.
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
6, and waits for an address byte. The device
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a
period of time from the Start condition until the end
of the two address bytes) will not modify the
memory contents, and the accompanying data
bytes are not acknowledged, as shown in Figure 5.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If,
instead, the addressed location is not Write-
protected, the device replies with Ack. The bus
master terminates the transfer by generating a
Stop condition, as shown in Figure 6.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10 bit” time
slot), either at the end of a Byte Write or a Page
th
7/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
that is, the most significant memory address bits
(b7-b4) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an
implementation dependent way.
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device
disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory
cells. The maximum Write time (t ) is shown in
w
Tables 8A and 8B, but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory
location are not modified, and each data byte is
followed by a NoAck. After each byte is
transferred, the internal byte address counter (the
The sequence, as shown in Figure 7, is:
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
4
least significant address bits only) is
incremented. The transfer is terminated by the bus
master generating a Stop condition.
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
8/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Read Mode Sequences
ACK
NO ACK
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
st
rd
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.
first byte of this instruction having been sent
during Step 1).
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Read Operations
Current Address Read
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 8) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device
Select Code with the RW bit set to 1. The device
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master
9/21
M24C16, M24C08, M24C04, M24C02, M24C01
After the last memory address, the address
counter ‘rolls-over’, and the device continues to
output data from memory address 00h.
terminates the transfer with a Stop condition, as
shown in Figure 8, without acknowledging the
byte.
Acknowledge in Read Mode
Sequential Read
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9 bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device
terminates the data transfer and switches to its
Stand-by mode.
This operation can be used after a Current
Address Read or a Random Address Read. The
bus master does acknowledge the data byte
output, and sends additional clock pulses so that
the device continues to output the next byte in
sequence. To terminate the stream of bytes, the
bus master must not acknowledge the last byte,
and must generate a Stop condition, as shown in
Figure 8.
th
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
Table 5. AC Measurement Conditions
Figure 9. AC Testing Input Output Waveforms
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.8V
CC
0.7V
CC
0.2V to 0.8V
CC
CC
0.3V
CC
0.2V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
CC
CC
AI00825
1
Table 6. Input Parameters (T = 25 °C, f = 400 kHz)
A
Symbol
CIN
Parameter
Test Condition
Min.
Max.
8
Unit
pF
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
CIN
6
pF
ZWCL
ZWCH
VIN < 0.5 V
5
70
kΩ
kΩ
V
IN > 0.7VCC
WC Input Impedance
500
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
ns
Note: 1. Sampled only, not 100% tested.
10/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table 7A. DC Characteristics
(T = 0 to 70 °C, or –40 to 85 °C; V = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
CC
(T = 0 to 70 °C, or –40 to 85 °C; V = 1.8 to 5.5 V or 1.8 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
Output Leakage Current
± 2
2
µA
mA
mA
mA
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
VCC =2.5V, f =400kHz (rise/fall time < 30ns)
-W series:
-R series:
-S series:
1
c
ICC
Supply Current
1
V
CC =1.8V, f =100kHz (rise/fall time < 30ns)
c
0.8
1
V
CC =1.8V, f =400kHz (rise/fall time < 30ns)
mA
µA
µA
µA
c
0.8
VIN = VSS or VCC , VCC = 5 V
1
V
IN = VSS or VCC , VCC = 2.5 V
-W series:
-R series:
0.5
Supply Current
(Stand-by)
ICC1
1
VIN = VSS or VCC , VCC = 1.8 V
0.3
1
V
IN = VSS or VCC , VCC = 1.8 V
4.5 V ≤ VCC ≤ 5.5 V
-S series:
µA
V
0.1
– 0.3
– 0.3
– 0.3
0.3 VCC
0.3 VCC
-W series:
-R series:
-S series:
2.5 V ≤ VCC ≤ 5.5 V
V
Input Low
Voltage
(E0, E1, E2,
SCL, SDA)
1
1.8 V ≤ VCC < 2.5 V
V
0.25 VCC
VIL
1
2.5 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC ≤ 3.6 V
– 0.3
– 0.3
V
V
0.3 VCC
1
0.3 VCC
Input High Voltage
VIH
0.7VCC
VCC+1
V
(E0, E1, E2, SCL, SDA)
Input Low Voltage (WC)
Input High Voltage (WC)
VIL
VIH
– 0.3
0.5
VCC+1
0.4
V
V
V
V
V
0.7VCC
IOL = 3 mA, VCC = 5 V
I
OL = 2.1 mA, VCC = 2.5 V
-W series:
0.4
Output Low
Voltage
VOL
1
-R series:
-S series:
IOL = 0.7 mA, VCC = 1.8 V
0.2
1
I
OL = 0.7 mA, VCC = 1.8 V
V
0.2
Note: 1. This is preliminary data.
11/21
M24C16, M24C08, M24C04, M24C02, M24C01
1
Table 7B. DC Characteristics
(T = –40 to 125 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
± 2
Unit
µA
ILI
Input Leakage Current (SCL, SDA)
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
± 2
µA
V
CC=5V, f =400kHz
c
ICC
Supply Current
3
mA
(rise/fall time < 30ns)
ICC1
VIL
VIN = VSS or VCC , VCC = 5 V
Supply Current (Stand-by)
5
µA
V
0.3 VCC
VCC+1
0.5
Input Low Voltage (E0, E1, E2, SCL, SDA)
Input High Voltage (E0, E1, E2, SCL, SDA)
Input Low Voltage (WC)
– 0.3
0.7VCC
– 0.3
VIH
VIL
V
V
VIH
VOL
Input High Voltage (WC)
0.7VCC
VCC+1
0.4
V
I
OL = 3 mA, VCC = 5 V
Output Low Voltage
V
Note: 1. This is preliminary data.
Table 8A. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01
V
=4.5 to 5.5 V
CC
V
=4.5 to 5.5 V;
CC
Symbol
Alt.
Parameter
T =0 to 70°C or
Unit
A
4
T =–40 to 125°C
A
–40 to 85°C
Min
Max
300
300
300
Min
Max
300
300
300
tCH1CH2
tCL1CL2
tR
tF
tR
tF
Clock Rise Time
ns
ns
ns
Clock Fall Time
SDA Rise Time
SDA Fall Time
2
20
20
tDH1DH2
2
20
600
600
600
0
300
20
600
600
600
0
300
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
kHz
ms
tDL1DL2
1
tSU:STA Clock High to Input Transition
tHIGH Clock Pulse Width High
tHD:STA Input Low to Clock Low (START)
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
tHD:DAT
tLOW
Clock Low to Input Transition
Clock Pulse Width Low
1.3
100
600
1.3
200
200
1.3
100
600
1.3
200
200
tSU:DAT
Input Transition to Clock Transition
tSU:STO Clock High to Input High (STOP)
tBUF
tAA
Input High to Input Low (Bus Free)
Clock Low to Data Out Valid
Data Out Hold Time After Clock Low
Clock Frequency
3
900
900
tCLQV
tCLQX
fC
tDH
fSCL
tWR
400
5
400
10
tW
Write Time
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
12/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table 8B. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01
V
=2.5 to 5.5 V
=1.8 to 5.5 V
V
=1.8 to 3.6 V
CC
V
CC
CC
T =0 to 70°C or T =0 to 70°C or
Symbol
Alt.
Parameter
T =0 to 70°C or
A
A
Unit
A
4
4
–40 to 85°C
–40 to 85°C
–40 to 85°C
Min
Max
300
300
300
Min
Max
1000
300
Min
Max
300
300
300
tCH1CH2
tCL1CL2
tR
tF
tR
tF
Clock Rise Time
ns
ns
ns
Clock Fall Time
SDA Rise Time
SDA Fall Time
2
20
20
1000
20
tDH1DH2
2
20
600
600
600
0
300
20
4700
4000
4000
0
300
20
600
600
600
0
300
ns
ns
ns
ns
µs
µs
tDL1DL2
1
tSU:STA Clock High to Input Transition
tHIGH
tHD:STA Input Low to Clock Low (START)
tHD:DAT
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
Clock Pulse Width High
Clock Low to Input Transition
tLOW Clock Pulse Width Low
1.3
4.7
1.3
Input Transition to Clock
Transition
tDXCX
tCHDH
tDHDL
tSU:DAT
100
600
1.3
250
4000
4.7
100
600
1.3
ns
ns
µs
ns
ns
tSU:STO Clock High to Input High (STOP)
Input High to Input Low (Bus
Free)
tBUF
3
tAA
tDH
Clock Low to Data Out Valid
200
200
900
200
200
3500
200
200
900
tCLQV
Data Out Hold Time After Clock
Low
tCLQX
fC
fSCL
tWR
Clock Frequency
Write Time
400
10
100
10
400
10
kHz
ms
tW
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
13/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
tCHDX
START
Condition
tW
Write Cycle
STOP
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
14/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table 9. Ordering Information Scheme
Example:
M24C08
–
W
DW
6
T
Memory Capacity
Option
16
08
04
02
01
16 Kbit (2048 x 8)
8 Kbit (1024 x 8)
4 Kbit (512 x 8)
2 Kbit (256 x 8)
1 Kbit (128 x 8)
T
Tape and Reel Packing
Temperature Range
–40 °C to 85 °C
6
3
–40 °C to 125 °C
Operating Voltage
Package
blank 4.5 V to 5.5 V (400 kHz)
BN PDIP8 (0.25 mm frame)
W
R
2.5 V to 5.5 V (400 kHz)
1.8 V to 5.5 V (100 kHz)
MN SO8 (150 mil width)
DW TSSOP8 (169 mil width)
1
S
1.8 V to 3.6 V (400 kHz)
SBGA5 (75 mil width)
EA
Note: 1. SBGA5 package available only for the M24C16, 1.8V to 3.6V (400 kHz), –40°C to 85°C (M24C16-SEA6)
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 9. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
15/21
M24C16, M24C08, M24C04, M24C02, M24C01
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-8
Note: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
10.16
8.26
7.11
–
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
8
0.130
0.115
8
N
16/21
M24C16, M24C08, M24C04, M24C02, M24C01
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
17/21
M24C16, M24C08, M24C04, M24C02, M24C01
TSSOP8 – 8 lead Thin Shrink Small Outline
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
TSSOP8 – 8 lead Thin Shrink Small Outline
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
0.043
0.006
0.037
0.012
0.008
0.122
0.256
0.177
–
A
A1
A2
B
1.10
0.15
0.95
0.30
0.20
3.10
6.50
4.50
–
0.05
0.85
0.19
0.09
2.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.114
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
8
8
CP
0.08
0.003
18/21
M24C16, M24C08, M24C04, M24C02, M24C01
SBGA5 (EA) – Underside view (ball side)
D
D1
E1
E
BALL "1"
e
A
A1
SBGA-00
Note: 1. Drawing is not to scale.
SBGA5 – 5 ball Shell Ball Grid Array
mm
inches
Symb.
Typ.
Min.
0.380
0.150
1.870
1.160
1.720
1.040
0.770
0.320
5
Max.
0.480
0.210
1.930
1.220
1.780
1.100
0.830
0.380
Typ.
0.017
0.007
0.075
0.047
0.069
0.042
0.031
0.014
Min.
0.015
0.006
0.074
0.046
0.068
0.041
0.030
0.013
5
Max.
0.019
0.008
0.076
0.048
0.070
0.043
0.033
0.015
A
0.430
0.180
1.900
1.190
1.750
1.070
0.800
0.350
A1
D
D1
E
E1
e
ball diameter
N
19/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table 10. Revision History
Date
Description of Revision
TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2
10-Dec-1999
18-Apr-2000 Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13
05-May-2000 Extra labelling to Fig-2D
SBGA package information removed to an annex document
23-Nov-2000
-R range changed to being the -S range, and the new -R range added
SBGA package information put back in this document
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
19-Feb-2001 Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
Wording brought in to line with standard glossary
20/21
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
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STMicroelectronics GROUP OF COMPANIES
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www.st.com
21/21
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