M24C32-RBN5PP [STMICROELECTRONICS]
4KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8;
| 型号： | M24C32-RBN5PP |
| 厂家： | 
ST |
| 描述： | 4KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总41页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C32-W M24C32-R M24C32-F
M24C32-X M24C32-DF
32-Kbit serial I²C bus EEPROM
Datasheet - production data
Features
2
• Compatible with all I C bus modes:
– 1 MHz
– 400 kHz
– 100 kHz
TSSOP8 (DW)
169 mil width
• Memory array:
– 32Kbit (4 Kbytes) of EEPROM
– Page size: 32 bytes
– Additional Write lockable page
(M24C32-D order codes)
• Single supply voltage:
– 1.7 V to 5.5 V over –40 °C / +85 °C
SO8 (MN)
150 mil width
– 1.6 V to 5.5 V over –20 °C / +85 °C
• Write:
– Byte Write within 5 ms (10 ms when
V
= 1.6 V)
CC
– Page Write within 5 ms (10 ms when
= 1.6 V)
V
CC
• Random and sequential Read modes
• Write protect of the whole memory array
• Enhanced ESD/Latch-Up protection
• More than 4 million Write cycles
PDIP8 (BN)
• More than 200-year data retention
Packages
UFDFPN8
(MC)
®
• PDIP8 ECOPACK1
®
• SO8 ECOPACK2
®
• TSSOP8 ECOPACK2
®
• UFDFPN8 ECOPACK2
®
• UFDFPN5 ECOPACK2
UFDFPN5
(MH)
May 2014
DocID4578 Rev 22
1/41
This is information on a product in full production.
www.st.com
Contents
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
2.6.2
2.6.3
2.6.4
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 17
Lock Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 17
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
5.2
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Contents
5.2.2
5.2.3
5.2.4
5.2.5
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 20
Read the lock status (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
8
9
10
11
DocID4578 Rev 22
3/41
3
List of tables
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC characteristics (M24C32-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (M24C32-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (M24C32-F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M24C32-X, device grade 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33
SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 34
PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 35
UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
UFDFPN5 (MLP5) – package dimensions (UFDFPN: Ultra thin Fine pitch
Table 24.
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25.
Table 26.
4/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UFDFPN5 package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Maximum R
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C
Figure 13. Maximum R
value versus bus parasitic capacitance C ) for
bus
bus
2
an I C bus at maximum frequency f = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C
Figure 14. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
Figure 17. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 35
Figure 18. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. UFDFPN5 (MLP5) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID4578 Rev 22
5/41
5
Description
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
1
Description
2
The M24C32 is a 32-Kbit I C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 4 K × 8 bits.
The M24C32-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24C32-R can
operate with a supply voltage from 1.8 V to 5.5 V, and the M24C32-F and M24C32-DF can
operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of
-40 °C / +85 °C; while the M24C32-X can operate with a supply voltage from 1.6 V to 5.5 V
over an ambient temperature range of -20 °C / +85 °C.
The M24C32-D offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
6
##
ꢄ
%ꢀꢅ%ꢆ
3$!
-ꢆꢃXXX
3#,
7#
6
!)ꢀꢁꢂꢃꢃF
33
Table 1. Signal names
Function
Signal name
Direction
E2, E1, E0
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Input
I/O
Input
Input
-
SCL
WC
VCC
VSS
-
6/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Description
Figure 2. 8-pin package connections, top view
%ꢀ
%ꢁ
%ꢆ
ꢁ
ꢆ
ꢄ
ꢃ
ꢂ
ꢈ
ꢉ
ꢇ
6
##
7#
3#,
3$!
6
33
!)ꢀꢁꢂꢃꢇF
1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Figure 3. UFDFPN5 package connections
6
6
ꢇ 7#
ꢆ 6
ꢇ
ꢆ
ꢃ
##
33
ꢁ
ꢆ
ꢄ
ꢁ
ꢆ
ꢄ
!"#$
89:7
33
ꢃ
3$!
3#,
4OP VIEW
"OTTOM VIEW
ꢊPADS SIDEꢋ
ꢊMARKING SIDEꢋ
-3ꢄꢆꢁꢁꢈ6ꢁ
1. Inputs E2, E1, E0 are not connected, therefore read as (000). Please refer to Section 2.3 for further
explanations.
DocID4578 Rev 22
7/41
40
Signal description
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2
2.3
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to V (Figure 12
CC
indicates how to calculate the value of the pull-up resistor).
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to V or V , as shown in Figure 4. When not connected (left floating), these inputs
CC
SS
are read as low (0).
For the UFDFPN5 package, the (E2,E1,E0) inputs are not connected, therefore read as
(0,0,0).
Figure 4. Chip enable inputs connection
V
V
CC
CC
M24xxx
M24xxx
E
E
i
i
V
V
SS
SS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Signal description
2.5
VSS (ground)
V
is the reference for the V supply voltage.
CC
SS
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage (V )
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the V line with a suitable capacitor (usually of the order of
CC
10 nF to 100 nF) close to the V /V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (t ).
W
2.6.2
2.6.3
Power-up conditions
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V has reached the
CC
internal reset threshold voltage. This threshold is lower than the minimum V operating
CC
voltage (see Operating conditions in Section 8: DC and AC parameters). When V passes
CC
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until V reaches a valid and stable DC voltage within the
CC
specified [V (min), V (max)] range (see Operating conditions in Section 8: DC and AC
CC
CC
parameters).
In a similar way, during power-down (continuous decrease in V ), the device must not be
CC
accessed when V drops below V (min). When V drops below the internal reset
CC
CC
CC
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in V ), the device must be in the Standby Power
CC
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
DocID4578 Rev 22
9/41
40
Memory organization
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
3
Memory organization
The memory is organized as shown below.
Figure 5. Block diagram
7#
%ꢀ
%ꢁ
%ꢆ
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)ꢍ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
ꢁ PAGE
)DENTIFICATION PAGE
8 DECODER
-3ꢄꢀꢌꢁꢆ6ꢁ
10/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Device operation
4
Device operation
2
The device supports the I C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
2
Figure 6. I C bus protocol
3#,
3$!
3$!
)NPUT
3$!
#HANGE
34!24
#ONDITION
34/0
#ONDITION
ꢁ
ꢆ
ꢄ
ꢈ
ꢂ
ꢌ
3#,
3$!
!#+
-3"
34!24
#ONDITION
ꢁ
ꢆ
ꢄ
ꢈ
ꢂ
ꢌ
3#,
3$!
-3"
!#+
34/0
#ONDITION
!)ꢀꢀꢈꢌꢆ"
DocID4578 Rev 22
11/41
40
Device operation
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
4.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
12/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Device operation
4.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier(1)
Chip Enable address(2)
RW
b0
b7
b6
b5
b4
b3
b2
b1
Device select code
when addressing the
memory array
1
0
1
0
E2
E1
E0
RW
RW
Device select code
when accessing the
Identification page
1
0
1
1
E2
E1
E0
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared with the value read on input pins E0, E1,and E2.
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
DocID4578 Rev 22
13/41
40
Instructions
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3. Most significant address byte
A15
A7
A14
A6
A13
A12
A11
A10
A9
A1
A8
A0
Table 4. Least significant address byte
A5 A4 A3 A2
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t is triggered. A Stop condition at any other time slot does not trigger the internal
W
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t ), the
W
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
14/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Instructions
5.1.1
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 7.
Figure 7. Write mode sequences with WC = 0 (data write enabled)
7#
!#+
!#+
!#+
!#+
"YTE 7RITE
$EV SEL
"YTE ADDR
"YTE ADDR
$ATA IN
2ꢍ7
7#
!#+
!#+
!#+
!#+
0AGE 7RITE
$EV SEL
"YTE ADDR
"YTE ADDR
$ATA IN ꢁ
$ATA IN ꢆ
2ꢍ7
7# ꢊCONTgDꢋ
!#+
!#+
0AGE 7RITE ꢊCONTgDꢋ
$ATA IN .
!)ꢀꢁꢁꢀꢉD
DocID4578 Rev 22
15/41
40
Instructions
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
5.1.2
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b16-b5, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 8. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
7#
!#+
!#+
!#+
./ !#+
"YTE 7RITE
$EV SEL
"YTE ADDR
"YTE ADDR
$ATA IN
2ꢍ7
7#
!#+
!#+
!#+
./ !#+
$ATA IN ꢆ
0AGE 7RITE
$EV SEL
"YTE ADDR
"YTE ADDR
$ATA IN ꢁ
2ꢍ7
7# ꢊCONTgDꢋ
./ !#+
./ !#+
0AGE 7RITE ꢊCONTgDꢋ
$ATA IN .
!)ꢀꢁꢁꢆꢀD
16/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Instructions
5.1.3
Write Identification Page (M24C32-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
•
•
Device type identifier = 1011b
MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A4/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4
5.1.5
Lock Identification Page (M24C32-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
•
•
•
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
ECC (Error Correction Code) and Write cycling
(1)
The Error Correction Code (ECC) is an internal logic function which is transparent for the
2
I C communication protocol.
(2)
The ECC logic is implemented on each group of four EEPROM bytes . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
(2)
other bytes located in the same group . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined Table 12: Cycling performance.
1. The ECC is implemented only in the devices identified with process letter K
2. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
DocID4578 Rev 22
17/41
40
Instructions
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
5.1.6
Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9, is:
•
Initial condition: a Write cycle is in progress.
•
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
tƌŝƚĞꢀĐLJĐůĞ
ŝŶꢀƉƌŽŐƌĞƐƐꢀꢀ
^ƚĂƌƚꢀĐŽŶĚŝƚŝŽŶ
ꢁĞǀŝĐĞꢀƐĞůĞĐƚ
ǁŝƚŚꢀZtꢀсꢀϬ
ꢂꢃ<
EK
ƌĞƚƵƌŶĞĚ
)LUVWꢅE\WHꢅRIꢅLQVWUXFWLRQ
ZLWKꢅ5:ꢅ ꢅꢀꢅDOUHDG\
GHFRGHGꢅE\ꢅWKHꢅGHYLFH
zꢄ^
EĞdžƚ
KƉĞƌĂƚŝŽŶꢀŝƐ
ĂĚĚƌĞƐƐŝŶŐꢀƚŚĞ
ŵĞŵŽƌLJ
EK
zꢄ^
^ĞŶĚꢀꢂĚĚƌĞƐƐ
ĂŶĚꢀZĞĐĞŝǀĞꢀꢂꢃ<
ZĞ^ƚĂƌƚ
EK
zꢄ^
^ƚŽƉ
6WDUW&RQGLWLRQ
ꢁĂƚĂꢀĨŽƌꢀƚŚĞ
tƌŝƚĞꢀĐƉĞƌĂƚŝŽŶ
'HYLFHꢅVHOHFW
ZLWKꢅ5:ꢅ ꢅꢁ
ꢃŽŶƚŝŶƵĞꢀƚŚĞ
ZĂŶĚŽŵꢀZĞĂĚꢀŽƉĞƌĂƚŝŽŶ
ꢃŽŶƚŝŶƵĞꢀƚŚĞ
tƌŝƚĞꢀŽƉĞƌĂƚŝŽŶ
$,ꢀꢁꢂꢃꢄH
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
18/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Instructions
5.2
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 10. Read mode sequences
ACK
NO ACK
Current
Address
Read
Dev sel
Data out
R/W
ACK
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequential
Current
Read
Dev sel
Data out 1
R/W
ACK
R/W
ACK
ACK
ACK
R/W
ACK
Sequention
Random
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out1
ACK
NO ACK
Data out N
AI01105d
DocID4578 Rev 22
19/41
40
Instructions
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
5.2.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the byte location in the Identification page, therefore the next Current
Address Read in the memory uses this new address counter value. When accessing the
memory, it is safer to always use the Random Address Read instruction (this instruction
loads the address counter with the byte location to read in the memory, see Section 5.2.1)
instead of the Current Address Read instruction.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.2.4
Read Identification Page (M24C32-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 10d, the number of bytes should be less than
or equal to 22, as the ID page boundary is 32 bytes).
20/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Initial delivery state
5.2.5
Read the lock status (M24C32-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
•
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
•
Stop: the device is then set back into Standby mode by the Stop condition.
6
Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
DocID4578 Rev 22
21/41
40
Maximum rating
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
7
Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
°C
mA
V
TSTG
Lead temperature during soldering
PDIP-specific lead temperature during soldering
DC output current (SDA = 0)
Input or output range
see note(1)
TLEAD
-
260(2)
IOL
VIO
-
5
–0.50
–0.50
-
6.5
VCC
VESD
Supply voltage
6.5
V
Electrostatic pulse (Human Body model)(3)
2000(4)
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
2. TLEAD max must not be applied for more than 10 s.
3. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω).
4. 4000V for devices identified with process letter K and P.
22/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Operating conditions (voltage range W)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
–40
-
5.5
85
1
V
Ambient operating temperature
Operating clock frequency
°C
fC
MHz
Table 7. Operating conditions (voltage range R)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.8
–40
-
5.5
85
1
V
Ambient operating temperature
Operating clock frequency
°C
fC
MHz
Table 8. Operating conditions (voltage range F)
Parameter Min.
Symbol
Max.
Unit
VCC
Supply voltage
1.6
-40
0
1.7
-40
5.5
85
85
-
V
Ambient operating temperature:READ
Ambient operating temperature: WRITE
Operating clock frequency
TA
fC
°C
-40
400
1000
kHz
Table 9. Operating conditions (voltage range X)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.6
–20
-
5.5
85
1
V
Ambient operating temperature
Operating clock frequency
°C
fC
MHz
Table 10. AC measurement conditions
Symbol
Parameter
Min.
Max.
Unit
Cbus
Load capacitance
100
pF
ns
V
SCL input rise/fall time, SDA input fall time
Input levels
-
50
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference levels
V
DocID4578 Rev 22
23/41
40
DC and AC parameters
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Figure 11. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
)NPUT AND OUTPUT
4IMING REFERENCE LEVELS
ꢀꢎꢂ6
##
ꢀꢎꢈ6
##
ꢀꢎꢄ6
##
ꢀꢎꢆ6
##
-3ꢁꢌꢈꢈꢃ6ꢁ
Table 11. Input parameters
Symbol
Parameter(1)
Test condition
Min. Max. Unit
CIN
CIN
ZL
Input capacitance (SDA)
-
-
-
8
6
-
pF
pF
kΩ
kΩ
Input capacitance (other pins)
-
VIN < 0.3 VCC
VIN > 0.7 VCC
30
500
Input impedance (E2, E1, E0, WC)(2)
ZH
-
1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
Table 12. Cycling performance
Symbol
Parameter
Test condition(1)
Max.
Unit
Write cycle(3)
TA ≤ 25 °C, VCC(min) < VCC < VCC(max)
4,000,000
1,200,000
Write cycle
Ncycle
endurance(2)
TA = 85 °C, VCC(min) < VCC < VCC(max)
1. Cycling performance for products identified by process letter K or T.
2. The Write cycle endurance is defined by characterization and qualification. For devices embedding the
ECC functionality (see Chapter 5.1.5), the write cycle endurance is defined for group of four bytes located
at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
3. A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Lock
Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write
Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling
Table 13. Memory cell data retention
Parameter
Data retention(1)
Test condition
TA = 55 °C
Min.
Unit
200
Year
1. For products identified by process letter K or T. The data retention behavior is checked in production, while
the 200-year limit is defined from characterization and qualification results.
24/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
DC and AC parameters
Table 14. DC characteristics (M24C32-W, device grade 6)
Test conditions (in addition to those
Symbol
Parameter
Min.
Max.
Unit
in Table 6)
Input leakage current
(SCL, SDA, E2, E1,
E0)
VIN = VSS or VCC, device in Standby
mode
ILI
-
± 2
µA
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
ILO
-
-
-
-
± 2
2
µA
mA
mA
mA
2.5 V < VCC < 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
ICC
ICC0
ICC1
Supply current (Read)
Supply current (Write)
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
2.5
5(2)
During tW,
2.5 V ≤ VCC ≤ 5.5 V
Device not selected(3)
VIN = VSS or VCC, VCC = 2.5 V
,
-
-
2
µA
µA
Standby supply
current
Device not selected(3)
VIN = VSS or VCC, VCC = 5.5 V
,
3(4)
Input low voltage
VIL
-
–0.45
0.3 VCC
6.5
V
(SCL, SDA, WC, E2,
E1, E0)(5)
Input high voltage
(SCL, SDA)
-
-
0.7 VCC
V
V
V
VIH
Input high voltage
(WC, E2, E1, E0)(6)
0.7 VCC VCC+1
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
VOL
Output low voltage
-
0.4
1. Only for devices identified with process letter K or T.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
4. 5 µA for previous devices identified by process letter P.
5. Ei inputs should be tied to Vss (see Section 2.3).
6. Ei inputs should be tied to Vcc (see Section 2.3).
DocID4578 Rev 22
25/41
40
DC and AC parameters
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Table 15. DC characteristics (M24C32-R, device grade 6)
Test conditions(1) (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 7)
Input leakage current
(E0, E1, E2, SCL, SDA)
VIN = VSS or VCC, device in
Standby mode
ILI
-
-
-
-
-
-
± 2
± 2
0.8
2.5
3(4)
1
µA
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
Supply current (Read)
Supply current (Write)(3)
VCC = 1.8 V, fc= 400 kHz
fc= 1 MHz(2)
mA
mA
mA
µA
ICC
During tW,
1.8 V ≤VCC ≤2.5 V
ICC0
ICC1
Device not selected(5)
VIN = VSS or VCC, VCC = 1.8 V
,
Standby supply current
Input low voltage
VIL
(SCL, SDA, WC, E2, E1, 1.8 V ≤ VCC < 2.5 V
–0.45 0.25 VCC
V
V
E0)(6)
Input high voltage
1.8 V ≤ VCC < 2.5 V
(SCL, SDA)
0.75 VCC
0.75 VCC VCC+1
0.2
6.5
VIH
Input high voltage
1.8 V ≤ VCC < 2.5 V
(WC, E2, E1, E0)(7)
V
V
VOL
Output low voltage
IOL = 1 mA, VCC = 1.8 V
-
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 14 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see note (1) in Table 19).
3. For devices identified with process letter K or T
4. Characterized value, not tested in production.
5. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
6. Ei inputs should be tied to Vss (see Section 2.3).
7. Ei inputs should be tied to Vcc (see Section 2.3).
26/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
DC and AC parameters
Table 16. DC characteristics (M24C32-F, device grade 6)
Test conditions(1) (in addition
Symbol
Parameter
Min.
Max.
Unit
µA
to those in Table 8)
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
-
-
-
± 2
± 2
0.8
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
µA
VCC = 1.6 V or 1.7 V, fc= 400 kHz
mA
ICC
Supply current (Read)
fc= 1 MHz(2)
-
-
2.5
mA
mA
ICC0
ICC1
Supply current (Write)
Standby supply current
During tW VCC < 2.5 V
3(3)
Device not selected(4)
VIN = VSS or VCC
,
,
-
1
µA
VCC = 1.6 V or 1.7 V
Input low voltage
VIL
VCC < 2.5 V
–0.45
0.25 VCC
6.5
V
V
(SCL, SDA, WC, Ei)(5)
Input high voltage
(SCL, SDA)
V
CC < 2.5 V
VCC < 2.5 V
IOL = 1 mA, VCC = 1.6 V or 1.7 V
0.75 VCC
VIH
Input high voltage
(WC, E2, E1, E0)(6)
0.75 VCC VCC+1
0.2
V
V
VOL
Output low voltage
-
1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 14 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see note(1) in Table 19).
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
5. Ei inputs should be tied to VSS (see Section 2.3).
6. Ei inputs should be tied to VCC (see Section 2.3).
DocID4578 Rev 22
27/41
40
DC and AC parameters
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Table 17. DC characteristics (M24C32-X, device grade 5)
Test conditions(1) (in addition
Symbol
Parameter
Min.
Max.
Unit
µA
to those in Table 9)
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
± 2
± 2
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
Supply current (Read)
µA
VCC = 1.6 V, fc= 400 kHz
0.8
2.5
3(3)
ICC
mA
fc= 1 MHz(2)
ICC0
ICC1
Supply current (Write)
Standby supply current
During tW, 1.6 V < VCC < 2.5 V
mA
µA
Device not selected(4)
,
1
VIN = VSS or VCC, VCC = 1.6 V
Input low voltage
VIL
1.6 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
6.5
V
V
(SCL, SDA, WC, Ei)(5)
Input high voltage
(SCL, SDA)
1.6 V ≤ VCC < 2.5 V
0.75 VCC
VIH
Input high voltage
(WC, E2, E1, E0)(6)
1.6 V ≤ VCC < 2.5 V
0.75 VCC VCC+0.6
0.2
V
V
VOL
Output low voltage
IOL = 1 mA, VCC = 1.6 V
1. If the application uses the device with 2.5 V < VCC < 5.5 V and -20 °C < TA < +85 °C, please refer to
Table 14 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see note(1) in Table 19)
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
5. Ei inputs should be tied to VSS (see Section 2.3).
6. Ei inputs should be tied to VCC (see Section 2.3).
28/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
DC and AC parameters
Table 18. 400 kHz AC characteristics
Parameter
Symbol
Alt.
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tF
Clock frequency
-
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
SDA (out) fall time
600
-
-
1300
20(2)
300
(1)
tQL1QL2
tXH1XH2
tXL1XL2
tDXCH
(3)
(3)
tR
Input signal rise time
Input signal fall time
(3)
(3)
tF
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
(4)
tCLQX
tDH
tAA
Data out hold time
100(5)
-
(6)
tCLQV
Clock low to next data valid (access time)
-
900
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
600
600
600
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tBUF
1300
-
ns
(7)(1)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(8)(1)
tDHWH
tW
tWR
Internal Write cycle duration
5(9)
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
80(10)
ns
(1)
tNS
-
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C < 400 kHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. The previous product identified by process letter P was specified with tCLQX = 200 ns (min). Both values
offer a safe margin compared to the I2C specification recommendations.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. 10 ms for the M24C32-X, when VCC< 1.7 V.
10. The previous M24C32 device (identified by process letter P) offers tNS = 100 ns (max), while the current
M24C32 device offers tNS = 80 ns (max). Both products offer a safe margin compared to the 50 ns
minimum value recommended by the I2C specification.
DocID4578 Rev 22
29/41
40
DC and AC parameters
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Table 19. 1 MHz AC characteristics
Symbol
Alt.
Parameter(1)
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tHIGH Clock pulse width high
260
tCLCH
tLOW
tR
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
500
-
(2)
(2)
tXH1XH2
tXL1XL2
(2)
(2)
tF
20(4)
50
120
(3)
tQL1QL2
tF
tDXCH
tCLDX
tSU:DAT Data in setup time
tHD:DAT Data in hold time
-
0
-
(5)
tCLQX
tDH
tAA
Data out hold time
100
-
-
(6)
tCLQV
Clock low to next data valid (access time)
450
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tBUF
500
-
ns
(7)(3)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(8)(3)
tDHWH
tW
tWR
Write time
5(9)
ms
Pulse width ignored (input filter on SCL and
SDA)
(3)
tNS
-
80
ns
1. Only for devices identified by the process letter K or T (devices qualified at 1 MHz).
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
3. Characterized only, not tested in production.
4. With CL = 10 pF.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. 10 ms for the M24C32-X, when VCC< 1.7 V.
30/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
DC and AC parameters
Figure 12. Maximum R
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz
C
ꢁꢀꢀ
4HE 2
X # TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢃꢀꢀ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢎ
6
##
ꢁꢀ
2
BUS
(ERE 2
BUS
§ # ꢏ ꢁꢆꢀ NS
BUS
ꢃ K½
3#,
3$!
)£# BUS
MASTER
-ꢆꢃXXX
ꢁ
ꢄꢀ P&
#
BUS
ꢁꢀ
ꢁꢀꢀ
"US LINE CAPACITOR ꢊP&ꢋ
ꢁꢀꢀꢀ
AIꢁꢃꢈꢌꢉB
Figure 13. Maximum R
value versus bus parasitic capacitance C ) for
bus
bus
2
an I C bus at maximum frequency f = 1MHz
C
6
ꢁꢀꢀ
##
2
BUS
4HE 2
§ #
TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢁꢇꢀ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢎ
3#,
3$!
)£# BUS
MASTER
ꢁꢀ
ꢃ
-ꢆꢃXXX
(EREꢐ
#
§
BUS
ꢏ ꢁꢆꢀ NS
#
2
BUS
BUS
ꢁ
ꢁꢀ
ꢄꢀ
"US LINE CAPACITOR ꢊP&ꢋ
ꢁꢀꢀ
-3ꢁꢌꢈꢃꢇ6ꢁ
DocID4578 Rev 22
31/41
40
DC and AC parameters
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Figure 14. AC waveforms
^ƚĂƌƚ
ĐŽŶĚŝƚŝŽŶ
^ƚĂƌƚ
ĐŽŶĚŝƚŝŽŶ
^ƚŽƉ
ĐŽŶĚŝƚŝŽŶ
ƚy>ϭy>Ϯ
ƚꢃ,ꢃ>
ƚy,ϭy,Ϯ
^ꢃ>
ƚꢃ>ꢃ,
ƚꢁ>ꢃ>
ƚy>ϭy>Ϯ
^ꢁꢂꢀ/Ŷ
tꢃ
^ꢁꢂ
/ŶƉƵƚ
ƚꢃ,ꢁ>
ƚꢃ>ꢁy
ƚꢁyꢃ,
^ꢁꢂ
ꢃŚĂŶŐĞ
ƚy,ϭy,Ϯ
ƚꢃ,ꢁ,
ƚꢁ,ꢁ>
ƚꢁ,t,
ƚt>ꢁ>
^ƚŽƉ
ĐŽŶĚŝƚŝŽŶ
^ƚĂƌƚ
ĐŽŶĚŝƚŝŽŶ
^ꢃ>
^ꢁꢂꢀ/Ŷ
ƚt
tƌŝƚĞꢀĐLJĐůĞ
ƚꢃ,ꢁ,
ƚꢃ,ꢁ>
ƚꢃ,ꢃ>
^ꢃ>
ƚꢃ>Ys
ƚꢃ>Yy
ꢁĂƚĂꢀǀĂůŝĚ
ƚY>ϭY>Ϯ
ꢁĂƚĂꢀǀĂůŝĚ
^ꢁꢂꢀKƵƚ
ꢂ/ϬϬϳϵϱŝ
32/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
–
–
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
–
–
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A1
A2
b
–
0.050
0.800
0.190
0.090
–
0.0020
0.0315
0.0075
0.0035
–
1.000
–
0.0394
–
c
–
–
CP
D
–
–
3.000
0.650
6.400
4.400
0.600
1.000
–
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
–
0.1142
–
e
E
6.200
4.300
0.450
–
6.600
4.500
0.750
–
0.2441
0.1693
0.0177
–
0.2598
0.1772
0.0295
–
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID4578 Rev 22
33/41
40
Package mechanical data
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
Kꢅ[ꢅꢃꢇ
$ꢈ
$
F
FFF
E
H
ꢀꢉꢈꢇꢅPP
*$8*(ꢅ3/$1(
'
N
ꢂ
(ꢁ
(
/
ꢁ
$ꢁ
/ꢁ
62ꢆ$
1. Drawing is not to scale.
Table 21. SO8N – 8-lead plastic small outline, 150 mils body width, package data
millimeters
Min
inches (1)
Symbol
Typ
Max
Typ
Min
Max
A
–
–
1.750
0.250
–
–
–
0.0689
0.0098
–
A1
A2
b
–
0.100
1.250
0.280
0.170
–
–
0.0039
0.0492
0.0110
0.0067
–
–
–
–
0.480
0.230
0.100
5.000
6.200
4.000
–
–
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
–
c
–
–
–
ccc
D
–
4.900
6.000
3.900
1.270
–
4.800
5.800
3.800
–
0.1929
0.2362
0.1535
0.0500
–
0.1890
0.2283
0.1496
–
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
–
–
L
–
0.400
–
1.270
–
–
0.0157
–
0.0500
–
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
34/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Package mechanical data
Figure 17. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
%
Bꢆ
!ꢆ
!ꢁ
!
,
C
B
E
E!
E"
$
ꢂ
ꢁ
%ꢁ
0$)0ꢅ"
1. Drawing is not to scale.
Table 22. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
–
–
5.33
–
–
–
0.2098
–
–
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
–
0.0150
0.1150
0.0142
0.0449
0.0079
0.3551
0.3000
0.2402
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
–
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.1299
0.0181
0.0598
0.0098
0.3650
0.3098
0.2500
0.1000
0.3000
–
0.1949
0.0220
0.0701
0.0142
0.4000
0.3252
0.2799
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
–
10.92
3.81
–
0.4299
0.1500
3.30
2.92
0.1299
0.1150
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID4578 Rev 22
35/41
40
Package mechanical data
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Figure 18. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead)
E
B
$
,ꢁ
,ꢄ
0IN ꢁ
%ꢆ
+
%
,
!
$ꢆ
EEE
!ꢁ
1. Drawing is not to scale.
:7?-%E6ꢆ
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 23. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead)
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.450
0.000
0.200
1.900
1.200
2.900
1.200
–
0.600
0.050
0.300
2.100
1.600
3.100
1.600
–
0.0217
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
–
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
–
A1
0.020
0.0008
b
0.250
0.0098
D
2.000
0.0787
D2 (rev MC)
–
–
E
3.000
0.1181
E2 (rev MC)
–
–
e
0.500
0.0197
K (rev MC)
–
–
–
–
–
0.300
0.300
–
–
–
–
–
–
–
0.0118
0.0118
–
–
L
L1
0.500
0.150
–
0.0197
0.0059
–
L3
0.300
0.080
0.0118
0.0031
eee(2)
–
–
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
36/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Package mechanical data
Figure 19. UFDFPN5 (MLP5) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead)
'
N
/
3LQꢅꢁ
3LQꢅꢁ
E
(
(ꢁ
H
$
$ꢁ
'ꢁ
7RSꢅYLHZꢅ
ꢊPDUNLQJꢅVLGHꢋ
%RWWRPꢅYLHZꢅ
ꢊSDGVꢅVLGHꢋ
6LGHꢅYLHZ
$ꢀ8.B0(B9ꢁ
1. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from
the orientation of the marking: when reading the marking, pin 1 is below the upper left package corner.
Table 24. UFDFPN5 (MLP5) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead)
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
b
0.550
–
0.500
0
0.600
0.050
0.260
1.800
1.600
1.500
0.260
–
0.0217
–
0.0197
0
0.0236
0.0020
0.0102
0.0709
0.0630
0.0591
0.0102
–
0.220
1.700
1.500
1.400
0.220
0.400
0.550
0.400
0.180
1.600
1.400
1.300
0.180
–
0.0087
0.0669
0.0591
0.0551
0.0087
0.0157
0.0217
0.0157
0.0071
0.0630
0.0551
0.0512
0.0071
–
D
D1
E
E1
e
L
0.500
–
0.600
–
0.0197
–
0.0236
–
k
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID4578 Rev 22
37/41
40
Part numbering
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
10
Part numbering
Table 25. Ordering information scheme
M24C32-D
Example:
W
MN 6
T
P /P
Device type
M24 = I2C serial access EEPROM
Device function
C32 = 32 Kbit (4096 x 8)
Device family
Blank = Without Identification page
D = With additional Identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
X = VCC = 1.6 V to 5.5 V
Package
BN = PDIP8 (1)
MN = SO8 (150 mil width) (2)
DW = TSSOP8 (169 mil width)(2)
MC = UFDFPN8 (MLP8) (2)
MH = UFDFPN5 (MLP5)(2)
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
5 = Consumer: device tested with standard test flow over –20 to 85°C
Option
T = Tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(3)
/P or /K or /T = Manufacturing technology code
1. RoHS-compliant (ECOPACK1®)
2. RoHS-compliant and halogen-free (ECOPACK2®)
3. The process letters appear on the device package (marking) and/or on the shipment box. Please contact
your nearest ST Sales Office for further information.
38/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Revision history
11
Revision history
Table 26. Document revision history
Changes
Date
Revision
Added:
– M24C32-DF and all information concerning the Identification Page:
sections 4.9, 4.10, 4.17, 4.18
– ECC section 4.11
– AC table with clock frequency of 1 MHz (Table 18)
– Table 4: Device select code
Updated:
– Section 1: Description
18-Mar-2011
18
– Section 4.5: Memory addressing
– Section 4.18: Read the lock status (M24C32-D)
– Table 6: Absolute maximum ratings
– AC/DC tables 13, 17 with values specific to the device identified with
process letter K
Deleted:
– Table 2: Device select code
– Table 23: Available M24C32 products (package, voltage range,
temperature grade)
Updated:
– Figure 4: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
– Figure 5: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value
versus bus parasitic capacitance (Cbus)
14-Sep-2011
19
Added tWLDL and tDHWH in:
– Table 17: 400 kHz AC characteristics
– Table 18: 1 MHz AC characteristics
– Figure 13: AC waveforms
Minor text changes.
Datasheet split into:
– M24C32-DF, M24C32-W, M24C32-R,M24C32-F (this datasheet) for
standard products (range 6),
21-May-2012
20
– M24C32-125 datasheet for automotive products (range 3).
DocID4578 Rev 22
39/41
40
Revision history
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Table 26. Document revision history (continued)
Date
Revision
Changes
Added reference M24C32-X.
Updated:
25-Jul-2012
21
– AC and DC tables in Section 8: DC and AC parameters.
– Section Figure 56.: M24C16-FCS5TP/S WLCSP 5 bumps package
outline.
Add new package UFDFPN5, description onFigure 19 and Table 24.
Updated:
– Figure 5: Block diagram
– VESD value on Table 5
– Icc1 values on Table 14
19-May-2014
22
– Icc and Icc0 test conditions on Table 16
– VIH(max) values on Table 14, Table 15
– Icc, Icc0 ,Icc1, VIL, VOL and VIH test conditions onTable 16
– Note on Table 12, Table 13, Table 14, Table 16, Table 17 and Table 19
– Table 25
– Section numbering for Section 5.2.4 and Section 5.2.5.
40/41
DocID4578 Rev 22
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2014 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
DocID4578 Rev 22
41/41
41
相关型号：
©2020 ICPDF网 联系我们和版权申明