M24C32-RMB5PP

更新时间:2024-10-29 13:07:26
描述:4KX8 I2C/2-WIRE SERIAL EEPROM, DSO8, 2 X 3 MM, ROHS COMPLIANT, MLP-8

M24C32-RMB5PP 概述

4KX8 I2C/2-WIRE SERIAL EEPROM, DSO8, 2 X 3 MM, ROHS COMPLIANT, MLP-8 EEPROM

M24C32-RMB5PP 规格参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:VSON,针数:8
Reach Compliance Code:compliant风险等级:5.02
最大时钟频率 (fCLK):0.4 MHzJESD-30 代码:R-XDSO-N8
长度:3 mm内存密度:32768 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-20 °C组织:4KX8
封装主体材料:UNSPECIFIED封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:0.6 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:OTHER
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:2 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

M24C32-RMB5PP 数据手册

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M24128  
M24C64 M24C32  
128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM  
Feature summary  
2
Two-Wire I C serial interface  
Supports 400kHz Protocol  
Single supply voltages (see Table 1 for root  
part numbers):  
– 2.5 to 5.5V  
– 1.8 to 5.5V  
– 1.7 to 5.5V  
PDIP8 (BN)  
Write Control Input  
Byte and Page Write  
Random And Sequential Read modes  
Self-Timed programming cycle  
Automatic address incrementing  
Enhanced ESD/Latch-Up Protection  
More than 1 Million Write cycles  
More than 40-year data retention  
SO8 (MN)  
150 mil width  
Packages  
– ECOPACK® (RoHS compliant)  
TSSOP8 (DW)  
169 mil width  
Table 1.  
Product list  
Reference  
Root part number Supply voltage  
M24128-BW  
M24128-BR  
M24C64-W  
M24C64-R  
M24C64-F  
M24C32-W  
M24C32-R  
M24C32-F  
2.5 to 5.5V  
1.8 to 5.5V  
2.5 to 5.5V  
1.8 to 5.5V  
1.7 to 5.5V  
2.5 to 5.5V  
1.8 to 5.5V  
1.7 to 5.5V  
M24128  
M24C64  
UFDFPN8 (MB)  
2x3mm² (MLP)  
M24C32  
October 2006  
Rev 9  
1/34  
www.st.com  
1
Contents  
M24128, M24C64, M24C32  
Contents  
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.0.1  
2.0.2  
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1  
2.2  
2.3  
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
2.3.1  
2.3.2  
2.3.3  
Operating supply voltage V  
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9  
Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
4.9  
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17  
4.10 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.12 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.13 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.14 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
5
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
2/34  
M24128, M24C64, M24C32  
Contents  
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
8
9
10  
3/34  
List of tables  
M24128, M24C64, M24C32  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Address most significant byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Operating conditions (M24128-BW, M24C64-W, M24C32-W) . . . . . . . . . . . . . . . . . . . . . . 21  
Operating conditions (M24128-BR, M24C64-R, M24C32-R) . . . . . . . . . . . . . . . . . . . . . . . 21  
Operating conditions (M24C64-F, M24C32-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
DC characteristics (V = 2.5V to 5.5V, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
CC  
DC characteristics (V = 2.5V to 5.5V, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
CC  
DC characteristics (V = 1.8V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
CC  
DC characteristics (V = 1.7V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
CC  
AC characteristics (V = 2.5V to 5.5V, device grades 6 and 3) . . . . . . . . . . . . . . . . . . . . 25  
CC  
AC characteristics (V = 1.8V to 5.5V or V = 1.7V to 5.5V) . . . . . . . . . . . . . . . . . . . . . 25  
CC  
CC  
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data . . . . . . . . . . . . 27  
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,  
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 29  
UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead  
Table 21.  
Table 22.  
2 × 3mm, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Table 23.  
Table 24.  
4/34  
M24128, M24C64, M24C32  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 9  
2
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Figure 10. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 11. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package outline. . . . . . . . . . . . . . . . . . . . 27  
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . 28  
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 16. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead  
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
5/34  
Summary description  
M24128, M24C64, M24C32  
1
Summary description  
2
The M24C32, M24C64 and M24128 devices are I C-compatible electrically erasable  
programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits  
and 16384 × 8 bits, respectively.  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages.  
ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark.  
ECOPACK specifications are available at: www.st.com.  
Figure 1.  
Logic diagram  
V
CC  
3
M24128-BW  
M24128-BR  
M24C64-W  
M24C64-R  
M24C64-F  
M24C32-W  
M24C32-R  
M24C32-F  
E0-E2  
SDA  
SCL  
WC  
V
SS  
AI01844d  
2
I C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.  
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the  
2
I C bus definition.  
2
The device behaves as a slave in the I C protocol, with all memory operations synchronized  
by the serial clock. Read and Write operations are initiated by a Start condition, generated  
by the bus master. The Start condition is followed by a Device Select Code and Read/Write  
bit (RW) (as described in Table 3), terminated by an acknowledge bit.  
th  
When writing data to the memory, the device inserts an acknowledge bit during the 9 bit  
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the  
bus master acknowledges the receipt of the data byte in the same way. Data transfers are  
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.  
6/34  
M24128, M24C64, M24C32  
Summary description  
Table 2.  
Signal names  
E0, E1, E2  
Chip Enable  
Serial Data  
Serial Clock  
Write Control  
Supply Voltage  
Ground  
SDA  
SCL  
WC  
VCC  
VSS  
Figure 2.  
DIP, SO, TSSOP and UFDFPN connections  
M24128  
M24C64  
M24C32  
E0  
E1  
E2  
1
2
3
4
8
7
6
5
V
CC  
WC  
SCL  
SDA  
V
SS  
AI01845e  
1. See Package mechanical section for package dimensions, and how to identify pin-1.  
7/34  
Signal description  
M24128, M24C64, M24C32  
2
Signal description  
2.0.1  
Serial Clock (SCL)  
This input signal is used to strobe all data in and out of the device. In applications where this  
signal is used by slave devices to synchronize the bus to a slower clock, the bus master  
must have an open drain output, and a pull-up resistor must be connected from Serial Clock  
(SCL) to V . (Figure 4 indicates how the value of the pull-up resistor can be calculated). In  
CC  
most applications, though, this method of synchronization is not employed, and so the pull-  
up resistor is not necessary, provided that the bus master has a push-pull (rather than open  
drain) output.  
2.0.2  
Serial Data (SDA)  
This bi-directional signal is used to transfer data in or out of the device. It is an open drain  
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A  
pull up resistor must be connected from Serial Data (SDA) to V . (Figure 4 indicates how  
CC  
the value of the pull-up resistor can be calculated).  
2.1  
Chip Enable (E0, E1, E2)  
These input signals are used to set the value that is to be looked for on the three least  
significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to  
V
or V , to establish the Device Select Code as shown in Figure 3. When not connected  
CC  
SS  
(left floating), these inputs are read as Low (0,0,0).  
Figure 3. Device select code  
V
V
CC  
CC  
M24xxx  
M24xxx  
E
E
i
i
V
V
SS  
SS  
Ai12806  
2.2  
Write Control (WC)  
This input signal is useful for protecting the entire contents of the memory from inadvertent  
write operations. Write operations are disabled to the entire memory array when Write  
Control (WC) is driven High. When unconnected, the signal is internally read as V , and  
IL  
Write operations are allowed.  
When Write Control (WC) is driven High, Device Select and Address bytes are  
acknowledged, Data bytes are not acknowledged.  
8/34  
M24128, M24C64, M24C32  
Signal description  
2.3  
Supply voltage (VCC)  
2.3.1  
Operating supply voltage V  
CC  
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage  
CC  
within the specified [V (min), V (max)] range must be applied (see Table 9 and Table 10).  
CC  
CC  
In order to secure a stable DC supply voltage, it is recommended to decouple the V line  
CC  
with a suitable capacitor (usually of the order of 10nF to 100nF) close to the V /V  
CC SS  
package pins.  
This voltage must remain stable and valid until the end of the transmission of the instruction  
and, for a Write instruction, until the completion of the internal write cycle (t ).  
W
2.3.2  
2.3.3  
Internal device reset  
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)  
circuit is included. At Power-up (continuous rise of V ), the device does not respond to any  
CC  
instruction until V has reached the Power On Reset threshold voltage (this threshold is  
CC  
lower than the minimum V operating voltage defined in Table 9 and Table 10).  
CC  
When V has passed the POR threshold, the device is reset and is in Standby Power  
CC  
mode.  
Power-down  
At Power-down (continuous decrease of V ), as soon as V drops from the normal  
CC  
CC  
operating voltage to below the Power On Reset threshold voltage, the device stops  
responding to any instruction sent to it.  
During Power-down, the device must be deselected and in the Standby Power mode (that is  
there should be no internal Write cycle in progress).  
2
Figure 4.  
Maximum R value versus bus parasitic capacitance (C) for an I C bus  
P
V
CC  
20  
16  
12  
8
R
R
P
P
SDA  
SCL  
MASTER  
C
fc = 100kHz  
4
fc = 400kHz  
C
0
10  
100  
C (pF)  
1000  
AI01665b  
9/34  
Signal description  
M24128, M24C64, M24C32  
2
Figure 5.  
I C bus protocol  
SCL  
SDA  
SDA  
Input  
SDA  
Change  
START  
Condition  
STOP  
Condition  
1
2
3
7
8
9
SCL  
SDA  
ACK  
MSB  
START  
Condition  
1
2
3
7
8
9
SCL  
SDA  
MSB  
ACK  
STOP  
Condition  
AI00792B  
Table 3.  
Device select code  
Device Type Identifier(1)  
Chip Enable Address(2)  
RW  
b7  
1
b6  
0
b5  
1
b4  
0
b3  
E2  
b2  
E1  
b1  
E0  
b0  
Device Select Code  
RW  
1. The most significant bit, b7, is sent first.  
2. E0, E1 and E2 are compared against the respective external pins on the memory device.  
Table 4.  
Address most significant byte  
b14 b13 b12  
b15  
b11  
b3  
b10  
b2  
b9  
b1  
b8  
Table 5.  
Address least significant byte  
b6 b5 b4  
b7  
b0  
10/34  
M24128, M24C64, M24C32  
Memory organization  
3
Memory organization  
The memory is organized as shown in Figure 6.  
Figure 6. Block diagram  
WC  
E0  
E1  
E2  
High Voltage  
Generator  
Control Logic  
SCL  
SDA  
I/O Shift Register  
Address Register  
and Counter  
Data  
Register  
1 Page  
X Decoder  
AI06899  
11/34  
Device operation  
M24128, M24C64, M24C32  
4
Device operation  
2
The device supports the I C protocol. This is summarized in Figure 5. Any device that sends  
data on to the bus is defined to be a transmitter, and any device that reads the data to be a  
receiver. The device that controls the data transfer is known as the bus master, and the  
other as the slave device. A data transfer can only be initiated by the bus master, which will  
also provide the serial clock for synchronization. The M24C32, M24C64 and M24128  
devices are always slaves in all communications.  
4.1  
4.2  
Start condition  
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in  
the High state. A Start condition must precede any data transfer command. The device  
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock  
(SCL) for a Start condition, and will not respond unless one is given.  
Stop condition  
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable  
and driven High. A Stop condition terminates communication between the device and the  
bus master. A Read command that is followed by NoAck can be followed by a Stop condition  
to force the device into the Stand-by mode. A Stop condition at the end of a Write command  
triggers the internal Write cycle.  
4.3  
4.4  
Acknowledge bit (ACK)  
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,  
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits  
th  
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) Low to  
acknowledge the receipt of the eight data bits.  
Data Input  
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock  
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge  
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock  
(SCL) is driven Low.  
12/34  
M24128, M24C64, M24C32  
Device operation  
4.5  
Memory addressing  
To start communication between the bus master and the slave device, the bus master must  
initiate a Start condition. Following this, the bus master sends the Device Select Code,  
shown in Table 3 (on Serial Data (SDA), most significant bit first).  
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable  
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is  
1010b.  
2
Up to eight memory devices can be connected on a single I C bus. Each one is given a  
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is  
received, the device only responds if the Chip Enable Address is the same as the value on  
the Chip Enable (E0, E1, E2) inputs.  
th  
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.  
If a match occurs on the Device Select code, the corresponding device gives an  
th  
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match  
the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.  
Table 6.  
Mode  
Operating modes  
RW bit WC(1)  
Bytes  
Initial Sequence  
Current Address  
Read  
1
X
1
START, Device Select, RW = 1  
0
1
X
X
START, Device Select, RW = 0, Address  
reSTART, Device Select, RW = 1  
Random Address  
Read  
1
Similar to Current or Random Address  
Read  
Sequential Read  
Byte Write  
1
0
X
1  
VIL  
1
START, Device Select, RW = 0  
32 for M24C64  
and M24C32  
Page Write  
0
VIL  
START, Device Select, RW = 0  
64 for M24128  
1. X = V or V .  
IH  
IL  
13/34  
Device operation  
M24128, M24C64, M24C32  
Figure 7.  
Write mode sequences with WC = 1 (data write inhibited)  
WC  
ACK  
ACK  
ACK  
NO ACK  
DATA IN  
BYTE WRITE  
DEV SEL  
BYTE ADDR  
BYTE ADDR  
R/W  
WC  
ACK  
ACK  
ACK  
NO ACK  
DATA IN 1 DATA IN 2  
PAGE WRITE  
DEV SEL  
BYTE ADDR  
BYTE ADDR  
R/W  
WC (cont'd)  
NO ACK  
NO ACK  
PAGE WRITE  
(cont'd)  
DATA IN N  
AI01120C  
14/34  
M24128, M24C64, M24C32  
Device operation  
4.6  
Write operations  
Following a Start condition the bus master sends a Device Select Code with the Read/Write  
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two  
address bytes. The device responds to each address byte with an acknowledge bit, and  
then waits for the data Byte.  
Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write  
instruction with Write Control (WC) driven High (during a period of time from the Start  
condition until the end of the two address bytes) will not modify the memory contents, and  
the accompanying data bytes are not acknowledged, as shown in Figure 7.  
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant  
Byte (Table 4) is sent first, followed by the Least Significant Byte (Table 5). Bits b15 to b0  
form the address of the byte in memory.  
th  
When the bus master generates a Stop condition immediately after the Ack bit (in the “10  
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is  
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.  
After the Stop condition, the delay t , and the successful completion of a Write operation,  
W
the device’s internal address counter is incremented automatically, to point to the next byte  
address after the last one that was modified.  
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does  
not respond to any requests.  
4.7  
4.8  
Byte Write  
After the Device Select code and the address bytes, the bus master sends one data byte. If  
the addressed location is Write-protected, by Write Control (WC) being driven High, the  
device replies with NoAck, and the location is not modified. If, instead, the addressed  
location is not Write-protected, the device replies with Ack. The bus master terminates the  
transfer by generating a Stop condition, as shown in Figure 8.  
Page Write  
The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for  
the M24128) to be written in a single Write cycle, provided that they are all located in the  
same ’row’ in the memory: that is, the most significant memory address bits (b13-b6 for  
M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent  
than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be  
avoided, as data starts to become overwritten in an implementation dependent way.  
The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes  
of data (for the M24128), each of which is acknowledged by the device if Write Control (WC)  
is Low. If Write Control (WC) is High, the contents of the addressed memory location are not  
modified, and each data byte is followed by a NoAck. After each byte is transferred, the  
internal byte address counter (inside the page) is incremented. The transfer is terminated by  
the bus master generating a Stop condition.  
15/34  
Device operation  
M24128, M24C64, M24C32  
Figure 8.  
Write mode sequences with WC = 0 (data write enabled)  
WC  
ACK  
ACK  
ACK  
ACK  
BYTE WRITE  
DEV SEL  
BYTE ADDR  
BYTE ADDR  
DATA IN  
R/W  
WC  
ACK  
ACK  
ACK  
ACK  
PAGE WRITE  
DEV SEL  
BYTE ADDR  
BYTE ADDR  
DATA IN 1  
DATA IN 2  
R/W  
WC (cont'd)  
ACK  
ACK  
PAGE WRITE  
(cont'd)  
DATA IN N  
AI01106C  
16/34  
M24128, M24C64, M24C32  
Device operation  
Figure 9.  
Write cycle polling flowchart using ACK  
WRITE Cycle  
in Progress  
START Condition  
DEVICE SELECT  
with RW = 0  
ACK  
Returned  
NO  
First byte of instruction  
YES  
with RW = 0 already  
decoded by the device  
Next  
Operation is  
Addressing the  
Memory  
NO  
YES  
Send Address  
and Receive ACK  
ReSTART  
START  
NO  
YES  
STOP  
Condition  
DATA for the  
WRITE Operation  
DEVICE SELECT  
with RW = 1  
Continue the  
Continue the  
Random READ Operation  
WRITE Operation  
AI01847C  
4.9  
Minimizing system delays by polling on ACK  
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy  
of the data from its internal latches to the memory cells. The maximum Write time (tw) is  
shown in Table 17 and Table 18, but the typical time is shorter. To make use of this, a polling  
sequence can be used by the bus master.  
The sequence, as shown in Figure 9, is:  
Initial condition: a Write cycle is in progress.  
Step 1: the bus master issues a Start condition followed by a Device Select Code  
(the first byte of the new instruction).  
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned  
and the bus master goes back to Step 1. If the device has terminated the internal  
Write cycle, it responds with an Ack, indicating that the device is ready to receive  
the second part of the instruction (the first byte of this instruction having been sent  
during Step 1).  
17/34  
Device operation  
M24128, M24C64, M24C32  
Figure 10. Read mode sequences  
ACK  
NO ACK  
CURRENT  
ADDRESS  
READ  
DEV SEL  
DATA OUT  
R/W  
ACK  
ACK  
ACK  
ACK  
NO ACK  
DATA OUT  
RANDOM  
ADDRESS  
READ  
DEV SEL *  
BYTE ADDR  
BYTE ADDR  
DEV SEL *  
R/W  
R/W  
ACK  
ACK  
ACK  
NO ACK  
SEQUENTIAL  
CURRENT  
READ  
DEV SEL  
DATA OUT 1  
DATA OUT N  
R/W  
ACK  
ACK  
ACK  
ACK  
ACK  
SEQUENTIAL  
RANDOM  
READ  
DEV SEL *  
BYTE ADDR  
BYTE ADDR  
DEV SEL * DATA OUT 1  
R/W  
R/W  
ACK  
NO ACK  
DATA OUT N  
AI01105C  
1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes)  
must be identical.  
18/34  
M24128, M24C64, M24C32  
Device operation  
4.10  
Read operations  
Read operations are performed independently of the state of the Write Control (WC) signal.  
After the successful completion of a Read operation, the device’s internal address counter is  
incremented by one, to point to the next byte address.  
4.11  
Random Address Read  
A dummy Write is first performed to load the address into this address counter (as shown in  
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start  
condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The  
device acknowledges this, and outputs the contents of the addressed byte. The bus master  
must not acknowledge the byte, and terminates the transfer with a Stop condition.  
4.12  
4.13  
Current Address Read  
For the Current Address Read operation, following a Start condition, the bus master only  
sends a Device Select Code with the Read/Write bit (RW) set to 1. The device  
acknowledges this, and outputs the byte addressed by the internal address counter. The  
counter is then incremented. The bus master terminates the transfer with a Stop condition,  
as shown in Figure 10, without acknowledging the Byte.  
Sequential Read  
This operation can be used after a Current Address Read or a Random Address Read. The  
bus master does acknowledge the data byte output, and sends additional clock pulses so  
that the device continues to output the next byte in sequence. To terminate the stream of  
bytes, the bus master must not acknowledge the last byte, and must generate a Stop  
condition, as shown in Figure 10.  
The output data comes from consecutive addresses, with the internal address counter  
automatically incremented after each byte output. After the last memory address, the  
address counter ‘rolls-over’, and the device continues to output data from memory address  
00h.  
4.14  
Acknowledge in Read mode  
For all Read commands, the device waits, after each byte read, for an acknowledgment  
th  
during the 9 bit time. If the bus master does not drive Serial Data (SDA) Low during this  
time, the device terminates the data transfer and switches to its Stand-by mode.  
19/34  
Initial delivery state  
M24128, M24C64, M24C32  
5
Initial delivery state  
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).  
6
Maximum rating  
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to  
the device. These are stress ratings only, and operation of the device at these, or any other  
conditions outside those indicated in the Operating sections of this specification, is not  
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect  
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant  
quality documents.  
Table 7.  
Symbol  
Absolute maximum ratings  
Parameter  
Min.  
Max.  
Unit  
TA  
Ambient Operating Temperature  
Storage Temperature  
–40  
–65  
130  
150  
°C  
°C  
°C  
°C  
V
TSTG  
Lead Temperature during Soldering  
PDIP-Specific Lead Temperature during Soldering  
Input or Output range  
see note (1)  
TLEAD  
260(2)  
VIO  
VCC  
–0.50  
–0.50  
6.5  
Supply Voltage  
6.5  
V
VESD  
Electrostatic Discharge Voltage (Human Body model)(3) –4000  
4000  
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®  
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)  
2002/95/EU.  
2. TLEAD max must not be applied for more than 10s.  
3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500)  
20/34  
M24128, M24C64, M24C32  
DC and AC parameters  
7
DC and AC parameters  
This section summarizes the operating and measurement conditions, and the DC and AC  
characteristics of the device. The parameters in the DC and AC Characteristic tables that  
follow are derived from tests performed under the Measurement Conditions summarized in  
the relevant tables. Designers should check that the operating conditions in their circuit  
match the measurement conditions when relying on the quoted parameters.  
Table 8.  
Symbol  
Operating conditions (M24128-BW, M24C64-W, M24C32-W)  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply Voltage  
2.5  
–40  
–40  
5.5  
85  
V
Ambient Operating Temperature (Device Grade 6)  
Ambient Operating Temperature (Device Grade 3)  
°C  
°C  
125  
Table 9.  
Symbol  
Operating conditions (M24128-BR, M24C64-R, M24C32-R)  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply Voltage  
Ambient Operating Temperature  
1.8  
5.5  
85  
V
–40  
°C  
Table 10. Operating conditions (M24C64-F, M24C32-F)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply Voltage  
Ambient Operating Temperature  
1.7  
5.5  
85  
V
–20  
°C  
Table 11. AC test measurement conditions  
Symbol  
Parameter  
Load Capacitance  
Min.  
Max.  
Unit  
CL  
100  
pF  
ns  
V
Input Rise and Fall Times  
Input Levels  
50  
0.2VCC to 0.8VCC  
0.3VCC to 0.7VCC  
Input and Output Timing Reference Levels  
V
Figure 11. AC test measurement I/O waveform  
Input Levels  
Input and Output  
Timing Reference Levels  
0.8V  
CC  
CC  
0.7V  
CC  
0.3V  
CC  
0.2V  
AI00825B  
21/34  
DC and AC parameters  
M24128, M24C64, M24C32  
Table 12. Input parameters  
Symbol  
Parameter(1),(2)  
Test Condition  
Min.  
Max.  
Unit  
CIN  
CIN  
Input Capacitance (SDA)  
Input Capacitance (other pins)  
WC Input Impedance  
8
6
pF  
pF  
kΩ  
kΩ  
ZWCL  
ZWCH  
VIN < 0.3VCC  
VIN > 0.7VCC  
50  
200  
WC Input Impedance  
500  
Pulse width ignored  
(Input Filter on SCL and SDA)  
tNS  
200  
ns  
1. TA = 25°C, f = 400kHz  
2. Sampled only, not 100% tested.  
Table 13. DC characteristics (V = 2.5V to 5.5V, device grade 6)  
CC  
Test Condition  
(in addition to those in Table 8)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Input Leakage Current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Stand-by mode  
ILI  
ILO  
ICC  
ICC0  
± 2  
± 2  
2
µA  
µA  
Output Leakage Current  
Supply Current (Read)  
Supply Current (Write)  
Stand-by Supply Current  
VOUT = VSS or VCC, SDA in Hi-Z  
2.5V < VCC < 5.5V, fc=400kHz  
(rise/fall time < 30ns)  
mA  
mA  
µA  
During tW, 2.5V < VCC < 5.5V  
5(1)  
5
VIN = VSS or VCC  
,
VCC = 5.5V  
ICC1  
V
IN = VSS or VCC  
,
Stand-by Supply Current  
2
µA  
V
VCC = 2.5V  
Input Low Voltage (SDA,  
SCL, WC)  
VIL  
VIH  
VOL  
–0.45 0.3VCC  
0.7VCC VCC+1  
0.4  
Input High Voltage (SDA,  
SCL, WC)  
V
I
OL = 2.1mA, VCC = 2.5V or  
OL = 3mA, VCC = 5.5V  
Output Low Voltage  
V
I
1. Characterized value, not tested in production.  
22/34  
M24128, M24C64, M24C32  
DC and AC parameters  
Table 14. DC characteristics (V = 2.5V to 5.5V, device grade 3)  
CC  
Test Condition  
(in addition to those in Table 8)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Input Leakage Current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Stand-by mode  
ILI  
± 2  
± 2  
2
µA  
µA  
ILO  
Output Leakage Current  
Supply Current (Read)  
Supply Current (Write)  
Stand-by Supply Current  
VOUT = VSS or VCC, SDA in Hi-Z  
2.5V < VCC < 5.5V, fc=400kHz  
(rise/fall time < 30ns)  
ICC  
mA  
mA  
µA  
ICC0  
ICC1  
During tW, 2.5V < VCC < 5.5V  
5(1)  
10  
VIN = VSS or VCC  
,
2.5V < VCC < 5.5V  
Input Low Voltage (SDA,  
SCL, WC)  
VIL  
VIH  
VOL  
–0.45 0.3VCC  
0.7VCC VCC+1  
0.4  
V
V
V
Input High Voltage (SDA,  
SCL, WC)  
IOL = 2.1mA, VCC = 2.5V or  
IOL = 3mA, VCC = 5.5V  
Output Low Voltage  
1. Characterized value, not tested in production.  
Table 15. DC characteristics (V = 1.8V to 5.5V)  
CC  
Test Condition  
(in addition to those in Table 9)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Input Leakage Current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Stand-by mode  
ILI  
± 2  
± 2  
0.8  
3(1)  
1
µA  
µA  
ILO  
Output Leakage Current  
Supply Current (Read)  
Supply Current (Write)  
Stand-by Supply Current  
VOUT = VSS or VCC, SDA in Hi-Z  
VCC =1.8V, fc = 400kHz  
(rise/fall time < 30ns)  
ICC  
mA  
mA  
µA  
ICC0  
ICC1  
During tW, 1.8V < VCC < 2.5V  
VIN = VSS or VCC  
,
1.8V < VCC < 2.5V  
Input Low Voltage (SDA,  
SCL, WC)  
VIL  
–0.45  
0.3 VCC  
V
Input High Voltage (SDA,  
SCL, WC)  
VIH  
0.7VCC  
VCC+1  
0.2  
V
V
VOL  
Output Low Voltage  
IOL = 0.7 mA, VCC = 1.8 V  
1. Characterized value, not tested in production.  
23/34  
DC and AC parameters  
M24128, M24C64, M24C32  
(1)  
Table 16. DC characteristics (V = 1.7V to 5.5V)  
CC  
Test Condition  
(in addition to those in  
Table 10)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Input Leakage Current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Stand-by mode  
ILI  
± 2  
± 2  
0.8  
3(2)  
1
µA  
µA  
ILO  
Output Leakage Current  
Supply Current (Read)  
Supply Current (Write)  
Stand-by Supply Current  
VOUT = VSS or VCC, SDA in Hi-Z  
VCC =1.7V, fc = 400kHz  
(rise/fall time < 30ns)  
ICC  
mA  
mA  
µA  
ICC0  
ICC1  
During tW, 1.7V < VCC < 2.5V  
VIN = VSS or VCC  
,
1.7V < VCC < 2.5V  
Input Low Voltage (SDA,  
SCL, WC)  
VIL  
–0.45  
0.3 VCC  
V
Input High Voltage (SDA,  
SCL, WC)  
VIH  
0.7VCC  
VCC+1  
0.2  
V
V
VOL  
Output Low Voltage  
IOL = 0.7 mA, VCC = 1.7 V  
1. Preliminary data.  
2. Characterized value, not tested in production.  
24/34  
M24128, M24C64, M24C32  
DC and AC parameters  
Table 17. AC characteristics (V = 2.5V to 5.5V, device grades 6 and 3)  
CC  
Test conditions specified in Table 11 and Table 8  
Symbol  
Alt.  
Parameter  
Min.  
Max. Unit  
fC  
fSCL  
Clock Frequency  
400  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
tCHCL  
tHIGH Clock Pulse Width High  
tLOW Clock Pulse Width Low  
600  
1300  
20  
tCLCH  
(1)  
tDL1DL2  
tDXCX  
tCLDX  
tCLQX  
tF  
SDA Fall Time  
300  
tSU:DAT Data In Set Up Time  
tHD:DAT Data In Hold Time  
100  
0
tDH  
tAA  
Data Out Hold Time  
200  
200  
600  
600  
600  
(2)  
tCLQV  
Clock Low to Next Data Valid (Access Time)  
900  
(3)  
tCHDX  
tSU:STA Start Condition Set Up Time  
tHD:STA Start Condition Hold Time  
tSU:STO Stop Condition Set Up Time  
tDLCL  
tCHDH  
tDHDL  
tW  
tBUF  
tWR  
Time between Stop Condition and Next Start Condition 1300  
Write Time  
5
1. Sampled only, not 100% tested.  
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the  
falling or rising edge of SDA.  
3. For a reSTART condition, or following a Write cycle.  
Table 18. AC characteristics (V = 1.8V to 5.5V or V = 1.7V to 5.5V)  
CC  
CC  
Test conditions specified in Table 11 and Table 9 or Table 10  
Parameter Min.  
Symbol  
Alt.  
Max. Unit  
fC  
fSCL Clock Frequency  
400  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
tCHCL  
tCLCH  
tHIGH Clock Pulse Width High  
tLOW Clock Pulse Width Low  
600  
1300  
20  
(1)  
tDL1DL2  
tDXCX  
tCLDX  
tF  
SDA Fall Time  
300  
tSU:DAT Data In Set Up Time  
tHD:DAT Data In Hold Time  
100  
0
tCLQX  
tDH  
tAA  
Data Out Hold Time  
200  
200  
600  
600  
600  
1300  
(2)  
tCLQV  
Clock Low to Next Data Valid (Access Time)  
900  
(3)  
tCHDX  
tSU:STA Start Condition Set Up Time  
tDLCL  
tCHDH  
tDHDL  
tW  
tHD:STA Start Condition Hold Time  
tSU:STO Stop Condition Set Up Time  
tBUF Time between Stop Condition and Next Start Condition  
tWR  
Write Time  
10  
1. Sampled only, not 100% tested.  
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the  
falling or rising edge of SDA.  
3. For a reSTART condition, or following a Write cycle.  
25/34  
DC and AC parameters  
M24128, M24C64, M24C32  
Figure 12. AC waveforms  
tCHCL  
tCLCH  
SCL  
tDLCL  
SDA In  
tCHDX  
START  
Condition  
tCLDX  
tDXCX  
SDA  
Change  
tCHDH tDHDL  
START  
SDA  
Input  
STOP  
Condition  
Condition  
SCL  
SDA In  
tCHDH  
STOP  
tCHDX  
tW  
Write Cycle  
START  
Condition  
Condition  
SCL  
tCLQV  
tCLQX  
Data Valid  
SDA Out  
AI00795C  
26/34  
M24128, M24C64, M24C32  
Package mechanical  
8
Package mechanical  
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package outline  
E
b2  
A2  
A1  
A
L
c
b
e
eA  
eB  
D
8
E1  
1
PDIP-B  
1. Drawing is not to scale.  
Table 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data  
millimeters  
Min.  
inches  
Min.  
Symbol  
Typ.  
Max.  
Typ.  
Max.  
A
A1  
A2  
b
5.33  
0.210  
0.38  
2.92  
0.36  
1.14  
0.20  
9.02  
7.62  
6.10  
0.015  
0.115  
0.014  
0.045  
0.008  
0.355  
0.300  
0.240  
3.30  
0.46  
1.52  
0.25  
9.27  
7.87  
6.35  
2.54  
7.62  
4.95  
0.56  
1.78  
0.36  
10.16  
8.26  
7.11  
0.130  
0.018  
0.060  
0.010  
0.365  
0.310  
0.250  
0.100  
0.300  
0.195  
0.022  
0.070  
0.014  
0.400  
0.325  
0.280  
b2  
c
D
E
E1  
e
eA  
eB  
L
10.92  
3.81  
0.430  
0.150  
3.30  
2.92  
0.130  
0.115  
27/34  
Package mechanical  
M24128, M24C64, M24C32  
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package  
outline  
h x 45˚  
A2  
A
c
ccc  
b
e
0.25 mm  
D
GAUGE PLANE  
k
8
1
E1  
E
L
A1  
L1  
SO-A  
1. Drawing is not to scale.  
Table 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,  
package mechanical data  
millimeters  
Min  
inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
A
A1  
A2  
b
1.75  
0.25  
0.069  
0.010  
0.10  
1.25  
0.28  
0.17  
0.004  
0.049  
0.011  
0.007  
0.48  
0.23  
0.10  
5.00  
6.20  
4.00  
0.019  
0.009  
0.004  
0.197  
0.244  
0.157  
c
ccc  
D
4.90  
6.00  
3.90  
1.27  
4.80  
5.80  
3.80  
0.193  
0.236  
0.154  
0.050  
0.189  
0.228  
0.150  
E
E1  
e
h
0.25  
0°  
0.50  
8°  
0.010  
0°  
0.020  
8°  
k
L
0.40  
1.27  
0.016  
0.050  
L1  
1.04  
0.041  
28/34  
M24128, M24C64, M24C32  
Package mechanical  
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline  
D
8
5
c
E1  
E
1
4
α
A1  
L
A
A2  
L1  
CP  
b
e
TSSOP8AM  
1. Drawing is not to scale.  
Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data  
millimeters  
Min.  
inches  
Min.  
Symbol  
Typ.  
Max.  
Typ.  
Max.  
A
A1  
A2  
b
1.200  
0.150  
1.050  
0.300  
0.200  
0.100  
3.100  
0.0472  
0.0059  
0.0413  
0.0118  
0.0079  
0.0039  
0.1220  
0.050  
0.800  
0.190  
0.090  
0.0020  
0.0315  
0.0075  
0.0035  
1.000  
0.0394  
c
CP  
D
3.000  
0.650  
6.400  
4.400  
0.600  
1.000  
2.900  
0.1181  
0.0256  
0.2520  
0.1732  
0.0236  
0.0394  
0.1142  
e
E
6.200  
4.300  
0.450  
6.600  
4.500  
0.750  
0.2441  
0.1693  
0.0177  
0.2598  
0.1772  
0.0295  
E1  
L
L1  
α
0°  
8°  
0°  
8°  
29/34  
Package mechanical  
M24128, M24C64, M24C32  
Figure 16. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead  
2 × 3mm, package outline  
e
b
D
L1  
L3  
E
E2  
L
A
D2  
ddd  
A1  
UFDFPN-01  
1. Drawing is not to scale.  
Table 22. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead  
2 × 3mm, package mechanical data  
millimeters  
Min  
inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
A
A1  
b
0.55  
0.02  
0.25  
2.00  
1.60  
0.50  
0.00  
0.20  
1.90  
1.50  
0.60  
0.05  
0.30  
2.10  
1.70  
0.08  
3.10  
0.30  
0.022  
0.001  
0.010  
0.079  
0.063  
0.020  
0.000  
0.008  
0.075  
0.059  
0.024  
0.002  
0.012  
0.083  
0.067  
0.003  
0.122  
0.012  
D
D2  
ddd  
E
3.00  
0.20  
0.50  
0.45  
2.90  
0.10  
0.118  
0.008  
0.020  
0.018  
0.114  
0.004  
E2  
e
L
0.40  
0.50  
0.15  
0.016  
0.020  
0.006  
L1  
L3  
0.30  
0.012  
30/34  
M24128, M24C64, M24C32  
Part numbering  
9
Part numbering  
Table 23. Ordering information scheme  
Example:  
M24C32–  
W
MN 6  
T
P /B  
Device Type  
M24 = I2C serial access EEPROM  
Device Function  
128–B = 128 Kbit (16384 x 8)  
C64– = 64 Kbit (8192 x 8)  
C32– = 32 Kbit (4096 x 8)  
Operating Voltage  
W = VCC = 2.5 to 5.5V  
R = VCC = 1.8 to 5.5V  
F = VCC = 1.7 to 5.5V(1)  
Package  
BN = PDIP8  
MN = SO8 (150 mil width)  
DW = TSSOP8 (169 mil width)  
MB = UFDFPN8 (MLP8)(2)  
Device Grade  
6 = Industrial: device tested with standard test flow over –40 to 85 °C  
3 = Automotive: device tested with High Reliability Certified Flow(3) over –40 to 125°C.  
5 = Consumer: device tested with standard test flow over –20 to 85°C(1)  
Option  
blank = Standard Packing  
T = Tape and Reel Packing  
Plating Technology  
blank = Standard SnPb plating  
P or G = ECOPACK® (RoHS compliant)  
Process  
B = F6DP26% Rousset  
P = F6DP26% Chartered  
1. Device grade 5 is available only with the operating voltage option F.  
2. The UFDFPN8 package is available in M24C32-x devices only. It is not available in M24C64-x devices.  
3. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.  
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your  
nearest ST sales office for a copy.  
For a list of available options (speed, package, etc.) or for further information on any aspect  
of this device, please contact your nearest ST Sales Office.  
The category of Second Level Interconnect is marked on the package and on the inner box  
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to  
soldering conditions are also marked on the inner box label.  
31/34  
Revision history  
M24128, M24C64, M24C32  
10  
Revision history  
Table 24. Document revision history  
Date  
Revision  
Changes  
TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,  
PackageMechData).  
22-Dec-1999  
28-Jun-2000  
2.3  
2.4  
TSSOP8 package data corrected  
References to Temperature Range 3 removed from Ordering Information  
31-Oct-2000  
2.5  
Voltage range -S added, and range -R removed from text and tables  
throughout.  
Lead Soldering Temperature in the Absolute Maximum Ratings table  
amended  
20-Apr-2001  
2.6  
Write Cycle Polling Flow Chart using ACK illustration updated  
References to PSDIP changed to PDIP and Package Mechanical data  
updated  
Test condition for ILI made more precise, and value of ILI for E2-E0 and  
WC added  
16-Jan-2002  
02-Aug-2002  
2.7  
2.8  
-R voltage range added  
Document reformatted using new template.  
TSSOP8 (3x3mm² body size) package (MSOP8) added.  
5ms write time offered for 5V and 2.5V devices  
04-Feb-2003  
27-May-2003  
2.9  
SO8W package removed. -S voltage range removed  
2.10  
TSSOP8 (3x3mm² body size) package (MSOP8) removed  
Table of contents, and Pb-free options added. Minor wording changes in  
Summary Description, Power-On Reset, Memory Addressing, Write  
Operations, Read Operations. VIL(min) improved to -0.45V.  
22-Oct-2003  
01-Jun-2004  
3.0  
4.0  
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.  
Soldering temperature information clarified for RoHS compliant devices.  
Device Grade clarified  
Product List summary table added. Device Grade 3 added. 4.5-5.5V  
range is Not for New Design. Some minor wording changes. AEC-Q100-  
002 compliance. tNS(max) changed. VIL(min) is the same on all input  
pins of the device. ZWCL changed.  
04-Nov-2004  
05-Jan-2005  
5.0  
6.0  
UFDFPN8 package added. Small text changes.  
32/34  
M24128, M24C64, M24C32  
Revision history  
Table 24. Document revision history (continued)  
Date  
Revision  
Changes  
Document converted to new ST template.  
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.  
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.  
Section 2.1: Chip Enable (E0, E1, E2) and Section 2.2: Write Control  
(WC) modified, Section 2.3: Supply voltage (VCC) added and replaces  
Power On Reset: VCC Lock-Out Write Protect section.  
TA added, Note 1 updated and TLEAD specified for PDIP packages in  
Table 7: Absolute maximum ratings.  
ICC0 added, ICC voltage conditions changed and ICC1 specified over the  
whole voltage range in Table 13: DC characteristics (VCC = 2.5V to  
5.5V, device grade 6).  
29-Jun-2006  
7
ICC0 added, ICC frequency conditions changed and ICC1 specified over  
the whole voltage range in Table 15: DC characteristics (VCC = 1.8V to  
5.5V).  
tW modified in Table 17: AC characteristics (VCC = 2.5V to 5.5V, device  
grades 6 and 3).  
SO8N package specifications updated (see Figure 14 and Table 20).  
Device grade 5 added, B and P Process letters added to Table 23:  
Ordering information scheme. Small text changes.  
ICC1 modified in Table 13: DC characteristics (VCC = 2.5V to 5.5V,  
device grade 6).  
03-Jul-2006  
17-Oct-2006  
8
9
Note 1 added to Table 16: DC characteristics (VCC = 1.7V to 5.5V) and  
table title modified.  
UFDFPN8 package specifications updated (see Table 22). M24128-BW-  
and M24128-BR part numbers added.  
Generic part number corrected in Feature summary on page 1.  
ICC0 corrected in Table 14 and Table 13.  
Packages are ECOPACK® compliant.  
33/34  
M24128, M24C64, M24C32  
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34/34  

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