M24C64-FCS5TG/P [STMICROELECTRONICS]
8KX8 I2C/2-WIRE SERIAL EEPROM, PBGA8, 0.50 MM PITCH, ROHS COMPLIANT, WLCSP-8;
| 型号： | M24C64-FCS5TG/P |
| 厂家： | 
ST |
| 描述： | 8KX8 I2C/2-WIRE SERIAL EEPROM, PBGA8, 0.50 MM PITCH, ROHS COMPLIANT, WLCSP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总44页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C64-DF
M24C64-W M24C64-R M24C64-F
64 Kbit serial I²C bus EEPROM
Features
2
■ Compatible with all I C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Memory array:
PDIP8 (BN)
– 64 Kb (8 Kbytes) of EEPROM
– Page size: 32 bytes
– Additional Write lockable Page (M24C64-
DF)
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
SO8 (MN)
150 mil width
■ Single supply voltage:
– M24C64-W: 2.5 V to 5.5 V
– M24C64-R: 1.8 V to 5.5 V
– M24C64-xF: 1.7 V
■ Random and Sequential Read modes
■ Write protect of the whole memory array
■ Enhanced ESD/Latch-Up protection
■ More than 1 million Write cycles
■ More than 40-year data retention
■ Packages
TSSOP8 (DW)
169 mil width
– RoHS-compliant and halogen-free
(ECOPACK2®)
– PDIP8 package: RoHS-compliant
(ECOPACK1®)
UFDFPN8 (MB)
WLCSP5 (CS)
December 2011
Doc ID 16891 Rev 26
1/44
www.st.com
1
Contents
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
2.6.2
2.6.3
2.6.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 Lock Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . 18
4.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.15 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Contents
4.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.17 Read Identification Page (M24C64-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.18 Read the lock status (M24C64-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6
7
8
9
10
Doc ID 16891 Rev 26
3/44
List of tables
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (M24xxx-W - device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 33
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
Table 21.
Table 22.
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WLCSP-R 5-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23.
Table 24.
Table 25.
4/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
I C Fast mode (f = 400 kHz): maximum R
value versus bus parasitic
C
bus
capacitance (C ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bus
2
Figure 6.
I C Fast mode Plus (f = 1 MHz): maximum R
value versus bus
C
bus
parasitic capacitance (C ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bus
2
Figure 7.
Figure 8.
Figure 9.
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 33
Figure 16. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 34
Figure 17. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. WLCSP-R 5-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 16891 Rev 26
5/44
Description
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
1
Description
The M24C64-W operates with a supply voltage range of 2.5 V/5.5 V, the M24C64-R
operates with a supply voltage range of 1.8 V/5.5 V and the M24C64-F, M24C64-DF devices
operate with a supply voltage range of 1.7 V/5.5 V.
The M24C64-DF offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in read only mode.
Figure 1.
Logic diagram
6
##
ꢄ
%ꢀꢅ%ꢆ
3$!
-ꢆꢃXXX
3#,
7#
6
!)ꢀꢁꢂꢃꢃF
33
6/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Description
Table 1.
Signal names
Signal name
Function
Chip Enable
Direction
E2, E1, E0
SDA
Input
I/O
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
SCL
Input
Input
WC
VCC
VSS
Figure 2.
8-pin package connections
%ꢀ
%ꢁ
%ꢆ
ꢁ
ꢂ
ꢈ
ꢉ
ꢇ
6
##
7#
ꢆ
ꢄ
ꢃ
3#,
3$!
6
33
!)ꢀꢁꢂꢃꢇF
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
WLCSP connections (top view)
633
6$$
3$!
7#
3#,
-3ꢁꢂꢉꢇꢇ6ꢆ
Note:
Inputs E2, E1, E0 are internally connected to (001). Please refer to Section 2.3 for further
explanations.
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Doc ID 16891 Rev 26
7/44
Signal description
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V . (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
CC
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
2.3
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V . (Figure 5 indicates how
CC
the value of the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V
CC
or V , to establish the device select code as shown in Figure 4. When not connected (left
SS
floating), these inputs are read as low (0). For the WLCSP package, the (E2,E1,E0) inputs
are internally connected to (0,0,1).
Figure 4.
Device select code
V
V
CC
CC
M24xxx
M24xxx
E
E
i
i
V
V
SS
SS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. When unconnected, the signal is internally read as V , and
IL
Write operations are allowed.
When Write Control (WC) is driven high, device select and Address bytes are
acknowledged, Data bytes are not acknowledged.
8/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Signal description
2.5
VSS ground
V
is the reference for the V supply voltage.
CC
SS
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 7, Table 8 and
CC
CC
Table 9). In order to secure a stable DC supply voltage, it is recommended to decouple the
V
V
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
CC
/V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
2.6.2
2.6.3
Power-up conditions
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
defined in Table 7, Table 8 and Table 9. The rise time must not vary faster than 1 V/µs.
Device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V ), the device does not respond to any
CC
instruction until V has reached the power on reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Table 8 and Table 9). Until V
CC
CC
passes over the POR threshold, the device is reset and in Standby Power mode.
In a similar way, during power-down (continuous decay of V ), as soon as V drops below
CC
CC
the POR threshold voltage, the device is reset and stops responding to any instruction sent
to it.
2.6.4
Power-down conditions
During power-down (continuous decay of V ), the device must be in Standby Power mode
CC
(mode reached after decoding a Stop condition, assuming that there is no internal Write
cycle in progress).
Doc ID 16891 Rev 26
9/44
Signal description
Figure 5.
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
I C Fast mode (f = 400 kHz): maximum R value versus bus parasitic
2
C
bus
capacitance (C
)
bus
ꢁꢀꢀ
4HE 2
X # TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢃꢀꢀ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢎ
6
##
ꢁꢀ
2
BUS
(ERE 2
BUS
§ # ꢍ ꢁꢆꢀ NS
BUS
ꢃ K
3#,
3$!
)£# BUS
MASTER
-ꢆꢃXXX
ꢁ
ꢄꢀ P&
#
BUS
ꢁꢀ
ꢁꢀꢀ
"US LINE CAPACITOR ꢋP&ꢌ
ꢁꢀꢀꢀ
AIꢁꢃꢈꢊꢉB
2
Figure 6.
I C Fast mode Plus (f = 1 MHz): maximum R
value versus bus
C
bus
parasitic capacitance (C
)
bus
6
ꢁꢀꢀ
##
2
BUS
4HE 2
§ #
TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢁꢇꢀ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢎ
3#,
3$!
)£# BUS
MASTER
ꢁꢀ
ꢃ
-ꢆꢃXXX
(EREꢏ
#
§
BUS
ꢍ ꢁꢆꢀ NS
#
2
BUS
BUS
ꢁ
ꢁꢀ
ꢄꢀ
"US LINE CAPACITOR ꢋP&ꢌ
ꢁꢀꢀ
-3ꢁꢊꢈꢃꢇ6ꢁ
10/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Signal description
2
Figure 7.
I C bus protocol
SCL
SDA
SDA
Input
SDA
Change
Start
Condition
Stop
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
Start
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
Stop
Condition
AI00792B
Table 2.
Device select code
Device type identifier(1)
Chip Enable address(2)(3)
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
1
0
1
0
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E2, E1 and E0 are compared against the respective external pins on the memory device.
3. For the WLCSP package, the (E2,E1,E0) inputs are internally connected to (0,0,1).
Table 3.
Address most significant byte
b14 b13 b12
b15
b11
b3
b10
b2
b9
b1
b8
b0
Table 4.
Address least significant byte
b6 b5 b4
b7
Doc ID 16891 Rev 26
11/44
Memory organization
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
3
Memory organization
The memory is organized as shown in Figure 8.
Figure 8. Block diagram
WC
E0
E1
E2
High Voltage
Generator
Control Logic
SCL
SDA
I/O Shift Register
Address Register
and Counter
Data
Register
1 Page
X Decoder
AI06899
12/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Device operation
4
Device operation
2
The device supports the I C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
4.1
4.2
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
4.3
4.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Doc ID 16891 Rev 26
13/44
Device operation
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
4.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is
2
(a)
1010b. Up to eight memory devices can be connected on a single I C bus . Each one is
given a unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select
code is received, the device only responds if the Chip Enable Address is the same as the
value on the Chip Enable (E2, E1, E0) inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
Mode
Operating modes
RW bit WC(1)
Bytes
Initial sequence
Current Address
Read
1
X
1
Start, device select, RW = 1
0
1
X
X
Start, device select, RW = 0, Address
reStart, device select, RW = 1
Random Address
Read
1
Similar to Current or Random Address
Read
Sequential Read
1
X
≥ 1
Byte Write
Page Write
0
0
VIL
VIL
1
Start, device select, RW = 0
Start, device select, RW = 0
≤ 32
1. X = V or V .
IH
IL
a. Only one M24C64 in WLCSP package can be connected on the I²C bus (see Figure 4).
14/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Device operation
Figure 9.
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
Byte Write
Dev select
Byte address
Byte address
Data in
R/W
WC
ACK
ACK
ACK
NO ACK
Data in 2
Page Write
Dev select
Byte address
Byte address
Data in 1
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
Data in N
AI01120d
Doc ID 16891 Rev 26
15/44
Device operation
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
4.6
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 10, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Table 3) is sent first, followed by the Least Significant Byte (Table 4). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay t , and the successful completion of a Write operation,
W
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 9.
4.7
4.8
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 10.
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
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Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Figure 10. Write mode sequences with WC = 0 (data write enabled)
Device operation
WC
ACK
ACK
ACK
ACK
Byte Write
Dev Select
Byte address
Byte address
Data in
R/W
WC
ACK
ACK
ACK
ACK
Page Write
Dev Select
Byte address
Byte address
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
ACK
Page Write
(cont'd)
Data in N
AI01106d
4.9
Write Identification Page (M24C64-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. The Identification Page is written by issuing an
Write Identification Page instruction. This instruction uses the same protocol and format as
Page Write (into memory array), except for the following differences:
●
Device type identifier = 1011b
●
MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A4/A0 define the byte address inside the Identification Page.
If the Identification Page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
Doc ID 16891 Rev 26
17/44
Device operation
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
4.10
Lock Identification Page (M24C64-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification Page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●
●
●
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
If the Identification Page is locked, the data bytes transferred during the Lock Identification
Page instruction are not acknowledged (NoAck).
4.11
ECC (Error Correction Code) and Write cycling
The M24C64 devices identified with the process letter A or K offer an ECC (Error Correction
Code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC.
As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read
operation, the ECC detects it and replaces it by the correct value. The read reliability is
therefore much improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by word (4 bytes) at address 4*N
(where N is an integer) in order to benefit from the larger amount of Write cycles.
The M24C64 devices are qualified as 1 million (1,000,000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-byte words.
18/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Figure 11. Write cycle polling flowchart using ACK
Device operation
Write cycle
in progress
Start condition
Device select
with RW = 0
ACK
NO
Returned
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
operation is
addressing the
memory
NO
YES
Send address
and receive ACK
ReStart
Start
NO
YES
Stop
condition
Data for the
Write operation
Device select
with RW = 1
Continue the
Continue the
Random Read operation
Write operation
AI01847d
4.12
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 17, but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 11, is:
1. Initial condition: a Write cycle is in progress.
2. Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Doc ID 16891 Rev 26
19/44
Device operation
Figure 12. Read mode sequences
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
ACK
NO ACK
Current
Address
Read
Dev select
Data out
R/W
ACK
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev select *
Byte address
Byte address
Dev select *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequential
Current
Read
Dev select
Data out 1
R/W
ACK
ACK
ACK
ACK
R/W
ACK
Sequential
Random
Read
Dev select *
Byte address
Byte address
Dev select *
Data out 1
R/W
ACK
NO ACK
Data out N
AI01105d
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
20/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Device operation
4.13
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
4.14
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 12) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.15
4.16
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 12, without acknowledging the Byte.
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 12.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory
address 00h.
4.17
Read Identification Page (M24C64-D)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the Identification Page from location 10d, the
number of bytes should be less than or equal to 22, as the ID page boundary is 32 bytes).
Doc ID 16891 Rev 26
21/44
Device operation
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
4.18
Read the lock status (M24C64-D)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
●
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
●
Stop: the device is then set back into Standby mode by the Stop condition.
4.19
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
th
during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Initial delivery state
5
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
6
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TA
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
°C
V
TSTG
Lead temperature during soldering
PDIP-specific lead temperature during soldering
Input or output range
see note (1)
TLEAD
260(2)
VIO
IOL
–0.50
6.5
DC output current (SDA = 0)
Supply voltage
-
–0.50
-
5
mA
V
VCC
VESD
6.5
Electrostatic pulse (human body model)(3)
4000
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. TLEAD max must not be applied for more than 10 s.
3. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC
Std JESD22-A114, C1=100pF, R1=1500Ω, R2=500Ω)
Doc ID 16891 Rev 26
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DC and AC parameters
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
7
DC and AC parameters
Table 7.
Symbol
Operating conditions (M24xxx-W)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
–40
–40
-
5.5
85
125
1
V
°C
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
Operating clock frequency
°C
fC
MHz
Table 8.
Symbol
Operating conditions (M24xxx-R)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.8
–40
-
5.5
85
1
V
Ambient operating temperature
Operating clock frequency
°C
fC
MHz
Table 9.
Symbol
Operating conditions (M24xxx-F)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.7
–40
-
5.5
85
V
Ambient operating temperature
Operating clock frequency
°C
fC
400(1)
kHz
1. fCmax is 1 MHz under certain conditions, see Table 16, note 1.
Table 10. AC test measurement conditions
Symbol
Parameter
Load capacitance
Min.
Max.
Unit
Cbus
100
pF
ns
V
SCL input rise/fall time, SDA input fall time
Input voltage levels
50
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and output timing reference levels
V
Figure 13. AC test measurement I/O waveform
Input voltage levels
Input and output
timing reference
levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
MS19844V1
24/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 11. Input parameters
DC and AC parameters
Symbol
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
CIN
Input capacitance (SDA)
8
6
pF
pF
Input capacitance (other pins)
Input impedance
(E2, E1, E0, WC)
(2)
ZL
VIN < 0.3VCC
30
kΩ
kΩ
Input impedance
(E2, E1, E0, WC)
(2)
ZH
VIN > 0.7VCC
500
1. Characterized value, not tested in production.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 12. Memory cell characteristics
Symbol
Parameter
Test condition
Min.
Max.
Unit
Write cycle
Ncycle Endurance
TA = 25°C, 1.8 V < Vcc < 5.5 V 1,000,000
-
Note:
This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please refer to AN2014.
Doc ID 16891 Rev 26
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DC and AC parameters
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 13. DC characteristics (M24xxx-W, device grade 6)
Test conditions (see Table 7 and
Table 10)
Symbol
Parameter
Min.
Max.
Unit
Input leakage current
(SCL, SDA, E2, E1,
E0)
V
IN = VSS or VCC
ILI
2
µA
device in Standby mode
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
ILO
2
2
µA
2.5 V < VCC < 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
mA
ICC
Supply current (Read)
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
2.5
5(2)
mA
mA
ICC0
Supply current (Write) During tW, 2.5 V < VCC < 5.5 V
Device not selected(3), VIN = VSS or
2
µA
µA
V
VCC, VCC = 2.5 V
Standby supply
current
ICC1
Device not selected(3), VIN = VSS or
VCC, VCC = 5.5 V
5(4)
0.3VCC
6.5
Input low voltage
(SCL, SDA, WC)
VIL
VIH
VOL
–0.45
Input high voltage
(SCL, SDA)
0.7VCC
V
V
Input high voltage
(WC, E2, E1, E0)
0.7VCC VCC+0.6
0.4
IOL = 2.1 mA, VCC = 2.5 V or
Output low voltage
IOL = 3 mA, VCC = 5.5 V
1. Only for devices operating at fC max = 1 MHz (see Table 18)
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
4. The new M24C64-W devices (identified by the process letter K) offer ICC1 = 3µA (max)
26/44
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F
DC and AC parameters
Table 14. DC characteristics (M24xxx-W - device grade 3)
Test conditions (in addition to those
Symbol
Parameter
Min.
Max.
Unit
in Table 7 and Table 10)
Input leakage current
(SCL, SDA, E2, E1,
E0)
V
IN = VSS or VCC
ILI
2
2
µA
µA
device in Standby mode
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
ILO
ICC
Supply current (Read) fc = 400 kHz
Supply current (Write) During tW
2
mA
mA
ICC0
5(1)
Standby supply
current
Device not selected(2), VIN = VSS or
VCC
ICC1
VIL
10
0.3VCC
6.5
µA
V
Input low voltage
(SCL, SDA, WC)
–0.45
Input high voltage
(SCL, SDA)
0.7VCC
V
VIH
Input high voltage
(WC, E2, E1, E0)
V
0.7VCC VCC+0.6
I
OL = 2.1 mA, VCC = 2.5 V or
VOL
Output low voltage
0.4
V
IOL = 3 mA, VCC = 5.5 V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 16891 Rev 26
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DC and AC parameters
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 15. DC characteristics (M24xxx-R - device grade 6)
Test conditions(1) (in addition
to those in Table 8 and
Table 10)
Symbol
Parameter
Min.
Max.
Unit
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
VCC = 1.8 V, fc= 400 kHz
0.8
mA
ICC
Supply current (Read)
fc= 1 MHz(2)
2.5
3(3)
1
mA
mA
µA
ICC0
ICC1
Supply current (Write)
Standby supply current
During tW, 1.8 V < VCC < 2.5 V
Device not selected(4)
,
VIN = VSS or VCC, VCC = 1.8 V
Input low voltage
(SCL, SDA, WC)
VIL
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
6.5
V
V
Input high voltage
(SCL, SDA)
1.8 V ≤ VCC < 2.5 V
0.75VCC
VIH
Input high voltage
(WC, E2, E1, E0)
1.8 V ≤ VCC < 2.5 V
0.75VCC VCC+0.6
0.2
V
V
VOL
Output low voltage
IOL = 1 mA, VCC = 1.8 V
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see Table 18).
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
28/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 16. DC characteristics (M24xxx-F)
DC and AC parameters
Test conditions(1) (in addition
Symbol
Parameter
to those in Table 9 and
Table 10)
Min.
Max.
Unit
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
VCC = 1.7 V, fc= 400 kHz
0.8
mA
ICC
Supply current (Read)
fc= 1 MHz(2)
2.5
3(3)
1
mA
mA
µA
ICC0
ICC1
Supply current (Write)
Standby supply current
During tW, 1.7 V < VCC < 2.5 V
Device not selected(4)
,
VIN = VSS or VCC, VCC = 1.7 V
Input low voltage
(SCL, SDA, WC)
VIL
1.7 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
6.5
V
V
Input high voltage
(SCL, SDA)
1.7 V ≤ VCC < 2.5 V
0.75VCC
VIH
Input high voltage
(WC, E2, E1, E0)
1.7 V ≤ VCC < 2.5 V
0.75VCC VCC+0.6
0.2
V
V
VOL
Output low voltage
IOL = 1 mA, VCC = 1.7 V
1. If the application uses the voltage range F device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see Table 18).
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 16891 Rev 26
29/44
DC and AC parameters
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 17. 400 kHz AC characteristics
Symbol
Alt.
Parameter(1)
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tF
Clock frequency
-
400
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
SDA (out) fall time
600
1300
20(3)
120
(2)
tQL1QL2
tXH1XH2
tXL1XL2
tDXCX
(4)
(4)
tR
Input signal rise time
Input signal fall time
(4)
(4)
tF
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
tCLQX
tDH
tAA
Data out hold time
100(5)
100(5)
600
-
(6)(7)
tCLQV
tCHDL
Clock low to next data valid (access time)
900
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
-
-
-
tDLCL
600
tCHDH
600
Time between Stop condition and next Start
condition
tDHDL
tBUF
1300
-
ns
(8)(2)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(9)(2)
tDHWH
tW
tWR
Write time
5
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
80(10)
ns
(2)
tNS
-
1. Test conditions (in addition to those in Table 7, Table 8, Table 9 and Table 10).
2. Characterized value, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C < 400 kHz.
5. The new M24C64 device (identified by the process letter K) offers tCLQX = 100 ns (min) and tCLQV = 100 ns
(min), while the current device offers tCLQX = 200 ns (min) and tCLQV = 200 ns (min). Both series offer a
safe margin compared to the I2C specification which recommends tCLQV = 0 ns (min).
6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.
8. WC=0 set up time condition to enable the execution of a WRITE command.
9. WC=0 hold time condition to enable the execution of a WRITE command.
10. The current M24C64 device offers tNS=100 ns (max), the new M24C64 device (identified by the process
letter K) offers tNS=80 ns (max). Both products offer a safe margin compared to the 50 ns minimum value
recommended by the I2C specification.
30/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 18. 1 MHz AC characteristics
DC and AC parameters
(1)
Symbol
Alt.
Parameter(2)
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tHIGH Clock pulse width high
tLOW Clock pulse width low
260
tCLCH
400
-
(3)
(3)
tXH1XH2
tXL1XL2
tR
tF
tF
Input signal rise time
Input signal fall time
SDA (out) fall time
(3)
(3)
(8)
tQL1QL2
tDXCX
tCLDX
-
50
0
120
tSU:DAT Data in setup time
tHD:DAT Data in hold time
-
-
tCLQX
tDH
tAA
Data out hold time
100
-
(4)(5)
tCLQV
tCHDL
Clock low to next data valid (access time)
450
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
tDLCL
tCHDH
Time between Stop condition and next Start
condition
tDHDL
tBUF
500
-
ns
(6)(8)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(7)(8)
tDHWH
tW
tWR
Write time
5
ms
Pulse width ignored (input filter on SCL and
SDA)
(8)
tNS
-
80
ns
1. Only M24C64 and M24C64-D devices identified by the process letter K are qualified at 1 MHz.
2. Test conditions (in addition to those in Table 7, Table 8, Table 9 and Table 10).
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C < 400 kHz, or less than 120 ns when fC < 1 MHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 6.
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
8. Characterized only, not tested in production.
Doc ID 16891 Rev 26
31/44
DC and AC parameters
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Figure 14. AC waveforms
3TART
CONDITION
3TART
CONDITION
3TOP
CONDITION
T8,ꢁ8,ꢆ
T8(ꢁ8(ꢆ
T#(#,
T#,#(
3#,
T$,#,
T8,ꢁ8,ꢆ
3$! )N
7#
3$!
)NPUT
T#($,
T7,$,
T#,$8
T$8#(
3$!
#HANGE
T8(ꢁ8(ꢆ
T#($(
T$($,
T$(7(
3TOP
CONDITION
3TART
CONDITION
3#,
3$! )N
T7
7RITE CYCLE
T#($(
T#($,
3#,
T#,16
T#,18
$ATA VALID
T1,ꢁ1,ꢆ
$ATA VALID
3$! /UT
!)ꢀꢀꢈꢊꢇG
32/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 15. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
1. Drawing is not to scale.
Table 19. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
5.33
0.2098
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.0150
0.1150
0.0142
0.0449
0.0079
0.3551
0.3000
0.2402
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.1299
0.0181
0.0598
0.0098
0.3650
0.3098
0.2500
0.1000
0.3000
0.1949
0.0220
0.0701
0.0142
0.4000
0.3252
0.2799
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.4299
0.1500
3.30
2.92
0.1299
0.1150
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 16891 Rev 26
33/44
Package mechanical data
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Figure 16. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.75
0.25
0.0689
0.0098
0.10
1.25
0.28
0.17
0.0039
0.0492
0.0110
0.0067
0.48
0.23
0.10
5.00
6.20
4.00
–
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
–
c
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.1929
0.2362
0.1535
0.0500
0.1890
0.2283
0.1496
–
E
E1
e
h
0.25
0°
0.50
8°
k
0°
8°
L
0.40
1.27
0.0157
0.0500
L1
1.04
0.0410
1. Values in inches are converted from mm and rounded to four decimal digits.
34/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Package mechanical data
Figure 17. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 16891 Rev 26
35/44
Package mechanical data
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Figure 18. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline
-"
-#
E
B
E
B
$
,ꢁ
,ꢁ
,ꢄ
,ꢄ
0IN ꢁ
%ꢆ
+
%
%ꢆ
+
,
,
!
$ꢆ
$ꢆ
EEE
!ꢁ
1. Drawing is not to scale.
:7?-%E
2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to
be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 22. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
0.550
0.020
0.250
2.000
1.600
0.450
0.000
0.200
1.900
1.500
1.200
2.900
0.100
1.200
0.600
0.050
0.300
2.100
1.700
1.600
3.100
0.300
1.600
0.0217
0.0008
0.0098
0.0787
0.0630
0.0177
0.0000
0.0079
0.0748
0.0591
0.0472
0.1142
0.0039
0.0472
0.0236
0.0020
0.0118
0.0827
0.0669
0.0630
0.1220
0.0118
0.0630
A1
b
D
D2 (rev MB)
D2 (rev MC)
E
3.000
0.200
0.1181
0.0079
E2 (rev MB)
E2 (rev MC)
e
K
0.500
0.0197
0.300
0.300
0.0118
0.0118
L
0.500
0.150
0.0197
0.0059
L1
L3
0.300
0.080
0.0118
0.0031
eee(2)
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
36/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Package mechanical data
Figure 19. WLCSP-R 5-bump wafer-length chip-scale package outline
Eꢁ
$
ꢁ
ꢆ
ꢄ
#
Eꢆ
'
$ETAIL !
E
"
!
%
)NDEX
!ꢆ
&
)NDEX
!
7AFER BACK SIDE
3IDE VIEW
"UMP SIDE
"UMP
$ETAIL !
ROTATED BY ꢊꢀ
!ꢁ
B
-3ꢁꢂꢉꢇꢉ6ꢆ
1. Drawing is not to scale.
2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow).
Table 23. WLCSP-R 5-bump wafer-length chip-scale package mechanical data
millimeters
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.545
0.190
0.355
0.270
0.959
1.073
0.693
0.400
0.3465
0.280
0.190
0.490
0.600
0.0215
0.0075
0.0140
0.0106
0.0378
0.0422
0.0273
0.0157
0.0136
0.0110
0.0075
0.0193
0.0236
A1
A2
b(2)
D
1.074
1.168
0.0423
0.0460
E
e
e1
e2
F
G
N (number of terminals)
5
5
aaa
eee
0.110
0.060
0.0043
0.0024
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension measured at the maximum bump diameter parallel to primary datum Z.
Doc ID 16891 Rev 26
37/44
Part numbering
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
9
Part numbering
Table 24. Ordering information scheme
Example:
M24C64-D
W
MN 6
T
P /P
Device type
M24 = I2C serial access EEPROM
Device function
C64 = 64 Kbit (8192 x 8)
Device family
Blank: Without Identification page
-D: With additional Identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
BN = PDIP8(1)
MN = SO8 (150 mil width)(2)
DW = TSSOP8 (169 mil width)(2)
MB or MC = UFDFPN8 (MLP8)
CS = WLCSP-R
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
5 = Consumer: device tested with standard test flow over –20 to 85°C
3 = Device tested with high reliability certified flow(3) automotive
temperature range (-40 to 125 °C)
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(4)
P = F6DP26% Chartered
K = F8H process
1. ECOPACK1® (RoHS-compliant).
2. ECOPACK2® (RoHS-compliant and halogen-free).
3. ST strongly recommends the use of Automotive Grade devices for use in an automotive environment. The
high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
4. Process letter is used only for device grade 3 and WLCSP packages.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
38/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Revision history
10
Revision history
Table 25. Document revision history
Date
Revision
Changes
TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,
PackageMechData).
22-Dec-1999
28-Jun-2000
2.3
2.4
TSSOP8 package data corrected
References to Temperature Range 3 removed from Ordering Information
31-Oct-2000
2.5
Voltage range -S added, and range -R removed from text and tables
throughout.
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
20-Apr-2001
2.6
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data
updated
Test condition for ILI made more precise, and value of ILI for E2-E0 and
WC added
16-Jan-2002
02-Aug-2002
2.7
2.8
-R voltage range added
Document reformatted using new template.
TSSOP8 (3x3mm² body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
04-Feb-2003
27-May-2003
2.9
SO8W package removed. -S voltage range removed
2.10
TSSOP8 (3x3mm² body size) package (MSOP8) removed
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to -0.45V.
22-Oct-2003
01-Jun-2004
3.0
4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified
Product List summary table added. Device Grade 3 added. 4.5-5.5V
range is Not for New Design. Some minor wording changes. AEC-Q100-
002 compliance. tNS(max) changed. VIL(min) is the same on all input
pins of the device. ZWCL changed.
04-Nov-2004
05-Jan-2005
5.0
6.0
UFDFPN8 package added. Small text changes.
Doc ID 16891 Rev 26
39/44
Revision history
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 25. Document revision history (continued)
Date
Revision
Changes
Document converted to new ST template.
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.
Section 2.3: Chip Enable (E2, E1, E0) and Section 2.4: Write Control
(WC) modified, Section 2.6: Supply voltage (VCC) added and replaces
Power On Reset: VCC Lock-Out Write Protect section.
TA added, Note 1 updated and TLEAD specified for PDIP packages in
Table 6: Absolute maximum ratings.
ICC0 added, ICC voltage conditions changed and ICC1 specified over the
whole voltage range in Table 24: DC characteristics (M24xxx-W, device
grade 6).
29-Jun-2006
7
ICC0 added, ICC frequency conditions changed and ICC1 specified over
the whole voltage range in Table 26: DC characteristics (M24xxx-R -
device grade 6).
tW modified in Table 28: AC characteristics.
SO8N package specifications updated (see Figure 16 and Table 20).
Device grade 5 added, B and P Process letters added to Table 24:
Ordering information scheme. Small text changes.
ICC1 modified in Table 24: DC characteristics (M24xxx-W, device grade
6).
03-Jul-2006
17-Oct-2006
8
9
Note 1 added to Table 27: DC characteristics (M24xxx-F) and table title
modified.
UFDFPN8 package specifications updated (see Table 21). M24128-BW-
and M24128-BR part numbers added.
Generic part number corrected in Features on page 1.
ICC0 corrected in Table 25 and Table 24.
Packages are ECOPACK® compliant.
Available packages and temperature ranges by product specified in
Table 22, Table 24 and Table 25.
Notes modified below Table 23: Input parameters.
VIH max modified in DC characteristics tables (see Table 24, Table 25,
Table 26 and Table 27).
27-Apr-2007
10
C process code added to Table 24: Ordering information scheme.
For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007
on, tW will be 5 ms (see Table 28: AC characteristics.
Small text changes. Section 2.5: VSS ground and Section 4.9: ECC
(error correction code) and write cycling added.
VIL and VIH modified in Table 26: DC characteristics (M24xxx-R - device
grade 6).
27-Nov-2007
11
JEDEC standard reference updated below Table 6: Absolute maximum
ratings.
Package mechanical data inch values calculated from mm and rounded
to 4 decimal digits (see Section 8: Package mechanical data).
40/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 25. Document revision history (continued)
Revision history
Date
Revision
Changes
Added Section 2.6.2: Power-up conditions, updated Section 2.6.3:
Device reset, and Section 2.6.4: Power-down conditions in Section 2.6:
Supply voltage (VCC).
Updated Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6,
respectively, in Section 4.9: ECC (error correction code) and write
cycling.
Added temperature grade 6 in Table 21: Operating conditions (M24xxx-
F).
Updated test conditions for ILO and VLO in Table 24: DC characteristics
(M24xxx-W, device grade 6), Table 25: DC characteristics (M24xxx-W,
device grade 3), and Table 26: DC characteristics (M24xxx-R - device
grade 6).
18-Dec-2007
12
Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤
VCC < 2.5 V and 2.5 V ≤ VCC < 5.5 V in Table 27: DC characteristics
(M24xxx-F).
Updated Table 28: AC characteristics, and Table 17: AC characteristics
(M24xxx-F).
Updated Figure 14: AC waveforms.
Added M24128-BF in Table 25: Available M24C32 products (package,
voltage range, temperature grade).
Process B removed fromTable 24: Ordering information scheme.
Small text changes.
30-May-2008
15-Jul-2008
13
14
C Process option and Blank Plating technology option removed from
Table 24: Ordering information scheme.
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 8: Package
mechanical data). Section 4.9: ECC (error correction code) and write
cycling updated.
IOL added to Table 6: Absolute maximum ratings.
Table 24: Available M24C32 products (package, voltage range,
temperature grade) and Table 25: Available M24C32 products (package,
voltage range, temperature grade) updated.
16-Sep-2008
05-Jan-2009
15
16
I2C modes supported specified in Features on page 1.
Note removed from Table 27: DC characteristics (M24xxx-F). Small text
changes.
Doc ID 16891 Rev 26
41/44
Revision history
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 25. Document revision history (continued)
Date
Revision
Changes
32 and 128 Kbit densities removed.
ECOPACK status of packages specified on page 1 and in Table 24:
Ordering information scheme.
Section 2.6.2: Power-up conditions updated.
Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) updated. ECC section removed.
tNS modified in Table 23: Input parameters.
ICC1 and VIH updated in Table 24: DC characteristics (M24xxx-W, device
grade 6), Table 25: DC characteristics (M24xxx-W, device grade 3),
Table 26: DC characteristics (M24xxx-R - device grade 6) and Table 27:
DC characteristics (M24xxx-F). Note added to Table 26: DC
characteristics (M24xxx-R - device grade 6).
10-Dec-2009
17
Table 28: AC characteristics modified.
Figure 14: AC waveforms modified.
Note added below Figure 18: UFDFPN8 (MLP8) – 8-lead ultra thin fine
pitch dual flat package no lead 2 × 3mm, package outline.
Small text changes.
05-Feb-2010
15-Sep-2010
18
19
Number of bytes changed for Page Write in Table 5: Operating modes.
Updated tables (process letter K) under Section 6:
– Table 6: ESD HBM passes 3000 V
Updated tables (process letter K) under Section 7:
– Table 18 (1MHz AC) inserted,
– Table 17, Table 18: Tclqv(min) = 100 ns
– Table 17, Table 18: tNS = 80 ns
Added M24C64-DF device.
Updated Features, Section 1: Description, Section 4: Device operation.
Changed title of Figure 2: 8-pin package connections.
Updated Table 10: AC test measurement conditions.
Replaced Figure 18: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual
flat package no lead 2 × 3mm, package outline and Table 21: UFDFPN8
(MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm,
data.
16-Nov-2010
20
Added Table 29: M24C32-D product (package, voltage range,
temperature grade).
Added WLCSP in Features and Figure 4: WLCSP connections (top
view).
Updated Table 22: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat
package no lead 2 x 3 mm, data.
08-Dec-2010
14-Mar-2011
21
22
Updated Table 26: Available M24C32 products (package, voltage range,
temperature grade) and Table 29: M24C32-D product (package, voltage
range, temperature grade).
Updated information concerning E2, E1, E0 for the WLCSP package:
– note under Figure 3: WLCSP connections (top view)
– comment under Figure 4: Device select code
– note (3) under Table 2: Device select code
42/44
Doc ID 16891 Rev 26
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Table 25. Document revision history (continued)
Revision history
Date
Revision
Changes
Updated MLP8 package data and Section 9: Part numbering.
Added footnote (a) in Section 4.5: Memory addressing.
07-Apr-2011
23
Updated:
– Figure 3: WLCSP connections (top view)
– Table 6: Absolute maximum ratings
– Small text changes
18-May-2011
24
Added:
– Figure 12: Memory cell characteristics
Updated:
– Table 22: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat
package no lead 2 x 3 mm, data
– Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
– Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
08-Sep-2011
16-Dec-2011
25
26
Added tWLDL and tDHWH in:
– Table 17: 400 kHz AC characteristics
– Table 18: 1 MHz AC characteristics
– Figure 14: AC waveforms
Minor text changes.
Updated A dimension in Table 23: WLCSP-R 5-bump wafer-length chip-
scale package mechanical data.
Doc ID 16891 Rev 26
43/44
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
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Doc ID 16891 Rev 26
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