M24C64-WBN6GB [STMICROELECTRONICS]
8KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8;
| 型号： | M24C64-WBN6GB |
| 厂家： | 
ST |
| 描述： | 8KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8 存储 内存集成电路 光电二极管 双倍数据速率 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 |
| 文件： | 总26页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C64
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■
Two-Wire I2C Serial Interface
Supports 400kHz Protocol
Figure 1. Packages
■
Single Supply Voltage:
–
–
–
4.5 to 5.5V for M24Cxx
2.5 to 5.5V for M24Cxx-W
1.8 to 5.5V for M24Cxx-R
■
■
■
■
■
■
■
■
Write Control Input
BYTE and PAGE WRITE (up to 32 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
8
1
Automatic Address Incrementing
PDIP8 (BN)
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
8
1
SO8 (MN)
150 mil width
Table 1. Product List
Reference
Part Number
M24C64
M24C64
M24C32
M24C64-W
M24C64-R
M24C32
TSSOP8 (DW)
169 mil width
M24C32-W
M24C32-R
UFDFPN8 (MB)
2x3mm² (MLP)
January 2005
1/26
M24C64, M24C32
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO, TSSOP and UFDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/26
M24C64, M24C32
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Operating Conditions (M24Cxx-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. DC Characteristics (M24Cxx(1), M24Cxx-W6 and M24Cxx-W3). . . . . . . . . . . . . . . . . . . 16
Table 14. DC Characteristics (M24Cxx-W6 and M24Cxx-W3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3) . . . . . . . . . . . . . . . . . . . 18
Table 17. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 20
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 20
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 21
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 22
Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 22
Figure 16.UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm. . . 23
Table 21. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M24C64, M24C32
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Table 2. Signal Names
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
Figure 2. Logic Diagram
SCL
WC
V
CC
V
V
CC
SS
3
Power On Reset: VCC Lock-Out Write Protect
E0-E2
SDA
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until VCC has reached
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not re-
spond to any command. In the same way, when
VCC drops from the operating voltage, below the
Power On Reset (POR) threshold voltage, all op-
erations are disabled and the device will not re-
spond to any command.
M24C64
M24C32
SCL
WC
V
SS
AI01844B
A stable and valid VCC (as defined in Table 9. and
Table 10.) must be applied before applying any
logic signal.
I2C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I2C bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in Table 3.), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
M24C64
M24C32
E0
E1
E2
1
2
3
4
8
V
CC
WC
7
6
5
SCL
SDA
V
SS
AI01845C
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
4/26
M24C64, M24C32
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to VCC. (Figure 4. indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to VCC or VSS, to establish the Device Select
Code.
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
0
fc = 400kHz
C
BUS
10
100
(pF)
1000
C
BUS
AI01665
5/26
M24C64, M24C32
Figure 5. I2C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 3. Device Select Code
1
2
RW
b0
Device Type Identifier
Chip Enable Address
b7
b6
0
b5
1
b4
0
b3
E2
b2
b1
Device Select Code
1
E1
E0
RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 4. Most Significant Byte
Table 5. Least Significant Byte
b15
b14
b13 b12 b11
b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
6/26
M24C64, M24C32
MEMORY ORGANIZATION
The memory is organized as shown in Figure 6..
Figure 6. Block Diagram
WC
E0
High Voltage
Generator
Control Logic
E1
E2
SCL
SDA
I/O Shift Register
Address Register
and Counter
Data
Register
1 Page
X Decoder
AI06899
7/26
M24C64, M24C32
DEVICE OPERATION
The device supports the I2C protocol. This is sum-
marized in Figure 5.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24Cxx device is always
a slave in all communication.
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Start Condition
Memory Addressing
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the de-
vice only responds if the Chip Enable Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal Write
cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9th clock pulse period, the receiver pulls Serial
Table 6. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 32
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
8/26
M24C64, M24C32
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120C
Write Operations
slot), either at the end of a Byte Write or a Page
Write, the internal Write cycle is triggered. A Stop
condition at any other time slot does not trigger the
internal Write cycle.
After the Stop condition, the delay tW, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
Following a Start condition the bus master sends
a Device Select Code with the Read/Write bit
(RW) reset to 0. The device acknowledges this, as
shown in Figure 8., and waits for two address
bytes. The device responds to each address byte
with an acknowledge bit, and then waits for the
data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 7..
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4.) is sent first, followed by the Least Signifi-
cant Byte (Table 5.). Bits b15 to b0 form the
address of the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in Figure 8..
9/26
M24C64, M24C32
Page Write
The bus master sends from 1 to 32 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 5 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
The Page Write mode allows up to 32 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits
(b12-b5 for M24C64, and b11-b5 for M24C32) are
the same. If more bytes are sent than will fit up to
the end of the row, a condition known as ‘roll-over’
occurs. This should be avoided, as data starts to
become overwritten in an implementation depen-
dent way.
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106C
10/26
M24C64, M24C32
Figure 9. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
Minimizing System Delays by Polling On ACK
–
–
Initial condition: a Write cycle is in progress.
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
The maximum Write time (t ) is shown in Table
w
–
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
16. and Table 17., but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9., is:
11/26
M24C64, M24C32
Figure 10. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
dressed byte. The bus master must not
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in Figure 10., without acknowledg-
ing the byte.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 10.) but without sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
Read/Write bit (RW) set to 1. The device acknowl-
edges this, and outputs the contents of the ad-
12/26
M24C64, M24C32
Sequential Read
Acknowledge in Read Mode
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 10..
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9th bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
13/26
M24C64, M24C32
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 7. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
TLEAD
VIO
Parameter
Min.
Max.
150
1
Unit
Storage Temperature
–65
°C
Lead Temperature during Soldering
Input or Output range
°C
V
See note
–0.50
–0.50
–4000
6.5
6.5
VCC
Supply Voltage
V
2
VESD
4000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
14/26
M24C64, M24C32
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions (M24Cxx-6)
Symbol
Parameter
Min.
4.5
Max.
5.5
Unit
V
1
V
CC
Supply Voltage
TA
Ambient Operating Temperature
–40
85
°C
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
Table 9. Operating Conditions (M24Cxx-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
Supply Voltage
CC
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 10. Operating Conditions (M24Cxx-R)
Symbol
Parameter
Min.
1.8
Max.
5.5
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
15/26
M24C64, M24C32
Table 11. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
Input Levels
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Levels
V
CC
Figure 11. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
Table 12. Input Parameters
1,2
Symbol
CIN
Test Condition
Min.
Max.
8
Unit
pF
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
CIN
6
pF
ZWCL
ZWCH
VIN < 0.3VCC
VIN > 0.7VCC
50
200
kΩ
kΩ
WC Input Impedance
500
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
200
ns
Note: 1. T = 25°C, f = 400kHz
A
2. Sampled only, not 100% tested.
Table 13. DC Characteristics (M24Cxx(1), M24Cxx-W6 and M24Cxx-W3)
Test Condition
Symbol
Parameter
Min.
Max.
Unit
(in addition to those in Table 8.)
Input Leakage Current
(SCL, SDA, E2, E1, E0)
V
IN = VSS or VCC
ILI
± 2
µA
device in Stand-by mode
ILO
ICC
Output Leakage Current
Supply Current
V
OUT = VSS or VCC, SDA in Hi-Z
± 2
2
µA
mA
µA
V
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
ICC1
VIL
Stand-by Supply Current
Input Low Voltage
V
IN = VSS or VCC, VCC = 5 V
10
–0.45
0.3VCC
VCC+1
0.4
VIH
VOL
Input High Voltage
Output Low Voltage
0.7VCC
V
IOL = 3 mA, VCC = 5 V
V
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
16/26
M24C64, M24C32
Table 14. DC Characteristics (M24Cxx-W6 and M24Cxx-W3)
Test Condition
Symbol
Parameter
Min.
Max.
Unit
(in addition to those in Table 9.)
Input Leakage Current
(SCL, SDA, E2, E1, E0)
V
IN = VSS or VCC
ILI
± 2
± 2
1
µA
µA
device in Stand-by mode
ILO
ICC
Output Leakage Current
Supply Current
V
OUT = VSS or VCC, SDA in Hi-Z
V
CC =2.5V, f =400kHz (rise/fall time <
c
mA
30ns)
ICC1
VIL
Stand-by Supply Current
Input Low Voltage
V
IN = VSS or VCC, VCC = 2.5 V
2
µA
V
–0.45
0.3VCC
VCC+1
0.4
VIH
VOL
Input High Voltage
Output Low Voltage
0.7VCC
V
IOL = 2.1 mA, VCC = 2.5 V
V
Table 15. DC Characteristics (M24Cxx-R)
Test Condition
(in addition to those in Table 10.)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA, E2, E1, E0)
V
IN = VSS or VCC
ILI
± 2
± 2
0.8
µA
µA
device in Stand-by mode
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
VCC =1.8V, f =100kHz (rise/fall time <
c
mA
30ns)
ICC1
VIL
Stand-by Supply Current
Input Low Voltage
V
IN = VSS or VCC, VCC = 1.8 V
0.2
0.3 VCC
VCC+1
0.2
µA
V
–0.45
VIH
VOL
Input High Voltage
Output Low Voltage
0.7VCC
V
IOL = 0.7 mA, VCC = 1.8 V
V
17/26
M24C64, M24C32
Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3)
Test conditions specified in Table 11. and Table 8. or Table 9.
Symbol
fC
Alt.
fSCL
Parameter
Min.
Max.
Unit
kHz
ns
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
600
600
600
1300
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
ns
tCHDX
tDLCL
tCHDH
tDHDL
tW
Start Condition Hold Time
ns
Stop Condition Set Up Time
ns
Time between Stop Condition and Next Start Condition
Write Time
ns
5 or4 10
tWR
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. The Write Time of 5 ms only applies to devices bearing the process letter “B” in the package marking (on the top side of the pack-
age), otherwise (for devices bearing the process letter “N”) the Write Time is 10 ms. For further details, please contact your nearest
ST sales office, and ask for a copy of the Product Change Notice PCEE0036.
Table 17. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 11. and Table 10.
Symbol
fC
Alt.
fSCL
Parameter
Min.
Max.
Unit
kHz
ns
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
600
600
600
1300
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
ns
tCHDX
tDLCL
tCHDH
tDHDL
tW
Start Condition Hold Time
ns
Stop Condition Set Up Time
ns
Time between Stop Condition and Next Start Condition
Write Time
ns
tWR
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
18/26
M24C64, M24C32
Figure 12. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
19/26
M24C64, M24C32
PACKAGE MECHANICAL
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Note: Drawing is not to scale.
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
20/26
M24C64, M24C32
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data
millimeters
Symbol
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
21/26
M24C64, M24C32
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
22/26
M24C64, M24C32
Figure 16. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: Drawing is not to scale.
Table 21. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm,
Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
0.60
0.05
0.30
Typ
Max
0.024
0.002
0.012
A
A1
b
0.55
0.50
0.022
0.020
0.000
0.008
0.00
0.25
2.00
0.20
0.010
0.079
D
D2
ddd
E
1.55
1.65
0.05
0.061
0.065
0.002
3.00
0.118
E2
e
0.15
–
0.25
–
0.006
–
0.010
–
0.50
0.45
0.020
0.018
L
0.40
0.50
0.15
0.016
0.020
0.006
L1
L3
N
0.30
8
0.012
8
23/26
M24C64, M24C32
PART NUMBERING
Table 22. Ordering Information Scheme
Example:
M24C32
–
W MN
6
T
P
Device Type
2
M24 = I C serial access EEPROM
Device Function
64 = 64 Kbit (8192 x 8)
32 = 32 Kbit (4096 x 8)
Operating Voltage
(2)
blank = V = 4.5 to 5.5V
CC
W = V = 2.5 to 5.5V
CC
R = V = 1.8 to 5.5V
CC
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
(3)
MB = UFDFPN8 (MLP8)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
(1)
3 = Automotive: device tested with High Reliability Certified Flow over –40 to 125 °C.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = RoHS compliant
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
3. The UFDFPN8 package is available in M24C32 devices only. It is not available in M24C64 devices.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
24/26
M24C64, M24C32
REVISION HISTORY
Table 23. Document Revision History
Date
Rev.
Description of Revision
22-Dec-1999
28-Jun-2000
2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData).
2.4 TSSOP8 package data corrected
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables throughout.
31-Oct-2000
20-Apr-2001
16-Jan-2002
2.5
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
2.6 Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
Test condition for I made more precise, and value of I for E2-E0 and WC added
LI
LI
2.7
-R voltage range added
Document reformatted using new template.
02-Aug-2002
04-Feb-2003
2.8 TSSOP8 (3x3mm² body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
2.9 SO8W package removed. -S voltage range removed
27-May-2003 2.10 TSSOP8 (3x3mm² body size) package (MSOP8) removed
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.
V (min) improved to -0.45V.
22-Oct-2003
3.0
4.0
5.0
IL
Absolute Maximum Ratings for V (min) and V (min) improved. Soldering temperature
IO
CC
01-Jun-2004
information clarified for RoHS compliant devices. Device Grade clarified
Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New
Design. Some minor wording changes. AEC-Q100-002 compliance. t (max) changed.
04-Nov-2004
05-Jan-2005
NS
V (min) is the same on all input pins of the device. Z
changed.
IL
WCL
6.0 UFDFPN8 package added. Small text changes.
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M24C64, M24C32
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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