M24C64T-FCU [STMICROELECTRONICS]
64-Kbit serial IC bus EEPROM 4 balls CSP;
| 型号： | M24C64T-FCU |
| 厂家： | 
ST |
| 描述： | 64-Kbit serial IC bus EEPROM 4 balls CSP 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总36页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C64T-FCU
64-Kbit serial I²C bus EEPROM 4 balls CSP
Datasheet - production data
Features
• Compatible with the 400 kHz I²C protocol
• High speed 1MHz transfer rate
• Memory array:
– 64 Kbit (8 Kbyte) of EEPROM
– Page size: 32 byte
• Specific device code
• Supply voltage range:
WLCSP (CU)
– 1.7 V to 5.5 V
• Operating temperature range
– V = 1.7 V to 5.5V over -40°C / +85°C
CC
– V = 1.6 V to 5.5V over 0°C / +85°C
CC
• Write
– Byte Write within 5 ms
– Page Write within 5 ms
• Random and sequential Read modes
• Software Write protect
– Upper quarter memory array
– Upper half memory array
– Upper 3/4 memory array
– Whole memory array
• ESD protection
– Human Body Model: 4 kV
• More than 4 million Write cycles
• More than 200-years data retention
• Package
– WLCSP, RoHS and Halogen free compliant
®
(ECOPACK2 )
October 2015
DocID028393 Rev 1
1/36
This is information on a product in full production.
www.st.com
Contents
M24C64T-FCU
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1
2.4.2
2.4.3
2.4.4
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
5.1.2
5.1.3
5.1.4
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
5.2
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1
5.2.2
5.2.3
5.2.4
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read the Write Protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
7
8
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1
Ultra Thin WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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3
List of tables
M24C64T-FCU
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect register (Address = 1xxx.xxxx.xxxx.xxxxb) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
Table 13.
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14.
Table 15.
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List of figures
List of figures
Figure 1.
Figure 2.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4-bump WLCSP connections
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequence (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
2
Maximum R
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
C
Figure 10. Maximum R
value versus bus parasitic capacitance (C
)
bus
bus
2
for an I C bus at 1 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline with BSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Description
M24C64T-FCU
1
Description
The M24C64T-FCU is a 64-Kbit I2C-compatible EEPROM (Electrically Erasable
PROgrammable Memory) organized as 8 K × 8 bits
The M24C64T-FCU can be hooked on the same bus as the standard M24C64S-FCU and
M24C64M-FCU in WLCSP 4 bump, thanks to specific device select code. See Section 4.5:
Device addressing.
The M24C64T-FCU can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient
temperature range of -40 °C/+85 °C and with an extended supply voltage from 1.6 V to 5.5
V, over a reduced ambient temperature range.
The M24C64T-FCU is delivered in a 4-ball WLCSP package.
Figure 1. Logic diagram
9&&
6'$
0ꢅꢂ&ꢃꢂ7ꢆ)&8
6&/
966
06ꢀꢁꢂꢂꢃ9ꢄ
Table 1. Signal names
Signal name
Function
Direction
SDA
SCL
VCC
VSS
Serial Data
Serial Clock
Supply voltage
Ground
I/O
Input
-
-
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Description
Figure 2. 4-bump WLCSP connections
(top view, marking side, with balls on the underside)
ꢄ
ꢅ
ꢅ
ꢄ
$
%
9&&
6&/
6&/
9&&
$
6'$
966
966
6'$
%
0DUNLQJꢈVLGH
ꢉWRSꢈYLHZꢊ
%XPSꢈVLGH
ꢉERWWRPꢈYLHZꢊ
06Yꢀꢁꢂꢅꢇ9ꢄ
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Signal description
M24C64T-FCU
2
Signal description
2.1
Serial Clock (SCL)
SCL is an input. The signal applied on the SCL input is used to strobe the data available on
SDA(in) and to output the data on SDA(out).
2.2
2.3
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to V (Figure 9
CC
indicates how to calculate the value of the pull-up resistor).
VSS (ground)
V
is the reference for the V supply voltage.
CC
SS
2.4
Supply voltage (VCC)
2.4.1
Operating supply voltage (V )
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the V line with a suitable capacitor (usually from10 nF to
CC
100 nF) close to the V /V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (t ).
W
2.4.2
2.4.3
Power-up conditions
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V has reached the
CC
internal reset threshold voltage. This threshold is lower than the minimum V operating
CC
voltage (see Operating conditions in Section 8: DC and AC parameters). When V passes
CC
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until V reaches a valid and stable DC voltage within the
CC
specified [V (min), V (max)] range (see Operating conditions in Section 8: DC and AC
CC
CC
parameters).
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Signal description
In a similar way, during power-down (continuous decrease in V ), the device must not be
CC
accessed when V drops below V (min). When V drops below the power-on-reset
CC
CC
CC
threshold voltage, the device stops responding to any instruction sent to it.
2.4.4
Power-down conditions
During power-down (continuous decrease in V ), the device must be in the Standby Power
CC
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
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Memory organization
M24C64T-FCU
3
Memory organization
The memory is organized as shown below.
Figure 3. Block diagram
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)ꢅ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
ꢄ PAGE
8 DECODER
-3ꢀꢁꢂꢃꢁ6ꢄ
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Device operation
4
Device operation
2
The device supports the I C protocol. This is summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
2
Figure 4. I C bus protocol
3#,
3$!
3$!
)NPUT
3$!
#HANGE
34!24
#ONDITION
34/0
#ONDITION
ꢄ
ꢇ
ꢀ
ꢂ
ꢈ
ꢆ
3#,
3$!
!#+
-3"
34!24
#ONDITION
ꢄ
ꢇ
ꢀ
ꢂ
ꢈ
ꢆ
3#,
3$!
-3"
!#+
34/0
#ONDITION
!)ꢁꢁꢂꢆꢇ"
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Device operation
M24C64T-FCU
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
4.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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Device operation
4.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier(1)
Chip Enable address
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
0
0
0
RW
1. The most significant bit, b7, is sent first.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time.
If the device does not match the device select code, the device deselects itself from the bus,
and goes into Standby mode (therefore will not acknowledge the device select code).
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Instructions
M24C64T-FCU
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 5, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3. Most significant address byte
A15
A7
A14
A6
A13
A12
A11
A10
A9
A1
A8
A0
Table 4. Least significant address byte
A5 A4 A3 A2
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t is triggered. A Stop condition at any other time slot does not trigger the internal
W
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t ), the
W
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
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Instructions
5.1.1
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, the device replies with NoAck, and the location is
not modified, as shown in Figure 6. If, instead, the addressed location is not Write-
protected, the device replies with Ack, as shown in Figure 5. The bus master shall
terminates the transfer by generating a Stop condition.
Figure 5. Write mode sequence (data write enabled)
!#+
!#+
!#+
!#+
"YTE 7RITE
$EV SEL
"YTE ADDR
"YTE ADDR
$ATA IN
2ꢅ7
!#+
!#+
!#+
!#+
0AGE 7RITE
$EV SEL
"YTE ADDR
"YTE ADDR
$ATA IN ꢄ
$ATA IN ꢇ
2ꢅ7
!#+
!#+
0AGE 7RITE ꢊCONTgDꢋ
$ATA IN .
!)ꢁꢄꢄꢁꢉE
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Instructions
M24C64T-FCU
5.1.2
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if the page is not write-protected, as shown in Figure 5. If the page is write-protected,
the contents of the addressed memory location are not modified, and each data byte is
followed by a NoAck, as shown in Figure 6. After each transferred byte, the internal page
address counter is incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 6. Write mode sequence (data write inhibited)
ACK
ACK
ACK
NO ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
ACK
ACK
ACK
NO ACK
Data in 2
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
R/W
NO ACK
NO ACK
Page Write (cont'd)
Data in N
AI01120e
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Instructions
5.1.3
Write protection
By writing specific values in a register (Table 5) located at address 1xxx.xxxx.xxxx.xxxxb,
the memory array can be write-protected by blocks, which size can be defined as:
•
•
•
•
the upper quarter memory array
the upper half memory array
the upper 3/4 memory array
the whole memory array
Table 5. Write Protect register (Address = 1xxx.xxxx.xxxx.xxxxb)
b7
x
b6
x
b5
x
b4
x
b3
b2
b1
b0
Write
Read
Size of write
protected
block
Write protect
activation
Size of write
protected block
Write protect
lock
0
0
0
0
Note:
Location 1xxx.xxxx.xxxx.xxxxb is outside of the addressing field of the EEPROM memory
(16 Kbytes are addressed within the 00xx.xxxx.xxxx.xxxx range)
•
Bit b3 enables or disables the Write protection
–
–
b3=0: the whole memory can be written (no Write protection)
b3=1: the concerned block is write-protected
•
Bits b2 and b1 define the size of the memory block to be protected against write
instructions
–
–
–
–
b2,b1=0,0: the upper quarter of memory is write-protected
b2,b1=0,1: the upper half memory is write-protected
b2,b1=1,0: the upper 3/4 of memory are write-protected
b2,b1=1,1: the whole memory is write-protected
•
•
bit b0 locks the write protect status
–
–
b0=0: bits b3,b2,b1,b0 can be modified
b0=1: bits b3,b2,b1,b0 cannot be modified and therefore the memory write
protection is frozen.
b7, b6, b5, b4 bits are Don't Care bits.
Writing the Write Protect register
Writing in the Write protect register is performed with a Byte Write instruction at address
1xxx.xxxx.xxxx.xxxxb. Bits b7,b6,b5,b4 of the data byte are not significant (Don't Care).
Writing more than one byte will discard the write cycle (Write protect register content will not
be changed).
DocID028393 Rev 1
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35
Instructions
M24C64T-FCU
5.1.4
Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 7, is:
•
Initial condition: a Write cycle is in progress.
•
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
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1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
18/36
DocID028393 Rev 1
M24C64T-FCU
Instructions
5.2
Read operations
Read operations are performed independently of the Write protection state.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 8. Read mode sequences
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5.2.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 8) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
DocID028393 Rev 1
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35
Instructions
M24C64T-FCU
5.2.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 8, without acknowledging the byte.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 8.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.2.4
Read the Write Protect register
Reading the Write Protect register is performed with a Random Read instruction at address
1xxx.xxxx.xxxx.xxxxb. Bits b7, b6, b5, b4 of the Write Protect register content are read as
0, 0, 0, 0. The signification of the Protect Register lower bits b3, b2, b1, b0 are defined in
Section 5.1.3: Write protection.
Reading more than one byte will loop on reading the Write Protect Register value.
The Write Protect register cannot be read while a write cycle (t ) is ongoing.
w
20/36
DocID028393 Rev 1
M24C64T-FCU
Initial delivery state
6
Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh) and
the Write Protect register set to 0 (00h).
DocID028393 Rev 1
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35
Maximum rating
M24C64T-FCU
7
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 6. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
-
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VIO
Lead temperature during soldering
Input or output range
see note(1)
–0.50
6
5
IOL
DC output current (SDA = 0)
Supply voltage
-
–0.50
-
mA
V
VCC
VESD
6
Electrostatic pulse (Human Body model)(2)
4000
V
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with , C1=100 pF, R1=1500 Ω).
22/36
DocID028393 Rev 1
M24C64T-FCU
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 7. Test conditions
Symbol
Parameter
Min.
Unit
Data retention(1)
Cycling
TA = 55 °C
TA = 25 °C
200
year
4 million
cycle
1. The data retention behavior is checked in production. The 200-year limit is defined from characterization
and qualification results.
Table 8. Operating conditions
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply voltage
1.60
–40
0
1.70
–40
–40
5.5
V
Ambient operating temperature: READ
Ambient operating temperature: WRITE
Operating clock frequency, VCC = 1.6 V
Operating clock frequency, VCC = 1.7 V
TA
85
°C
-
-
400
fC
kHz
1000
DocID028393 Rev 1
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35
DC and AC parameters
M24C64T-FCU
Table 9. DC characteristics
Test conditions
Symbol
Parameter
Min.
Max.
Unit
Input leakage current VIN = VSS or VCC
ILI
-
-
± 2
± 2
µA
µA
(SCL, SDA)
device in Standby mode
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
ILO
VCC < 1.8 V, fC = 400 kHz
-
-
-
0.8
2
mA
mA
mA
ICC
Supply current (Read)
VCC >= 1.8 V, fC = 400 kHz
VCC >= 1.8 V, fC = 1 MHz(1)
2.5
Supply current
(Write)(2)
ICC0
During tW
-
2
mA
µA
µA
µA
V
(3)
Device not selected
VIN = VSS or VCC, VCC = 1.8 V
,
-
1
Standby supply
current
Device not selected (3)
VIN = VSS or VCC, VCC = 2.5 V
,
ICC1
-
-
2
3
Device not selected (3)
VIN = VSS or VCC, VCC = 5.5 V
,
Input low voltage
(SCL, SDA)
VIL
VIH
-
–0.45
0.25 VCC
Input high voltage
(SCL, SDA)
-
0.75 VCC VCC + 1
V
I
OL = 1 mA, VCC < 1.8 V
-
-
-
0.2
0.4
0.4
V
V
V
VOL
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V
IOL = 3 mA, VCC = 5.5 V
1. Only for devices operating at fcMax = 1 MHz (See Table 8)
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
24/36
DocID028393 Rev 1
M24C64T-FCU
DC and AC parameters
Table 10. 400 kHz AC characteristics
Parameter
Symbol
Alt.
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tF
Clock frequency
-
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
SDA (out) fall time
600
-
-
1300
20 (2)
300
(1)
tQL1QL2
tXH1XH2
tXL1XL2
tDXCH
(3)
(3)
tR
Input signal rise time
Input signal fall time
(3)
(3)
tF
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
(4)
tCLQX
tDH
tAA
Data out hold time
50
-
(5)
tCLQV
Clock low to next data valid (access time)
-
900
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
600
600
600
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
tWR
-
1300
-
ns
ms
ns
Write time
-
-
5
Pulse width ignored (input filter on SCL and
SDA) - single glitch
(1)
tNS
50
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C
specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C < 400 kHz.
4. The min value for tCLQX (Data out hold time) offers a safe timing to bridge the undefined region of the falling
edge SCL.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is less than 400 ns.
DocID028393 Rev 1
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DC and AC parameters
Symbol
M24C64T-FCU
Table 11. 1 MHz AC characteristics
Parameter
Alt.
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tR
Clock frequency
0
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
260
tCLCH
700(1)
-
(2)
(2)
tXH1XH2
tXL1XL2
(2)
(2)
tF
(3)
tQL1QL2
tF
20(4)
50
120
tDXCH
tCLDX
tSU:DAT Data in setup time
tHD:DAT Data in hold time
-
0
-
(5)
tCLQX
tDH
tAA
Data out hold time
50
-
(6)
tCLQV
Clock low to next data valid (access time)
-
650
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
tWR
-
500
-
ns
ms
ns
Write time
-
-
5
Pulse width ignored (input filter on SCL and
SDA)
(3)
tNS
50
1. 600ns when -20°C ≤ t°≤ +85°C. Characterized only, not tested in production.
2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
f
C < 1 MHz.
3. Characterized only, not tested in production.
4. With CL = 10 pF.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 10.
26/36
DocID028393 Rev 1
M24C64T-FCU
DC and AC parameters
Figure 9. Maximum R
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz
C
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for an I C bus at 1 MHz
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DocID028393 Rev 1
27/36
35
DC and AC parameters
M24C64T-FCU
Figure 11. AC waveforms
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28/36
DocID028393 Rev 1
M24C64T-FCU
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
9.1
Ultra Thin WLCSP package information
Figure 12. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline
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1. Drawing is not to scale.
DocID028393 Rev 1
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35
Package mechanical data
M24C64T-FCU
Table 12. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b(2)
D
0.2400
0.2700
0.0950
0.1750
0.1850
0.8330
0.8330
0.4000
0.5000
0.2170
0.1670
0.1100
0.1100
0.1100
0.0600
0.0600
0.3000
0.0094
0.0106
0.0037
0.0069
0.0073
0.0328
0.0328
0.0157
0.0197
0.0085
0.0066
0.0043
0.0043
0.0043
0.0024
0.0024
0.0118
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8530
0.0336
E
0.8530
0.0336
e
-
-
-
-
-
-
-
-
e1
F
G
aaa
bbb
ccc
ddd
eee
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z
30/36
DocID028393 Rev 1
M24C64T-FCU
Package mechanical data
Figure 13. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline with BSC
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1. Drawing is not to scale.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
DocID028393 Rev 1
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35
Package mechanical data
M24C64T-FCU
Table 13. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
0.265
0.295
0.095
0.200
0.025
0.185
0.833
0.833
0.400
0.500
0.217
0.167
-
0.330
0.0104
0.0116
0.0037
0.0079
0.0010
0.0073
0.0328
0.0328
0.0157
0.0197
0.0085
0.0066
-
0.0130
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A2
-
-
A3 (BSC)
b(2) (3)
D
-
-
-
-
0.853
0.853
-
0.0336
0.0336
-
E
e
e1
-
-
F
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.110
0.110
0.110
0.060
0.060
0.0043
0.0043
0.0043
0.0024
0.0024
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Figure 14. Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package recommended footprint
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H
$ꢋ=ꢇB)3B9ꢄ
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Part numbering
10
Part numbering
Table 14. Ordering information scheme
Example:
M24 C64T -F CU 6
T
/T
F
Device type
M24 = I2C serial access EEPROM
Device function
C64T = 64 Kbits (8 K x 8 bits)
Operating voltage
F = VCC = 1.7 V to 5.5 V
Package(1)
CU = ultra-thin 4-bump WLCSP
Device grade
6 = device tested with standard test flow over –40 to 85 °C
Packing
T = Tape and reel packing
Process technology(2)
/T = Process letter
Option
blank = no Back Side Coating (WLCSP height = 0.300mm)
F = Back Side Coating (WLCSP height = 0.330mm)
1. The package is ECOPACK2® (RoHS compliant and free of brominated, chlorinated and antimony oxide
flame retardants).
2. The process letter appears on the device package (marking) and on the shipment box. Please contact
your nearest ST Sales Office for further information.
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M24C64T-FCU
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
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Revision history
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Revision history
Table 15. Document revision history
Changes
Date
Revision
06-Oct-2015
1
Initial release
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© 2015 STMicroelectronics – All rights reserved
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