M25P80VMW3TP [STMICROELECTRONICS]
1MX8 FLASH 2.7V PROM, PDSO8, 0.200 INCH, ROHS COMPLIANT, PLASTIC, SO-8;
| 型号： | M25P80VMW3TP |
| 厂家： | 
ST |
| 描述： | 1MX8 FLASH 2.7V PROM, PDSO8, 0.200 INCH, ROHS COMPLIANT, PLASTIC, SO-8 可编程只读存储器 光电二极管 |
| 文件： | 总41页 (文件大小：565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25P80
8 Mbit, Low Voltage, Serial Flash Memory
With 40MHz SPI Bus Interface
FEATURES SUMMARY
■
8 Mbit of Flash Memory
Figure 1. Packages
■
Page Program (up to 256 Bytes) in 1.4ms
(typical)
■
■
■
■
■
■
■
■
Sector Erase (512 Kbit) in 1s (typical)
Bulk Erase (8 Mbit) in 10s (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
40MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Electronic Signature (13h)
VFQFPN8 (MP)
(MLP8)
Packages
–
ECOPACK® (RoHS compliant)
8
1
SO8 (MW)
200 mil width
October 2005
1/41
M25P80
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active Power, Stand-by Power and Deep Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/41
M25P80
Release from Deep Power-down and Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . 24
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3/41
M25P80
SUMMARY DESCRIPTION
The M25P80 is a 8 Mbit (1M x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 16 sectors, each con-
taining 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 4096 pages, or 1,048,576 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Table 1. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
Q
S
W
HOLD
V
Supply Voltage
Ground
CC
V
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
SS
Figure 3. VFQFPN and SO8 Connections
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
V
M25P80
CC
S
Q
1
2
3
4
8
V
CC
HOLD
7
D
C
S
Q
W
6
5
C
D
V
SS
AI04965B
M25P80
W
HOLD
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to V , and
must not be allowed to be connected to any other voltage
or signal line on the PCB.
SS
V
SS
AI04964
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
4/41
M25P80
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving
Chip Select (S) Low enables the device, placing it
in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP2,
BP1 and BP0 bits of the Status Register).
5/41
M25P80
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746D
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
6/41
M25P80
OPERATING FEATURES
Page Programming
To program one data byte, two instructions are re-
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is followed by the
internal Program cycle (of duration tPP).
When Chip Select (S) is High, the device is dis-
abled, but could remain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write Status Register). The device then
goes in to the Stand-by Power mode. The device
consumption drops to ICC1
.
The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
consumption drops further to ICC2. The device re-
mains in this mode until another specific instruc-
tion (the Release from Deep Power-down Mode
and Read Electronic Signature (RES) instruction)
is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase
instructions.
To spread this overhead, the Page Program (PP)
instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Page Program (PP), Instruction Times (De-
vice Grade 6) and Instruction Times (Device
Grade 3)).
Sector Erase and Bulk Erase
Status Register
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration tSE or tBE).
The Status Register contains a number of status
and control bits that can be read or set (as appro-
priate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
cates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0)
become read-only bits.
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (tW, tPP, tSE, or tBE). The Write In
Progress (WIP) bit is provided in the Status Regis-
ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com-
plete.
Active Power, Stand-by Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode.
7/41
M25P80
Protection Modes
–
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P80 boasts the
following data protection mechanisms:
–
–
–
■
■
The Block Protect (BP2, BP1, BP0) bits allow
part of the memory to be configured as read-
only. This is the Software Protected Mode
(SPM).
The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be
protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
■
■
■
Power-On Reset and an internal timer (tPUW
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit . This bit is returned to its reset state
by the following events:
)
■
–
–
Power-up
Write Disable (WRDI) instruction
completion
Table 2. Protected Area Sizes
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protected Area
Unprotected Area
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
All sectors (sixteen sectors: 0 to 15)
Upper sixteenth (Sector 15)
Lower fifteen-sixteenths (fifteen sectors: 0 to 14)
Upper eighth (two sectors: 14 and 15)
Upper quarter (four sectors: 12 to 15)
Upper half (eight sectors: 8 to 15)
All sectors (sixteen sectors: 0 to 15)
All sectors (sixteen sectors: 0 to 15)
All sectors (sixteen sectors: 0 to 15)
Lower seven-eighths (fourteen sectors: 0 to 13)
Lower three-quarters (twelve sectors: 0 to 11)
Lower half (eight sectors: 0 to 7)
none
none
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
8/41
M25P80
Hold Condition
rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in Figure
6.).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in Fig-
ure 6.).
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts af-
ter Serial Clock (C) next goes Low. Similarly, if the
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (S) goes High while the device is in
the Hold condition, this has the effect of resetting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the device from going back
to the Hold condition.
Figure 6. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
AI02029D
9/41
M25P80
MEMORY ORGANIZATION
The memory is organized as:
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
■
■
■
1,048,576 bytes (8 bits each)
16 sectors (512 Kbits, 65536 bytes each)
4096 pages (256 bytes each).
Table 3. Memory Organization
Sector
Address Range
FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
15
14
13
12
11
10
9
F0000h
E0000h
D0000h
C0000h
B0000h
A0000h
90000h
80000h
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
8
7
6
5
4
3
2
1
0
10/41
M25P80
Figure 7. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
FFFFFh
Size of the
read-only
memory area
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI04987
11/41
M25P80
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
quence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a
byte boundary, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses
after Chip Select (S) being driven Low is an exact
multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
The instruction set is listed in Table 4..
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep
Power-down, and Read Electronic Signature
(RES) instruction, the shifted-in instruction se-
Table 4. Instruction Set
Address Dummy
Data
Bytes
Instruction
Description
Write Enable
One-byte Instruction Code
Bytes
Bytes
WREN
WRDI
RDSR
WRSR
READ
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
06h
04h
05h
01h
03h
0Bh
02h
D8h
C7h
B9h
0
0
0
0
3
3
3
3
0
0
0
0
0
0
0
1
0
0
0
0
0
Write Disable
0
1 to ∞
1
Read Status Register
Write Status Register
Read Data Bytes
1 to ∞
1 to ∞
1 to 256
0
FAST_READ Read Data Bytes at Higher Speed
PP
SE
BE
DP
Page Program
Sector Erase
Bulk Erase
0
Deep Power-down
0
Release from Deep Power-down,
and Read Electronic Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-down
0
12/41
M25P80
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 8. Write Enable (WREN) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
–
–
–
Figure 9. Write Disable (WRDI) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
13/41
M25P80
Read Status Register (RDSR)
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or
Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) in-
struction. When one or both of the Block Protect
(BP2, BP1, BP0) bits is set to 1, the relevant mem-
ory area (as defined in Table 2.) becomes protect-
ed against Page Program (PP) and Sector Erase
(SE) instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hard-
ware Protected mode has not been set. The Bulk
Erase (BE) instruction is executed if, and only if,
both Block Protect (BP2, BP1, BP0) bits are 0.
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 10..
Table 5. Status Register Format
b7
b0
SRWD
0
0
BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
Block Protect Bits
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP2, BP1,
BP0) become read-only bits and the Write Status
Register (WRSR) instruction is no longer accepted
for execution.
Write Enable Latch Bit
Write In Progress Bit
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
14/41
M25P80
Write Status Register (WRSR)
(whose duration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable
Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP2, BP1, BP0) bits, to define the size of
the area that is to be treated as read-only, as de-
fined in Table 2.. The Write Status Register
(WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD)
bit in accordance with the Write Protect (W) signal.
The Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11..
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b1 and b0 of the Status Reg-
ister. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en High, the self-timed Write Status Register cycle
Figure 11. Write Status Register (WRSR) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
15/41
M25P80
Table 6. Protection Modes
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Status Register
Mode
1
1
Protected Area
Unprotected Area
1
0
0
0
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Software
Protected
(SPM)
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
1
1
Status Register is
Hardware Hardware write protected
Protected The values in the SRWD,
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
0
1
(HPM)
BP2, BP1 and BP0 bits
cannot be changed
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2..
The protection features of the device are summa-
rized in Table 6..
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register,
are also hardware protected against data
modification.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
–
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
–
–
If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0)
bits of the Status Register, can be used.
–
If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
16/41
M25P80
Read Data Bytes (READ)
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 12..
The first byte addressed can be at any location.
The address is automatically incremented to the
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI03748D
Note: Address bits A23 to A20 are Don’t Care.
17/41
M25P80
Read Data Bytes at Higher Speed
(FAST_READ)
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 13..
The first byte addressed can be at any location.
The address is automatically incremented to the
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
3
2
1
0
D
Q
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI04006
Note: Address bits A23 to A20 are Don’t Care.
18/41
M25P80
Page Program (PP)
ing any effects on the other bytes of the same
page.
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end
of the current page are programmed from the start
address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero).
Chip Select (S) must be driven Low for the entire
duration of the sequence.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Instruction Times (Device Grade 6) and In-
struction Times (Device Grade 3)).
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is tPP
)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 3. and Table 2.) is not execut-
ed.
The instruction sequence is shown in Figure 14..
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 256 Data
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
19/41
M25P80
Figure 14. Page Program (PP) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04082B
Note: Address bits A23 to A20 are Don’t Care.
20/41
M25P80
Sector Erase (SE)
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
ration is tSE) is initiated. While the Sector Erase cy-
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 3. and Table 2.) is not execut-
ed.
The instruction sequence is shown in Figure 15..
Figure 15. Sector Erase (SE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751D
Note: Address bits A23 to A20 are Don’t Care.
21/41
M25P80
Bulk Erase (BE)
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
the self-timed Bulk Erase cycle (whose duration is
tBE) is initiated. While the Bulk Erase cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
pleted. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Bulk Erase (BE) instruction is entered by driv-
ing Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
The Bulk Erase (BE) instruction is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0. The
Bulk Erase (BE) instruction is ignored if one, or
more, sectors are protected.
The instruction sequence is shown in Figure 16..
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
Figure 16. Bulk Erase (BE) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Instruction
AI03752D
22/41
M25P80
Deep Power-down (DP)
ture of the device to be output on Serial Data Out-
put (Q).
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
The instruction sequence is shown in Figure 17..
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
to reduce the standby current (from ICC1 to ICC2
as specified in Table 12.).
,
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instruction also allows the Electronic Signa-
Figure 17. Deep Power-down (DP) Instruction Sequence
S
tDP
0
1
2
3
4
5
6
7
C
D
Instruction
Stand-by Mode
Deep Power-down Mode
AI03753D
23/41
M25P80
Release from Deep Power-down and Read
Electronic Signature (RES)
Data Input (D) during the rising edge of Serial
Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data
Output (Q), each bit being shifted out during the
falling edge of Serial Clock (C).
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Pow-
er-down mode.
The instruction can also be used to read, on Serial
Data Output (Q), the 8-bit Electronic Signature,
whose value for the M25P80 is 13h.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the 8-
bit Electronic Signature of the device, and can be
applied even if the Deep Power-down mode has
not been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
The instruction sequence is shown in Figure 18..
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminat-
ed by driving Chip Select (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is
put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the
transition to the Stand-by Power mode is immedi-
ate. If the device was previously in the Deep Pow-
er-down mode, though, the transition to the Stand-
by Power mode is delayed by tRES2, and Chip Se-
lect (S) must remain High for at least tRES2(max),
as specified in Table 17.. Once in the Stand-by
Power mode, the device waits to be selected, so
that it can receive, decode and execute instruc-
tions.
The device is first selected by driving Chip Select
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
C
tRES2
Instruction
3 Dummy Bytes
23 22 21
MSB
3
2
1
0
D
Q
Electronic Signature Out
High Impedance
7
6
5
4
3
2
0
1
MSB
Deep Power-down Mode
Stand-by Mode
AI04047C
Note: The value of the 8-bit Electronic Signature, for the M25P80, is 13h.
24/41
M25P80
Figure 19. Release from Deep Power-down (RES) Instruction Sequence
S
tRES1
0
1
2
3
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode
Stand-by Mode
AI04078B
Driving Chip Select (S) High after the 8-bit instruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmitted for the first time (as shown in Fig-
ure 19.), still insures that the device is put into
Stand-by Power mode. If the device was not pre-
viously in the Deep Power-down mode, the transi-
tion to the Stand-by Power mode is immediate. If
the device was previously in the Deep Power-
down mode, though, the transition to the Stand-by
Power mode is delayed by tRES1, and Chip Select
(S) must remain High for at least tRES1(max), as
specified in Table 17.. Once in the Stand-by Power
mode, the device waits to be selected, so that it
can receive, decode and execute instructions.
25/41
M25P80
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on VCC) until VCC reaches the
correct value:
Program or Erase instructions should be sent until
the later of:
–
–
t
PUW after VCC passed the VWI threshold
tVSL afterVCC passed the VCC(min) level
–
VCC(min) at Power-up, and then for a further
delay of tVSL
These values are specified in Table 7..
If the delay, tVSL, has elapsed, after VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not yet
fully elapsed.
–
VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to insure safe and proper Power-up
and Power-down.
At Power-up, the device is in the following state:
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while VCC is less than the POR
threshold value, VWI – all operations are disabled,
and the device does not respond to any instruc-
tion.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of tPUW has
elapsed after the moment that VCC rises above the
VWI threshold. However, the correct operation of
the device is not guaranteed if, by this time, VCC is
still below VCC(min). No Write Status Register,
–
The device is in the Standby mode (not the
Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
–
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC feed. Each device
in a system should have the VCC rail decoupled by
a suitable capacitor close to the package pins.
(Generally, this capacitor is of the order of 0.1µF).
At Power-down, when VCC drops from the operat-
ing voltage, to below the POR threshold value,
V
does not respond to any instruction. (The designer
needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in
progress, some data corruption can result.)
WI, all operations are disabled and the device
26/41
M25P80
Figure 20. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
Table 7. Power-Up Timing and VWI Threshold
Symbol
Parameter
Min.
10
1
Max.
Unit
µs
1
V
(min) to S low
tVSL
CC
1
Time delay to Write instruction
Write Inhibit Voltage
10
2
ms
V
tPUW
1
1
VWI
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status
Register bits are 0).
27/41
M25P80
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min.
–65
Max.
150
4.0
Unit
°C
V
T
Storage Temperature
STG
VIO
Input and Output Voltage (with respect to Ground)
Supply Voltage
–0.6
V
CC
–0.6
4.0
V
2
VESD
–2000
2000
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
28/41
M25P80
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions
Symbol
Parameter
Min.
2.7
Max.
3.6
Unit
V
Supply Voltage
V
CC
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
TA
°C
125
Table 10. Data Retention and Endurance
Parameter
Condition
Min.
Max.
100 000
10 000
20
Unit
Device Grade 6
cycles per
sector
Erase/Program Cycles
1
Device Grade 3
Device Grade 6
Data Retention
years
1
20
Device Grade 3 (at 85°C)
Note: 1. This is preliminary data
Table 11. Capacitance
Symbol
COUT
Parameter
Output Capacitance (Q)
Input Capacitance (other pins)
Test Condition
= 0V
Min.
Max.
Unit
pF
V
8
6
OUT
CIN
V
IN
= 0V
pF
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 20MHz.
A
29/41
M25P80
Table 12. DC Characteristics (Device Grade 6)
Test Condition
(in addition to those in Table 9.)
Symbol
Parameter
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
50
µA
µA
µA
µA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Deep Power-down Current
10
C = 0.1VCC / 0.9.VCC at 40MHz,
Q = open
8
4
mA
mA
ICC3
Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open
ICC4
ICC5
ICC6
ICC7
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
S = VCC
S = VCC
S = VCC
S = VCC
15
15
mA
mA
mA
mA
V
15
15
–0.5
0.3VCC
VCC+0.4
0.4
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
I
OL = 1.6mA
V
Output High Voltage
I
OH = –100µA
VCC–0.2
V
Table 13. DC Characteristics (Device Grade 3)
Test Condition
(in addition to those in Table 9.)
1
1
Symbol
Parameter
Unit
Min.
Max.
ILI
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
100
50
µA
µA
µA
µA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Deep Power-down Current
C = 0.1VCC / 0.9.VCC at 40MHz,
Q = open
8
4
mA
mA
ICC3
Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open
ICC4
ICC5
ICC6
ICC7
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
S = VCC
S = VCC
S = VCC
S = VCC
15
15
mA
mA
mA
mA
V
15
15
– 0.5
0.3VCC
VCC+0.4
0.4
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
IOL = 1.6mA
V
Output High Voltage
I
OH = –100µA
VCC–0.2
V
Note: 1. This is preliminary data
30/41
M25P80
Table 14. Instruction Times (Device Grade 6)
Test conditions specified in Table 9. and Table 16.
Symbol
Alt.
Parameter
Min.
Typ.
5
Max.
Unit
t
W
Write Status Register Cycle Time
Page Program Cycle Time (256 Bytes)
15
ms
1.4
(1)
5
ms
t
PP
0.4+
n*1/256
Page Program Cycle Time (n Bytes)
t
Sector Erase Cycle Time
Bulk Erase Cycle Time
1
3
s
s
SE
t
BE
10
20
1. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one se-
quence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
Table 15. Instruction Times (Device Grade 3)
Test conditions specified in Table 9. and Table 16.
1,2
2
Symbol
Alt.
Parameter
Min.
Unit
Typ.
Max.
t
W
Write Status Register Cycle Time
Page Program Cycle Time (256 Bytes)
8
15
ms
1.5
3
0.4+
n*1.1/
256
5
ms
t
PP
Page Program Cycle Time (n Bytes)
t
Sector Erase Cycle Time
Bulk Erase Cycle Time
1
3
s
s
SE
t
BE
10
20
Note: 1. At 85°C
2. This is preliminary data
3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence
including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
Table 16. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
5
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input Timing Reference Voltages
Output Timing Reference Voltages
V
CC
V
/ 2
V
CC
Note: Output Hi-Z is defined as the point where data out is no longer driven.
31/41
M25P80
Figure 21. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
CC
0.3V
CC
0.5V
0.2V
CC
AI07455
Table 17. AC Characteristics (25MHz Operation, Device Grade 6 or 3)
Test conditions specified in Table 9. and Table 16.
5
5
Symbol
Alt.
Parameter
Typ.
Unit
Min.
Max.
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR
f
C
f
C
D.C.
25
MHz
f
Clock Frequency for READ instructions
Clock High Time
D.C.
18
20
MHz
ns
R
1
t
t
CLH
CH
1
t
Clock Low Time
18
ns
t
CL
CLL
2
2
3
0.1
V/ns
t
t
Clock Rise Time (peak to peak)
CLCH
3
0.1
10
10
5
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Fall Time (peak to peak)
CHCL
t
t
t
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
SLCH
CHSL
CSS
t
t
DVCH
CHDX
CHSH
SHCH
DSU
t
t
t
t
DH
Data In Hold Time
5
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
10
10
100
t
t
CSH
SHSL
2
t
Output Disable Time
15
15
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
ns
ns
ns
ns
ns
ns
ns
CLQV
CLQX
HLCH
t
t
t
t
HO
0
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
10
10
10
10
CHHH
HHCH
t
t
CHHL
2
t
LZ
15
t
HHQX
32/41
M25P80
Test conditions specified in Table 9. and Table 16.
5
5
Symbol
Alt.
Parameter
HOLD to Output High-Z
Typ.
Unit
ns
Min.
Max.
2
t
HZ
20
t
HLQZ
4
4
Write Protect Setup Time
20
ns
t
t
WHSL
Write Protect Hold Time
100
ns
SHWL
2
S High to Deep Power-down Mode
3
3
µs
t
DP
S High to Standby Mode without Electronic
Signature Read
2
2
µs
µs
t
RES1
RES2
S High to Standby Mode with Electronic
Signature Read
1.8
t
Note: 1. t + t must be greater than or equal to 1/ f
C
CH
CL
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. For device grade 3, this is Preliminary Data
Table 18. AC Characteristics (40MHz Operation, Device Grade 6)
5
40MHz available for products marked since week 20 of 2004, only
Test conditions specified in Table 9. and Table 16.
Symbol
Alt.
Parameter
Typ.
Unit
Min.
Max.
40
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR
f
C
f
C
D.C.
MHz
f
Clock Frequency for READ instructions
Clock High Time
D.C.
11
20
MHz
ns
R
1
t
t
CLH
CH
1
t
Clock Low Time
11
ns
t
CL
CLL
2
2
3
0.1
V/ns
t
t
Clock Rise Time (peak to peak)
CLCH
3
0.1
5
V/ns
ns
Clock Fall Time (peak to peak)
CHCL
t
t
t
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
SLCH
CHSL
CSS
t
t
5
ns
2
ns
DVCH
CHDX
CHSH
SHCH
DSU
t
t
t
t
DH
Data In Hold Time
5
ns
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
5
ns
5
ns
t
t
CSH
100
ns
SHSL
2
t
Output Disable Time
9
9
ns
ns
ns
ns
ns
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
CLQV
CLQX
HLCH
t
t
t
t
HO
0
5
5
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
CHHH
33/41
M25P80
5
40MHz available for products marked since week 20 of 2004, only
Test conditions specified in Table 9. and Table 16.
Symbol
Alt.
Parameter
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
Typ.
Unit
ns
Min.
Max.
t
5
5
HHCH
t
ns
CHHL
2
t
HOLD to Output Low-Z
9
9
ns
ns
ns
ns
µs
t
LZ
HHQX
2
t
HZ
HOLD to Output High-Z
t
HLQZ
4
Write Protect Setup Time
Write Protect Hold Time
S High to Deep Power-down Mode
20
t
t
WHSL
4
100
SHWL
2
3
3
t
DP
S High to Standby Mode without Electronic
Signature Read
2
2
µs
µs
t
RES1
RES2
S High to Standby Mode with Electronic
Signature Read
1.8
t
Note: 1. t + t must be greater than or equal to 1/ f
C
CH
CL
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Details of how to find the date of marking are given in Application Note, AN1995.
Figure 22. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
34/41
M25P80
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439
Figure 24. Hold Timing
S
tHLCH
tCHHL
tHLQZ
tHHCH
C
tCHHH
tHHQX
Q
D
HOLD
AI02032
35/41
M25P80
Figure 25. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449e
36/41
M25P80
PACKAGE MECHANICAL
Figure 26. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm,
Package Outline
D
D1
E
E1
E2
e
b
D2
θ
A
A2
L
A1 A3
VFQFPN-01
Note: Drawing is not to scale.
Table 19. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm,
Package Mechanical Data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
1.00
0.05
Typ.
Max.
A
A1
A2
A3
b
0.85
0.0335
0.0394
0.0020
0.00
0.35
3.20
0.0000
0.0138
0.1260
0.65
0.20
0.40
6.00
5.75
3.40
5.00
4.75
4.00
1.27
0.60
0.0256
0.0079
0.0157
0.2362
0.2264
0.1339
0.1969
0.1870
0.1575
0.0500
0.0236
0.48
3.60
4.20
0.0189
0.1417
0.1654
D
D1
D2
E
E1
E2
e
3.80
0.50
0.1496
0.0197
L
0.75
12°
0.0295
12°
θ
37/41
M25P80
Figure 27. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 20. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
millimetres
Min.
inches
Min.
Symbol
Typ.
Max.
2.03
0.25
1.78
0.45
–
Typ.
Max.
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
1.27
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
38/41
M25P80
PART NUMBERING
Table 21. Ordering Information Scheme
Example:
M25P80
–
V MW
6
T
P
Device Type
M25P = Serial Flash Memory for Code Storage
Device Function
80 = 8 Mbit (1M x 8)
Operating Voltage
V = V = 2.7 to 3.6V
CC
Package
(3)
MW = SO8 (200 mil width)
MP = VDFPN8 (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
(2)
(1)
3
= Device tested with High Reliability Certified Flow
.
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHs compliant)
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Device grade 3 available in SO8 Lead-free and RoHS compliant package
3. The SO8 wide (200mil width) package is not a preferred option. Please ask your nearest ST sales office for availability.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
The category of second Level Interconnect is
marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions
are also marked on the inner box label.
39/41
M25P80
REVISION HISTORY
Table 22. Document Revision History
Date
Rev.
Description of Revision
Document released as a Product Preview data sheet
24-Apr-2002
1.0 Clarification of descriptions of entering Stand-by Power mode from Deep Power-down mode,
and of terminating an instruction sequence or data-out sequence.
VFQFPN8 package (MLP8) added. Order code (MW) corrected on page 1 for SO8 package.
Document promoted to Preliminary Data.
27-Sep-2002
13-Dec-2002
1.1
Typical Page Program time improved. Write Protect setup and hold times specified, for
1.2 applications that switch Write Protect to exit the Hardware Protection mode immediately before
a WRSR, and to enter the Hardware Protection mode again immediately after.
Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.
2.0 40MHz AC Characteristics table included as well as 25MHz. Change of naming for VDFPN8
package. Document promoted to full datasheet
24-Oct-2003
24-Nov-2003
21-Apr-2004
2.1 Improvement to description of reading the 8-bit electronic signature.
SO16 package added. SO8W package removed. Soldering temperature information clarified
3.0
for RoHS compliant devices. Device Grade clarified
07-May-2004
18-May-2004
4.0 Automotive range added
5.0 SO8W package re-instated, but under limited availability
Data-retention measurement temperature corrected. Details of how to find the date of marking
added.
05-Aug-2004
01-Aug-2005
6.0
Updated Page Program (PP) instructions in Page Programming, Page Program (PP),
Instruction Times (Device Grade 6) and Instruction Times (Device Grade 3).
7.0
SO16 package removed. All packages are ECOPACK®. MLP8 package renamed as
VFQFPN8. Plating technology clarified in Table 21., Ordering Information Scheme. VFQFPN
20-Oct-2005
8.0
silhouette modified (see Figure 1., Packages). t
Timing.
timing modified in Figure 25., Output
SHQZ
40/41
M25P80
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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相关型号：
M25PE10
1 and 2 Mbit,Low Voltage,Page-Erasable Serial Flash Memories with Byte-Alterability,33 MHz SPI Bus,Standard Pin-out
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1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
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M25PE10-VMN6P
1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout
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M25PE10-VMN6TG
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M25PE10-VMN6TP
1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out
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M25PE10-VMN6TP
1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
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M25PE10-VMP6G
1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
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M25PE10-VMP6G
1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout
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