M27256-F1 [STMICROELECTRONICS]
NMOS 256K 32K x 8 UV EPROM; NMOS 256K 32K ×8 UV EPROM
| 型号： | M27256-F1 |
| 厂家： | 
ST |
| 描述： | NMOS 256K 32K x 8 UV EPROM |
| 文件： | 总10页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27256
NMOS 256 Kbit (32Kb x 8) UV EPROM
NOT FOR NEW DESIGN
■ FAST ACCESS TIME: 170ns
■ EXTENDED TEMPERATURE RANGE
■ SINGLE 5V SUPPLY VOLTAGE
■ LOW STANDBY CURRENT: 40mA max
■ TTL COMPATIBLE DURING READ and
PROGRAM
28
■ FAST PROGRAMMING ALGORITHM
■ ELECTRONIC SIGNATURE
1
■ PROGRAMMING VOLTAGE: 12V
FDIP28W (F)
DESCRIPTION
The M27256 is a 262,144 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 32.768 words by 8 bits.
The M27256 is housed in a 28 pin Window Ceram-
ic Frit-Seal Dual-in-Line package. The transparent
lid allows the user to expose the chip to ultraviolet
light to erase the bit pattern. A new pattern can
then be written to the device by following the pro-
gramming procedure.
Figure 1. Logic Diagram
V
V
PP
CC
15
8
A0-A14
Q0-Q7
E
M27256
G
V
SS
AI00767B
November 2000
1/10
This is information on a product still in production but not recommended for new designs.
M27256
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
grade 1
grade 6
0 to 70
–40 to 85
°C
TBIAS
Temperature Under Bias
grade 1
grade 6
–10 to 80
–50 to 95
°C
TSTG
VIO
Storage Temperature
Input or Output Voltages
Supply Voltage
–65 to 125
–0.6 to 6.25
–0.6 to 6.25
–0.6 to 13.5
–0.6 to 14
°C
V
VCC
VA9
VPP
V
VA9 Voltage
V
Program Supply
V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Read Mode
Figure 2. DIP Pin Connections
The M27256 has two control functions, both of
which must be logically satisfied in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
V
1
2
3
4
5
6
7
8
9
28
V
CC
PP
A12
A7
A6
A5
A4
A3
A2
A1
27 A14
26 A13
25 A8
24 A9
23 A11
addresses are stable, address access time (tAVQV
)
is equal to the delay from E to output (tELQV). Data
is available at the outputs after the falling edge of
G, assuming that E has been low and the ad-
22
G
M27256
21 A10
20
dresses have been stable for at least tAVQV-tGLQV
.
E
Standby Mode
A0 10
Q0 11
Q1 12
Q2 13
19 Q7
18 Q6
17 Q5
16 Q4
15 Q3
The M27256 has a standby mode which reduces
the maximum active power current from 100mA to
40mA. The M27256 is placed in the standby mode
by applying a TTL high signal to the E input. When
in the standby mode, the outputs are in a high
impedance state, independent of the G input.
V
14
SS
AI00768
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
DEVICE OPERATION
The eight modes of operations of the M27256 are
listed in the Operating Modes Table. A single 5V
power supply is required in the read mode. All
inputs are TTL levels except for VPP and 12V on A9
for Electronic Signature.
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
2/10
M27256
DEVICE OPERATION (cont’d)
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus.
Programmain
When delivered, (and after each erasure for UV
EPROM), all bits of the M27256 are in the “1" state.
Data is introduced by selectively programming ”0s"
into the desired bit locations. Although only “0s” will
be programmed, both “1s” and “0s” can be present
in the data word. The only way to change a “0" to
a ”1" is by ultraviolet light erasure. The M27256 is
in the programming mode when VPP input is at
12.5V and E is at TTL low. The data to be pro-
grammed is applied 8 bits in parallel to the data
outputpins. The levels required fortheaddress and
data inputs are TTL.
This ensures that all deselected memory devices
are in their low power standby mode and that the
output pins are only active when data is required
from a particular memory device.
System Considerations
The power switching characteristics of fast
EPROMs require carefuldecouplingofthedevices.
The supply current, ICC, has three segments that
are of interest to the system designer : the standby
current level, the active current level, and transient
current peaks that are produced by the falling and
rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and
inductive loading of the device at the output. The
associated transient voltage peaks can be sup-
pressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitors should be used
between VCC and VSS for every eight devices. The
Fast Programming Algorithm
Fast Programming Algorithm rapidly programs
M27256 EPROMs using an efficient and reliable
method suited to the production programming en-
vironment. Programming reliability is also ensured
as the incremental program margin of each byte is
continually monitored to determine when it has
been successfully programmed. A flowchart of the
M27256 Fast Programming Algorithm is shown on
the Flowchart. The Fast Programming Algorithm
utilizes two different pulse types : initial and over-
program. The duration of the initial E pulse(s) is
1ms, which will then be followed by a longer over-
program pulse of length 3ms by n (n is equal to the
number of the initial one millisecond pulses applied
Table 3. Operating Modes
Mode
E
VIL
G
A9
X
VPP
VCC
VCC
VPP
VPP
VPP
VPP
VCC
VCC
Q0 - Q7
Data Out
Hi-Z
Read
VIL
VIH
VIH
VIL
VIL
VIH
X
Output Disable
Program
VIL
X
VIL Pulse
VIH
X
Data In
Data Out
Data Out
Hi-Z
Verify
X
Optional Verify
Program Inhibit
Standby
VIL
X
VIH
X
VIH
X
Hi-Z
Electronic Signature
VIL
VIL
VID
Codes
Note: X = VIH or VIL, VID = 12V ± 0.5%.
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
VIL
VIH
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
0
Hex Data
20h
0
0
0
0
0
1
0
0
04h
3/10
M27256
Figure 4. AC Testing Load Circuit
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤
20ns
1.3V
Input Pulse Voltages
0.45V to 2.4V
0.8V to 2.0V
Input and Output Timing Ref. Voltages
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
DEVICE
UNDER
TEST
OUT
2.4V
2.0V
C
= 100pF
L
0.8V
0.45V
AI00827
C
includes JIG capacitance
L
AI00828
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
A0-A14
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q7
DATA OUT
AI00758
4/10
M27256
Table 6. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0 ≤ VIN ≤ VCC
VOUT = VCC
E = VIL, G = VIL
E = VIH
Min
Max
±10
±10
100
40
Unit
µA
µA
mA
mA
mA
V
ILO
ICC
ICC1
IPP
Supply Current (Standby)
Program Current
VPP = VCC
5
VIL
Input Low Voltage
–0.1
2
0.8
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
VCC + 1
0.45
V
VOL
VOH
IOL = 2.1mA
V
IOH = –400µA
2.4
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
Table 7A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M27256
-2, -20
Test
Condition
Symbol Alt
Parameter
Unit
-1
blank, -25
Min
Max
Min
Max
Min
Max
Address Valid to
Output Valid
E = VIL,
G = VIL
tAVQV
tELQV
tGLQV
tACC
tCE
tOE
tDF
170
200
200
75
250
ns
ns
ns
ns
ns
ns
Chip Enable Low
to Output Valid
G = VIL
E = VIL
G = VIL
E = VIL
170
70
250
100
60
Output Enable
Low to Output Valid
Chip Enable High
to Output Hi-Z
(2)
tEHQZ
0
0
0
35
0
0
0
55
0
0
0
Output Enable
High to Output Hi-Z
(2)
tGHQZ
tAXQX
tDF
35
55
60
Address Transition
to Output Transition
E = VIL,
G = VIL
tOH
Table 7B. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M27256
Test
Condition
Symbol Alt
Parameter
Unit
-3
-4
Min
Max
Min
Max
Address Valid to
Output Valid
E = VIL,
G = VIL
tAVQV
tELQV
tGLQV
tACC
tCE
tOE
tDF
tDF
tOH
300
450
450
150
130
130
ns
ns
ns
ns
ns
ns
Chip Enable Low
to Output Valid
G = VIL
E = VIL,
G = VIL
E = VIL
300
Output Enable
Low to Output Valid
120
Chip Enable High
to Output Hi-Z
(2)
tEHQZ
0
0
105
105
0
0
0
Output Enable
High to Output Hi-Z
(2)
tGHQZ
tAXQX
Address Transition
to Output Transition
E = VIL,
G = VIL
0
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
2. Sampled only, not 100% tested.
5/10
M27256
Table 8. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6V ± 0.25V; VPP = 12.5V ± 0.3V)
Symbol
ILI
Parameter
Input Leakage Current
Supply Current
Test Condition
Min
Max
±10
Unit
µA
mA
mA
V
VIL ≤ VIN ≤ VIH
ICC
100
IPP
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
A9 Voltage
E = VIL
50
VIL
–0.1
2
0.8
VIH
VCC + 1
0.45
V
VOL
VOH
VID
IOL = 2.1mA
V
IOH = –400µA
2.4
V
11.5
12.5
V
Note. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
Table 9. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6V ± 0.25V; VPP = 12.5V ± 0.3V)
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
Address Valid to Chip Enable
Low
tAVEL
tAS
2
µs
tQVEL
tVPHEL
tVCHEL
tDS
tVPS
tVCS
Input Valid to Chip Enable Low
VPP High to Chip Enable Low
VCC High to Chip Enable Low
2
2
2
µs
µs
µs
Chip Enable Program Pulse
Width (Initial)
tELEH
tELEH
tEHQX
tQXGL
tGLQV
tPW
tOPW
tDH
Note 2
Note 3
0.95
2.85
2
1.05
ms
ms
µs
µs
ns
Chip Enable Program Pulse
Width (Overprogram)
78.75
Chip Enable High to Input
Transition
Input Transition to Output
Enable Low
tOES
tOE
tDFP
tAH
2
Output Enable Low to
Output Valid
150
130
Output Enable Low to
Output Hi-Z
(4)
tGHQZ
0
0
ns
Output Enable High to
Address Transition
tGHAX
n s
Notes. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
2. The Initial Program Pulse width tolerance is 1 ms ± 5%.
3. The length of the Over-program Pulse varies from 2.85 ms to 78.95 ms, depending on the multiplication value of the iteration counter.
4. Sampled only, not 100% tested.
6/10
M27256
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A14
tAVEL
Q0-Q7
DATA IN
tQVEL
DATA OUT
tEHQX
V
PP
tVPHEL
tVCHEL
tGLQV
tGHQZ
tGHAX
V
CC
E
tELEH
tQXGL
G
PROGRAM
VERIFY
AI00759
Figure 7. Programming Flowchart
DEVICE OPERATION (cont’d)
to a particular M27256 location), before a correct
verify occurs. Up to 25 one-millisecond pulses per
byteareprovidedforbefore the overprogrampulse
is applied. The entire sequence of program pulses
and byte verifications is performed at VCC = 6V and
V
= 6V, V
= 12.5V
PP
CC
V
PP = 12.5V.
n = 1
When the Fast Programming cycle has been com-
pleted, all bytes should be compared to the original
data with VCC = 5V and VPP = 5V.
E = 1ms Pulse
Program Inhibit
NO
Programming of multiple M27256s in parallel with
different data is also easily accomplished. Except
for E, all like inputs (including G) of the parallel
M27256 may be common. A TTL low pulse applied
to a M27256’s E input, with VPP = 12.5V, will
program that M27256. A high level E input inhibits
the other M27256s from being programmed.
NO
++n
> 25
VERIFY
YES
E = 3ms Pulse by n
++ Addr
YES
FAIL
Program Verify
Last
NO
Addr
A verify should be performed on the programmed
bits to determine that they were correctly pro-
grammed. The verify is accomplished withE = VIH,
G = VIL and VPP = 12.5V.
YES
CHECK ALL BYTES
= 5V, V = 5V
V
CC
PP
Optional Verify
AI00774B
Theoptionalverify maybe performedinsteadof the
verify mode. It is performed with G = VIL, E = VIL
(as opposed t the standard verify which has E =
7/10
M27256
DEVICE OPERATION (cont’d)
croelectronics M27256, these two identifier bytes are
given below.
VIH), and VPP = 12.5V. The outputs will be in a Hi-z
state accordingto thesignal presentedtoG. There-
fore, all devices with VPP = 12.5V and G = VIL will
present data on the bus independent of theE state.
When parallel programming several devices which
share the common bus, VPP should be lowered to
VCC (6V) and the normal read mode used to exe-
cute a program verify.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristic of the M27256 is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000 Årange. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M27256 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M27256 is
to be exposed to these types of lighting conditions
for extended periods of time, it is suggested that
opaque lables be put over the M27256 window to
prevent unintentional erasure. The recommended
erasure procedure for the M27256 is exposure to
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of15W-sec/cm2. Theerasuretimewiththisdosage
is approximately 15 to 20 minutes using an ultra-
violet lamp with 12000 µW/cm2 power rating. The
M27256 should be placed within 2.5cm (1 inch) of
the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be re-
moved before erasure.
Electronic Signature
The Electronic Signature mode allows the reading
out of a binary code from an EPROM that will
identify its manufacturer and type. This mode is
intended for use by programmingequipmentforthe
purpose of automatically matching the device to be
programmed with its corresponding programming
algorithm. This modeisfunctionalin the25°C± 5°C
ambient temperature range that is required when
programming the M27256. To activate this mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27256. Two
identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from V
IL
to VIH. All other address lines must be held at VIL
during Electronic Signature mode. Byte 0 (A0 = V )
IL
represents the manufacturer code and byte 1 (A0
= VIH) the device identifier code. For the STMi-
ORDERING INFORMATION SCHEME
Example:
M27256
-1
F
1
Speed and VCC Tolerance
Package
FDIP28W
Temperature Range
-1
170 ns, 5V ±5%
200 ns, 5V ±5%
250 ns, 5V ±5%
300 ns, 5V ±5%
400 ns, 5V ±5%
200 ns, 5V ±10%
250 ns, 5V ±10%
F
1
6
0 to 70 °C
-2
blank
-3
–40 to 85 °C
-4
-20
-25
For a list of available options (Speed, VCC Tolerance, Package, etc) refer to the current Memory Shortform
catalogue.
For further information on any aspect of this device, please contact STMicroelectronics Sales Office nearest
to you.
8/10
M27256
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
mm
Min
inches
Min
Symb
Typ
Max
5.71
1.78
5.08
0.55
1.42
0.31
38.10
15.80
13.36
–
Typ
Max
0.225
0.070
0.200
0.022
0.056
0.012
1.500
0.622
0.526
–
A
A1
A2
B
0.50
3.90
0.40
1.17
0.22
0.020
0.154
0.016
0.046
0.009
B1
C
D
E
15.40
13.05
–
0.606
0.514
–
E1
e1
e3
eA
L
2.54
0.100
1.300
33.02
–
–
–
–
16.17
3.18
1.52
–
18.32
4.10
2.49
–
0.637
0.125
0.060
–
0.721
0.161
0.098
–
S
7.11
0.280
α
4°
15°
4°
15°
N
2
8
28
A2
A
A1
e1
L
B1
B
α
C
eA
e3
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale
9/10
M27256
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
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10/10
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