M27C1001-90XN1X [STMICROELECTRONICS]
1 Mbit 128Kb x8 UV EPROM and OTP EPROM; 1兆位128KB X8 UV EPROM和OTP EPROM
| 型号： | M27C1001-90XN1X |
| 厂家： | 
ST |
| 描述： | 1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
| 文件： | 总17页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27C1001
1 Mbit (128Kb x8) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 35ns
32
32
■ LOW POWER CONSUMPTION:
– Active Current 30mA at 5Mhz
– Standby Current 100µA
1
1
FDIP32W (F)
PDIP32 (B)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 05h
LCCC32W (L)
DESCRIPTION
The M27C1001 is a 1 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and
is organized as 131,072 words of 8 bits.
PLCC32 (C)
TSOP32 (N)
8 x 20 mm
The FDIP32W (window ceramic frit-seal package)
and the LCCC32W (leadless chip carrier package)
have a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
Figure 1. Logic Diagram
For applications where the content is programmed
only one time and erasure is not required, the
M27C1001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
V
V
PP
CC
17
8
A0-A16
Q0-Q7
P
E
M27C1001
G
V
SS
AI00710B
June 2002
1/17
M27C1001
Figure 2A. DIP Connections
Figure 2B. LCC Connections
V
1
2
3
4
5
6
7
8
9
32
31
V
P
PP
CC
A16
A15
A12
A7
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
1 32
A7
A14
A13
A8
A6
A5
A4
A6
A5
A9
A4
M27C1001
A3
A2
A1
A0
Q0
9
M27C1001
25 A11
G
A3
24
23 A10
22
G
A2 10
A1 11
A0 12
Q0 13
Q1 14
Q2 15
A10
E
E
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
Q7
17
V
16
SS
AI00712
AI00711
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A16
Address Inputs
Q0-Q7
Data Outputs
Chip Enable
Output Enable
Program
A11
A9
1
32
G
E
G
P
A10
E
A8
A13
A14
NC
P
Q7
Q6
Q5
Q4
Q3
V
Program Supply
Supply Voltage
Ground
PP
V
8
9
M27C1001 25
V
CC
CC
(Normal)
V
24
V
SS
PP
V
SS
A16
Q2
Q1
Q0
A0
A1
A2
A3
A15
A12
A7
NC
Not Connected Internally
A6
A5
A4
16
17
AI01151B
2/17
M27C1001
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
CC
–2 to 7
V
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
E
G
P
A9
X
Q7-Q0
Data Out
Hi-Z
PP
V
V
V
V
or V
or V
Read
X
IL
IL
IL
IL
IL
IH
IH
CC
SS
SS
V
V
V
V
V
V
Output Disable
Program
X
X
CC
V
IL
Pulse
V
X
Data In
Data Out
Hi-Z
PP
PP
PP
V
IL
V
IH
V
Verify
X
V
Program Inhibit
Standby
X
X
X
IH
IH
V
V
or V
CC SS
X
X
X
Hi-Z
V
V
IL
V
IH
V
ID
V
CC
Electronic Signature
Codes
IL
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
Hex Data
20h
V
IL
0
1
V
0
0
0
0
0
1
0
05h
IH
3/17
M27C1001
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
IN
C
OUT
V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
The operating modes of the M27C1001 are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
(t
(t
of t
) is equal to the delay from E to output
). Data is available at the output after a delay
AVQV
ELQV
from the falling edge of G, assuming that
GLQV
levels except for V and 12V on A9 for Electronic
PP
E has been low and the addresses have been sta-
Signature.
Read Mode
ble for at least t
-t
.
AVQV GLQV
Standby Mode
The M27C1001 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
The M27C1001 has a standby mode which reduc-
es the supply current from 30mA to 100µA. The
M27C1001 is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
4/17
M27C1001
(1)
Table 7. Read Mode DC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; V = 5V ± 5% or 5V ± 10%; V = V )
CC
PP
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
Unit
µA
I
±10
±10
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
µA
E = V , G = V ,
IL
IL
I
Supply Current
30
mA
CC
I
= 0mA, f = 5MHz
OUT
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
E > V
– 0.2V
CC
100
10
CC2
I
V
= V
PP CC
PP
V
IL
Input Low Voltage
–0.3
2
0.8
(2)
V
+ 1
Input High Voltage
V
V
V
V
V
CC
IH
V
I
= 2.1mA
= –400µA
= –100µA
Output Low Voltage
0.4
OL
OL
I
Output High Voltage TTL
Output High Voltage CMOS
2.4
OH
OH
V
OH
I
V
– 0.7V
CC
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; V = 5V ± 5% or 5V ± 10%; V = V )
CC
PP
CC
M27C1001
Unit
(3)
Symbol
Alt
Parameter
Test Condition
-45
-60
-70
-35
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
t
t
E = V , G = V
35
35
25
25
25
45
45
25
25
25
60
60
30
30
30
70
70
35
30
30
ns
ns
ns
ns
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
IL
ELQV
CE
Output Enable Low
to Output Valid
t
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
DF
G = V
0
0
0
0
0
0
0
0
0
0
0
0
t
IL
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
DF
E = V
t
IL
GHQZ
Address Transition
to Output Transition
t
t
E = V , G = V
IL IL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
5/17
M27C1001
(1)
Table 8B. Read Mode AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; V = 5V ± 5% or 5V ± 10%; V = V )
CC
PP
CC
M27C1001
-12/-15/
-20/-25
Symbol
Alt
Parameter
Test Condition
-80
-90
-10
Unit
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
t
t
E = V , G = V
80
80
40
30
30
90
90
45
30
30
100
100
50
120
120
60
ns
ns
ns
ns
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
ELQV
CE
IL
IL
IL
IL
Output Enable Low
to Output Valid
t
t
E = V
G = V
E = V
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
DF
0
0
0
0
0
0
0
0
0
30
0
0
0
40
t
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
DF
30
40
t
GHQZ
Address Transition
to Output Transition
t
t
E = V , G = V
IL IL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A16
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q7
AI00713B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
devices. The supply current, I , has three seg-
CC
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/17
M27C1001
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
Input Leakage Current
Supply Current
V
≤ V ≤ V
LI
IL
IN
IH
I
CC
I
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
PP
IL
V
IL
–0.3
2
0.8
V
IH
V
+ 0.5
V
CC
V
OL
I
= 2.1mA
OL
0.4
V
V
I
= –400µA
OH
2.4
V
OH
V
ID
11.5
12.5
V
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
t
t
t
t
Address Valid to Program Low
Input Valid to Program Low
AVPL
AS
2
QVPL
DS
t
t
t
t
V
V
High to Program Low
High to Program Low
2
VPHPL
VPS
VCS
CES
PP
CC
t
2
VCHPL
t
Chip Enable Low to Program Low
Program Pulse Width
2
ELPL
t
t
PW
95
2
105
PLPH
t
t
DH
Program High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
PHQX
t
t
2
QXGL
GLQV
OES
t
t
100
130
OE
(2)
t
0
0
ns
ns
t
DFP
GHQZ
Output Enable High to Address
Transition
t
t
GHAX
AH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
let light (UV EPROM). The M27C1001 is in the
programming mode when V input is at 12.75V,
PP
When delivered (and after each erasure for UV
EPROM), all bits of the M27C1001 are in the '1'
state. Data is introduced by selectively program-
ming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposition to ultravio-
E is at V and P is pulsed to V . The data to be
IL
IL
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. V is specified to
CC
be 6.25V ± 0.25V.
7/17
M27C1001
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A16
tAVPL
Q0-Q7
DATA IN
DATA OUT
tQVPL
tVPHPL
tVCHPL
tPHQX
V
PP
tGLQV
tGHQZ
tGHAX
V
CC
E
tELPL
tPLPH
P
tQXGL
G
PROGRAM
VERIFY
AI00714
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed, with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II involves in applying a se-
quence of 100µs program pulses to each byte until
a correct verify occurs (see Figure 7). During pro-
gramming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE provides necessary mar-
gin to each programmed cell.
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
P = 100µs Pulse
NO
NO
++n
= 25
Program Inhibit
VERIFY
YES
++ Addr
Programming of multiple M27C1001s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C1001 may be common. A TTL low level
pulse applied to a M27C1001's P input, with E low
YES
Last
Addr
NO
FAIL
and V at 12.75V, will program that M27C1001.
A high level E input inhibits the other M27C1001s
from being programmed.
PP
YES
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
Program Verify
CC
CC
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
AI00715C
and G at V , P at V , V at 12.75V and V at
IL
IH
PP
CC
6.25V.
8/17
M27C1001
Electronic Signature
ERASURE OPERATION (applies to UV EPROM)
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C1001. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
The erasure characteristics of the M27C1001 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C1001 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C1001 is to be exposed to
these types of lighting conditions for extended pe-
riods of time, it is suggested that opaque labels be
put over the M27C1001 window to prevent unin-
tentional erasure. The recommended erasure pro-
cedure for the M27C1001 is exposure to short
wave ultraviolet light which has a wavelength of
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
M27C1001, with V = V
= 5V. Two identifier
PP
CC
bytes may then be sequenced from the device out-
puts by toggling address line A0 from V to V . All
IL
IH
other address lines must be held at V during
IL
Electronic Signature mode.
Byte 0 (A0 = V ) represents the manufacturer
IL
code and byte 1 (A0 = V ) the device identifier
IH
code. For the STMicroelectronics M27C1001,
these two identifier bytes are given in Table 4 and
can be read-out on outputs Q7 to Q0.
2
of 15 W-sec/cm . The erasure time with this dos-
age is approximately 15 to 20 minutes using an ul-
2
traviolet lamp with 12000 µW/cm power rating.
The M27C1001 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
9/17
M27C1001
Table 11. Ordering Information Scheme
Example:
M27C1001
-35
X
C
1
TR
Device Type
M27
Supply Voltage
C = 5V
Device Function
1001 = 1 Mbit (128Kb x8)
Speed
(1)
-35
= 35 ns
-45 = 45 ns
-60 = 60 ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-25 = 250 ns
V
CC
Tolerance
blank = ± 10%
X = ± 5%
Package
F = FDIP32W
B = PDIP32
L = LCCC32W
C = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Options
X = Additional Burn-in
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
10/17
M27C1001
Table 12. Revision History
Date
Revision Details
September 1998 First Issue
24-Jan-2000
20-Sep-2000
35ns speed class addes (Table 8A, 11)
AN620 Reference removed
PLCC32 Package mechanical data and drawing clarified (Table 16 and Figure 11)
TSOP32 Package mechanical data clarified (Table 17)
04-Jun-2002
11/17
M27C1001
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
41.73
–
0.30
42.04
–
0.009
1.643
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
0.637
0.125
0.060
–
0.710
S
2.49
–
0.098
–
7.11
0.280
α
4°
11°
4°
11°
N
32
32
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
12/17
M27C1001
Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
inches
Min
–
Symbol
Typ
Min
–
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
41.78
–
0.30
42.04
–
0.008
1.645
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.600
15.24
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.03
10°
0.600
0.125
0.070
0°
0.700
0.135
0.080
10°
S
α
N
32
32
Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
13/17
M27C1001
Table 15. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
2.28
0.71
11.63
14.22
–
Typ
Max
0.090
0.028
0.458
0.560
–
A
B
0.51
11.23
13.72
–
0.020
0.442
0.540
–
D
E
e
1.27
0.050
e1
e2
e3
h
0.39
–
–
0.015
–
–
7.62
10.16
1.02
–
0.300
0.400
0.040
0.020
–
–
–
–
–
–
–
–
–
j
0.51
–
–
–
–
L
1.14
1.96
10.50
8.03
32
1.40
2.36
10.80
8.23
0.045
0.077
0.413
0.316
32
0.055
0.093
0.425
0.324
L1
K
K1
N
Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Outline
e2
D
j x 45o
e
N
1
L1
B
e1
K
E
e3
K1
A
h x 45o
L
LCCCW-a
Drawing is not to scale.
14/17
M27C1001
Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
A
Typ
Max
3.56
2.41
–
Typ
Max
0.140
0.095
–
3.18
0.125
0.060
0.015
0.013
0.026
A1
A2
B
1.53
0.38
0.33
0.53
0.81
0.10
12.57
11.51
5.66
–
0.021
0.032
0.004
0.495
0.453
0.223
–
B1
CP
D
0.66
12.32
11.35
4.78
–
0.485
0.447
0.188
–
D1
D2
D3
E
7.62
0.300
14.86
13.89
6.05
–
15.11
14.05
6.93
–
0.585
0.547
0.238
–
0.595
0.553
0.273
–
E1
E2
E3
e
10.16
1.27
0.400
0.050
–
–
–
–
F
0.00
0.13
0.000
0.005
N
32
32
R
0.89
–
–
0.035
–
–
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
A2
D1
1 N
B1
e
E2
E3
E1 E
F
B
0.51 (.020)
E2
1.14 (.045)
D3
A
R
CP
D2
D2
PLCC-A
Drawing is not to scale.
15/17
M27C1001
Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.250
0.210
0.100
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0098
0.0083
0.0039
0.7953
0.7283
–
A
A1
A2
B
0.050
0.950
0.170
0.100
0.0020
0.0374
0.0067
0.0039
C
CP
D
19.800
18.300
–
0.7795
0.7205
–
D1
e
0.500
0.0197
E
7.900
0.500
0°
8.100
0.700
5°
0.3110
0.0197
0°
0.3189
0.0276
5°
L
α
N
32
32
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
16/17
M27C1001
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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