M27C202-150B3TR [STMICROELECTRONICS]
2 Mbit 128Kb x16 UV EPROM and OTP EPROM; 2兆位128KB X16 UV EPROM和OTP EPROM
| 型号： | M27C202-150B3TR |
| 厂家： | 
ST |
| 描述： | 2 Mbit 128Kb x16 UV EPROM and OTP EPROM |
| 文件： | 总15页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27C202
2 Mbit (128Kb x16) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 45ns
■ LOW POWER CONSUMPTION:
– Active Current 50mA at 5MHz
– Standby Current 100µA
40
40
1
1
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
FDIP40W (F)
PDIP40 (B)
– Device Code: 1Ch
TSOP40 (N)
10 x 14 mm
DESCRIPTION
PLCC44 (K)
The M27C202 is a 2 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs, in
the application where the contents is stable and
needs to be programmed only one time, and is or-
ganised as 131,072 by 16 bits.
Figure 1. Logic Diagram
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C202 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14 mm) packages.
V
V
CC
PP
17
16
A0-A16
Q0-Q15
P
E
M27C202
G
V
SS
AI01815
April 1999
1/15
M27C202
Figure 2A. DIP Connections
Figure 2B. TSOP Connections
V
1
2
3
4
5
6
7
8
9
40
39
V
P
A9
A10
A11
A12
A13
A14
A15
A16
P
1
40
V
SS
A8
PP
E
CC
Q15
Q14
Q13
Q12
Q11
Q10
Q9
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
A7
A6
A5
A4
A3
A2
A1
Q8 10
V
10
11
31
30
A0
CC
M27C202
M27C202
V
11
30
V
SS
V
G
SS
PP
E
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
G
20
DQ8
20
21
V
SS
AI02784
AI01817B
Figure 2C. LCC Connections
Table 1. Signal Names
A0-A16
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program
Q0-Q15
E
G
P
1 44
Q12
A13
A12
A11
A10
A9
Q11
Q10
Q9
V
Program Supply
Supply Voltage
Ground
PP
Q8
V
CC
V
12
M27C202
34
V
SS
SS
NC
Q7
Q6
Q5
Q4
NC
A8
A7
A6
A5
V
SS
NC
Not Connected Internally
23
AI01816
2/15
M27C202
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
–2 to 7
V
CC
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V +2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
E
G
P
A9
X
Q15-Q0
Data Output
Hi-Z
PP
V
V
V
V
V
or V
or V
Read
IL
IL
IL
IL
IL
IH
CC
CC
SS
SS
Output Disable
Program
V
V
V
V
V
X
X
IH
V
Pulse
V
X
X
Data Input
Data Output
Hi-Z
IL
PP
PP
PP
Verify
V
V
X
V
IL
IH
V
Program Inhibit
Standby
X
X
X
IH
IH
V
V
or V
CC SS
X
X
X
Hi-Z
V
V
V
V
V
CC
Electronic Signature
Codes
IL
IL
IH
ID
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
Q1
0
Q0
Hex Data
20h
V
0
1
0
0
IL
V
0
0
0
1
1
0
1Ch
IH
Note: Outputs Q15-Q8 are set to ’0’.
3/15
M27C202
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
IN
C
OUT
V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
The operating modes of the M27C202 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
(t
(t
) is equal to the delay from E to output
). Data is available at the output after a delay
AVQV
ELQV
of t from the falling edge of G, assuming that E
OE
levels except for V and 12V on A9 for Electronic
PP
has been low and the addresses have been stable
Signature.
Read Mode
for at least t
-t
.
AVQV GLQV
Standby Mode
The M27C202 has a standby mode which reduces
the supply current from 50mA to 100µA.
The M27C202 is placed in the standby mode by
applying a TTL high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
The M27C202 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G) is the output control and should
be used to gate data to the output pins, indepen-
4/15
M27C202
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; V = 5V ± 10%; V = V
)
CC
A
CC
PP
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±10
±10
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
µA
LO
E = V , G = V ,
IL
IL
I
Supply Current
50
mA
CC
I
= 0mA, f = 5MHz
OUT
I
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
E = V
1
mA
µA
µA
V
CC1
IH
I
E > V – 0.2V
CC
100
100
0.8
CC2
I
V
= V
PP CC
PP
V
Input Low Voltage
–0.3
2
IL
(2)
V
+ 1
Input High Voltage
V
V
CC
IH
V
I
= 2.1mA
= –400µA
= –100µA
Output Low Voltage
0.4
V
V
V
OL
OL
Output High Voltage TTL
Output High Voltage CMOS
I
I
2.4
OH
OH
V
OH
V
– 0.7V
CC
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
.
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
Two Line Output Control
System Considerations
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I , has three seg-
CC
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
M27C202
(1)
Table 8. Read Mode AC Characteristics
(T = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; V = 5V ± 10%; V = V
)
CC
A
CC
PP
M27C202
(3)
(3)
Symbol
Alt
Parameter
Test Condition
-80
-100
Unit
-45
-70
Min Max Min Max Min Max Min Max
Address Validto
Output Valid
t
t
E = V , G = V
45
45
25
25
25
70
70
40
30
30
80
80
40
30
30
100
100
50
ns
ns
ns
ns
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
IL
ELQV
CE
Output Enable Low
to Output Valid
t
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
G = V
IL
0
0
0
0
0
0
0
0
0
0
0
0
30
t
DF
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
E = V
IL
30
t
DF
GHQZ
Address Transition to
Output Transition
t
t
E = V , G = V
IL IL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Figure 5. Read Mode AC Waveforms
VALID
VALID
A0-A16
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q15
AI01818B
6/15
M27C202
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
Input Leakage Current
Supply Current
0 ≤ V ≤ V
LI
IN
IH
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
–0.3
2
0.8
IL
V
V
+ 0.5
CC
V
IH
V
OL
I
= 2.1mA
OL
0.4
V
V
I
= –400µA
2.4
V
OH
OH
V
11.5
12.5
V
ID
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
t
t
t
Address Valid to Program Low
Input Valid to Program Low
AVPL
AS
t
2
QVPL
DS
t
t
V
V
High to Program Low
High to Program Low
2
VPHPL
VPS
VCS
CES
PP
CC
t
t
t
2
VCHPL
t
t
Chip Enable Low to Program Low
Program Pulse Width
2
ELPL
t
95
2
105
PLPH
PW
t
t
Program High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
PHQX
DH
t
t
2
QXGL
GLQV
OES
t
t
100
130
OE
(2)
t
Output Enable High to Output Hi-Z
0
0
ns
ns
t
DFP
GHQZ
Output Enable High to Address
Transition
t
t
GHAX
AH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
light (UV EPROM). The M27C202 is in the pro-
gramming mode when V input is at 12.75V, E is
PP
When delivered (and after each ‘1’s erasure for UV
EPROM), all bits of the M27C202 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ‘0’ to a ‘1’ is by die exposure to ultraviolet
at V and P is pulsed to V . The data to be pro-
IL
IL
grammed is applied to 16 bits in parallel, to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. V is specified to
CC
be 6.25V ± 0.25V.
7/15
M27C202
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A15
Q0-Q15
tAVPL
tQVPL
DATA IN
DATA OUT
tPHQX
V
PP
tVPHPL
tGLQV
tGHQZ
tGHAX
V
CC
tVCHPL
E
tELPL
tPLPH
P
tQXGL
G
PROGRAM
VERIFY
AI00706
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II consists of applying a se-
quence of 100µs program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
P = 100µs Pulse
NO
NO
++n
= 25
VERIFY
YES
++ Addr
Program Inhibit
YES
Programming of multiple M27C202s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C202 may be common. A TTL low level pulse
applied to a M27C202’s P input, with E low and
Last
Addr
NO
FAIL
YES
V
at 12.75V, will program that M27C202. A high
PP
CHECK ALL WORDS
level E input inhibits the other M27C202s from be-
ing programmed.
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
Program Verify
AI00707C
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at V , P at V , V at 12.75V and V at
IL
IH
PP
CC
6.25V.
8/15
M27C202
On-Board Programming
ERASURE OPERATION (applies to UV EPROM)
The M27C202 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
The erasure characteristics of the M27C202 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C202 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C202 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27C202 window to prevent unintentional era-
sure. The recommended erasure procedure for
the M27C202 is exposure to short wave ultraviolet
light which has wavelength 2537 Å. The integrated
dose (i.e. UV intensity x exposure time) for erasure
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C202. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the M27C202
with V = V = 5V. Two identifier bytes may
PP
CC
then be sequenced from the device outputs by tog-
gling address line A0 from V to V . All other ad-
2
IL
IH
should be a minimum of 15 W-sec/cm . The era-
dress lines must be held at V during Electronic
IL
sure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with
Signature mode. Byte 0 (A0 = V ) represents the
IL
manufacturer code and byte 1 (A0 = V ) the de-
2
IH
12000µW/cm power rating. The M27C202 should
vice identifier code. For the STMicroelectronics
M27C202, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q7 to Q0.
be placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before era-
sure.
9/15
M27C202
Table 11. Ordering Information Scheme
Example:
M27C202
-80
K
1
TR
Device Type
M27
Supply Voltage
C = 5V ±10%
Device Function
202 = 2 Mbit (128Kb x16)
Speed
(1)
-45
= 45 ns
= 70 ns
(1)
-70
-80 = 80 ns
-100 = 100 ns
(2)
Not For New Design
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP40W
B = PDIP40
K = PLCC44
N = TSOP40: 10 x 14 mm
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Options
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
2. These speeds are replaced by the 100ns.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
10/15
M27C202
Table 12. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Min
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
51.79
–
0.30
52.60
–
0.009
2.039
–
0.012
2.071
–
D
D2
E
48.26
15.24
1.900
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
–
0.637
0.125
0.060
–
0.710
–
S
2.49
–
0.098
–
8.13
0.320
α
4°
11°
4°
11°
N
40
40
Figure 8. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
11/15
M27C202
Table 13. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm
Min
–
inches
Min
Symb
Typ
4.45
0.64
Max
–
Typ
Max
–
A
A1
A2
B
0.175
0.025
–
0.38
3.56
0.38
1.14
0.20
51.78
–
–
0.015
0.140
0.015
0.045
0.008
2.039
–
–
3.91
0.53
1.78
0.31
52.58
–
0.154
0.021
0.070
0.012
2.070
–
B1
C
D
D2
E
48.26
1.900
14.80
13.46
–
16.26
13.99
–
0.583
0.530
–
0.640
0.551
–
E1
e1
eA
eB
L
2.54
0.100
0.600
15.24
–
–
–
15.24
3.05
1.52
0°
17.78
3.81
2.29
15°
0.600
0.120
0.060
0°
0.700
0.150
0.090
15°
S
α
N
40
40
Figure 9. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
12/15
M27C202
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
mm
Min
4.20
2.29
–
inches
Min
Symb
Typ
Max
4.70
3.04
0.51
0.53
0.81
17.65
16.66
16.00
17.65
16.66
16.00
–
Typ
Max
0.185
0.120
0.020
0.021
0.032
0.695
0.656
0.630
0.695
0.656
0.630
–
A
A1
A2
B
0.165
0.090
–
0.33
0.66
17.40
16.51
14.99
17.40
16.51
14.99
–
0.013
0.026
0.685
0.650
0.590
0.685
0.650
0.590
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
44
44
CP
0.10
0.004
Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
13/15
M27C202
Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
14.20
12.50
10.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.559
0.492
0.398
–
A
A1
A2
B
0.05
0.95
0.17
0.10
13.80
12.30
9.90
–
0.002
0.037
0.007
0.004
0.543
0.484
0.390
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
40
40
CP
0.10
0.004
Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
14/15
M27C202
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