M27C256B-12XF6TR [STMICROELECTRONICS]
256 Kbit (32Kb x 8) UV EPROM and OTP EPROM; 256千位(32KB ×8) UV EPROM和OTP EPROM型号: | M27C256B-12XF6TR |
厂家: | ST |
描述: | 256 Kbit (32Kb x 8) UV EPROM and OTP EPROM |
文件: | 总16页 (文件大小:149K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M27C256B
256 Kbit (32Kb x 8) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 45ns
■ LOW POWER CONSUMPTION:
– Active Current 30mA at 5MHz
– Standby Current 100µA
28
28
1
1
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
FDIP28W (F)
PDIP28 (B)
– Device Code: 8Dh
DESCRIPTION
The M27C256B is a 256 Kbit EPROM offered in
the two ranges UV (ultra violet erase) and OTP
(one time programmable). It is ideally suited for mi-
croprocessor systems and is organized as 32,768
by 8 bits.
PLCC32 (C)
TSOP28 (N)
8 x 13.4 mm
Figure 1. Logic Diagram
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C256B is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
V
V
PP
CC
15
8
A0-A14
Q0-Q7
E
M27C256B
G
V
SS
AI00755B
August 2002
1/16
M27C256B
Figure 2A. DIP Connections
Figure 2B. LCC Connections
V
1
2
3
4
5
6
7
8
9
28
V
CC
PP
A12
A7
A6
A5
A4
A3
A2
A1
27 A14
26 A13
25 A8
24 A9
23 A11
1 32
A6
A8
A9
A11
NC
G
A5
A4
A3
22
G
M27C256B
A2
A1
A0
NC
Q0
9
M27C256B
25
21 A10
20
A10
E
E
A0 10
Q0 11
Q1 12
Q2 13
19 Q7
18 Q6
17 Q5
16 Q4
15 Q3
Q7
Q6
17
V
14
SS
AI00756
AI00757
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A14
Q0-Q7
E
Address Inputs
Data Outputs
Chip Enable
Output Enable
G
A11
A9
22
21
A10
E
G
Q7
Q6
Q5
Q4
Q3
A8
V
Program Supply
Supply Voltage
Ground
PP
A13
A14
V
CC
V
28
1
15
14
CC
V
SS
M27C256B
V
V
SS
PP
A12
Q2
Q1
Q0
A0
A1
A2
NC
DU
Not Connected Internally
Don’t Use
A7
A6
A5
A4
A3
7
8
AI00614B
2/16
M27C256B
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
CC
–2 to 7
V
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
PP
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
E
G
A9
X
Q7-Q0
Data Out
Hi-Z
V
IL
V
IL
Read
V
IL
V
IH
V
IH
Output Disable
Program
X
V
Pulse
X
Data In
Data Out
Hi-Z
IL
V
V
V
Verify
X
IH
IH
IH
IL
V
V
Program Inhibit
Standby
X
IH
X
X
Hi-Z
V
IL
V
V
ID
Electronic Signature
Codes
IL
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
0
Hex Data
20h
V
IL
V
1
0
0
0
1
1
0
1
8Dh
IH
3/16
M27C256B
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
IN
C
OUT
V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
dresses are stable, the address access time
(t
) is equal to the delay from E to output
). Data is available at the output after delay
AVQV
The operating modes of the M27C256B are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL lev-
(t
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been sta-
els except for V and 12V on A9 for Electronic
PP
ble for at least t
-t
.
AVQV GLQV
Signature.
Standby Mode
Read Mode
The M27C256B has a standby mode which reduc-
es the supply current from 30mA to 100µA. The
M27C256B is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
The M27C256B has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
4/16
M27C256B
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V = 5V ± 5% or 5V ± 10%; V = V
)
A
CC
PP
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
Unit
µA
I
0V ≤ V ≤ V
±10
±10
LI
IN
CC
I
LO
0V ≤ V ≤ V
OUT CC
µA
E = V , G = V ,
IL
IL
I
Supply Current
30
mA
CC
I
= 0mA, f = 5MHz
OUT
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
E > V – 0.2V
CC
100
100
0.8
CC2
I
V
= V
PP CC
PP
V
IL
Input Low Voltage
–0.3
2
(2)
V
+ 1
Input High Voltage
V
V
CC
IH
V
I
= 2.1mA
= –1mA
Output Low Voltage
0.4
V
OL
OL
I
Output High Voltage TTL
Output High Voltage CMOS
3.6
V
OH
V
OH
I
= –100µA
V
CC
– 0.7V
V
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V = 5V ± 5% or 5V ± 10%; V = V
)
A
CC
PP
CC
M27C256B
(3)
Symbol
Alt
Parameter
Test Condition
-60 -70
-80
Unit
-45
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
t
t
E = V , G = V
45
45
25
25
25
60
60
30
30
30
70
70
35
30
30
80
80
40
30
30
ns
ns
ns
ns
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
ELQV
CE
IL
IL
IL
IL
Output Enable Low to
Output Valid
t
t
E = V
G = V
E = V
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
0
0
0
0
0
0
0
0
0
0
0
0
t
t
DF
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
DF
GHQZ
Address Transition to
Output Transition
t
t
E = V , G = V
IL IL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is desired from a particular memory de-
vice.
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
5/16
M27C256B
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V = 5V ± 5% or 5V ± 10%; V = V
)
A
CC
PP
CC
M27C256B
-10 -12
Min Max Min Max Min Max Min Max
Symbol
Alt
Parameter
Test Condition
-90
-15/-20/-25 Unit
Address Valid to
Output Valid
t
t
E = V , G = V
90
90
40
30
30
100
100
50
120
120
60
150
150
65
ns
ns
ns
ns
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
ELQV
CE
IL
IL
IL
IL
Output Enable Low to
Output Valid
t
t
E = V
G = V
E = V
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
0
0
0
0
0
0
30
0
0
0
40
0
0
0
50
t
DF
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
30
40
50
t
DF
GHQZ
Address Transition to
Output Transition
t
t
E = V , G = V
IL IL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A14
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q7
AI00758B
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
devices. The supply current, I , has three seg-
and V . This should be a high frequency capaci-
CC
SS
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/16
M27C256B
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
Input Leakage Current
Supply Current
V
≤ V ≤ V
LI
IL
IN
IH
I
CC
I
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
PP
IL
V
IL
–0.3
2
0.8
V
IH
V
+ 0.5
V
CC
V
OL
I
= 2.1mA
= –1mA
0.4
V
OL
V
I
OH
3.6
V
OH
V
11.5
12.5
V
ID
Note: V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
t
t
t
t
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
AVEL
AS
2
QVEL
DS
t
t
t
t
V
V
High to Chip Enable Low
High to Chip Enable Low
2
VPHEL
VPS
VCS
PP
CC
2
VCHEL
t
t
PW
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
Output Enable High to Address Transition
95
2
105
ELEH
t
t
DH
EHQX
t
t
2
QXGL
GLQV
OES
t
t
t
100
130
OE
t
0
0
GHQZ
GHAX
DFP
t
t
AH
Note: V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
Programming
light (UV EPROM). The M27C256B is in the pro-
gramming mode when V input is at 12.75V, G is
When delivered (and after each erasure for UV
EPROM), all bits of the M27C256B are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a '0' to a '1' is by die exposure to ultraviolet
PP
at V and E is pulsed to V . The data to be pro-
IH
IL
grammed is applied to 8 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. V
6.25V ± 0.25 V.
is specified to be
CC
7/16
M27C256B
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A14
tAVEL
Q0-Q7
DATA IN
tQVEL
DATA OUT
tEHQX
V
PP
tVPHEL
tVCHEL
tGLQV
tGHQZ
tGHAX
V
CC
E
tELEH
tQXGL
G
PROGRAM
VERIFY
AI00759
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100µs program pulses to each byte until a cor-
rect verify occurs (see Figure 7). During program-
ming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE provides necessary mar-
gin to each programmed cell.
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
E = 100µs Pulse
NO
NO
++n
= 25
VERIFY
YES
++ Addr
Program Inhibit
YES
Programming of multiple M27C256Bs in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C256B may be common. A TTL low level
Last
Addr
NO
FAIL
pulse applied to a M27C256B's E input, with V
PP
YES
at 12.75V, will program that M27C256B. A high
level E input inhibits the other M27C256Bs from
being programmed.
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
AI00760B
at V , E at V , V at 12.75V and V at 6.25V.
IL
IH
PP
CC
8/16
M27C256B
Electronic Signature
ERASURE OPERATION (applies for UV EPROM)
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C256B. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
The erasure characteristics of the M27C256B is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C256B in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C256B is to be exposed to
these types of lighting conditions for extended pe-
riods of time, it is suggested that opaque labels be
put over the M27C256B window to prevent unin-
tentional erasure. The recommended erasure pro-
cedure for the M27C256B is exposure to short
wave ultraviolet light which has wavelength
2537Å. The integrated dose (i.e. UV intensity x ex-
posure time) for erasure should be a minimum of
M27C256B, with V
= V = 5V. Two identifier
CC
PP
bytes may then be sequenced from the device out-
puts by toggling address line A0 from V to V . All
IL
IH
other address lines must be held at V during
IL
Electronic Signature mode. Byte 0 (A0 = V ) rep-
IL
resents the manufacturer code and byte 1
(A0 = V ) the device identifier code. For the ST-
IH
Microelectronics M27C256B, these two identifier
bytes are given in Table 4 and can be read-out on
outputs Q7 to Q0.
2
15 W-sec/cm . The erasure time with this dosage
is approximately 15 to 20 minutes using an ultravi-
2
olet lamp with 12000 µW/cm power rating. The
M27C256B should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
9/16
M27C256B
Table 11. Ordering Information Scheme
Example:
M27C256B
-70
X
C
1
TR
Device Type
M27
Supply Voltage
C = 5V
Device Function
256B = 256 Kbit (32Kb x 8)
Speed
(1)
-45
= 45 ns
-60 = 60 ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-25 = 250 ns
V
CC
Tolerance
blank = ± 10%
X = ± 5%
Package
F = FDIP28W
B = PDIP28
C = PLCC32
N = TSOP28: 8 x 13.4 mm
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Options
X = Additional Burn-in
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
10/16
M27C256B
Table 12. Revision History
Date
July 1998
Version
1.0
Revision Details
First Issue
20-Sep-2000
29-Nov-2000
02-Apr-2001
1.1
AN620 Reference removed
1.2
PLCC codification changed (Table 11)
1.3
FDIP28W mechanical dimensions changed (Table 13)
Package mechanical data clarified for PDIP28 (Table 14),
PLCC32 (Table 15, Figure 10) and TSOP28 (Table 16, Figure 11)
29-Aug-2002
1.4
11/16
M27C256B
Table 13. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
36.50
–
0.30
37.34
–
0.009
1.437
–
0.012
1.470
–
D
D2
E
33.02
15.24
1.300
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
4.10
2.49
–
0.637
0.125
0.060
–
0.710
0.161
0.098
–
S
7.11
0.280
α
4°
11°
4°
11°
N
28
28
Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
12/16
M27C256B
Table 14. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
4.445
0.630
3.810
0.450
1.270
0.1750
0.0248
0.1500
0.0177
0.0500
3.050
4.570
0.1201
0.1799
B1
C
0.230
36.580
–
0.310
37.080
–
0.0091
1.4402
–
0.0122
1.4598
–
D
36.830
33.020
15.240
13.720
2.540
1.4500
1.3000
0.6000
0.5402
0.1000
0.5906
D2
E
E1
e1
eA
eB
L
12.700
–
14.480
–
0.5000
–
0.5701
–
15.000
14.800
15.200
15.200
16.680
0.5827
0.5984
0.5984
0.6567
3.300
0.1299
S
1.78
0°
2.08
10°
0.070
0°
0.082
10°
α
N
28
28
Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
13/16
M27C256B
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
3.56
2.41
–
Typ
Max
0.140
0.095
–
A
A1
A2
B
3.18
0.125
0.060
0.015
0.013
0.026
1.53
0.38
0.33
0.53
0.81
0.10
12.57
11.51
5.66
–
0.021
0.032
0.004
0.495
0.453
0.223
–
B1
CP
D
0.66
12.32
11.35
4.78
–
0.485
0.447
0.188
–
D1
D2
D3
E
7.62
0.300
14.86
13.89
6.05
–
15.11
14.05
6.93
–
0.585
0.547
0.238
–
0.595
0.553
0.273
–
E1
E2
E3
e
10.16
1.27
0.400
0.050
–
–
–
–
F
0.00
–
0.13
–
0.000
–
0.005
–
R
0.89
0.035
N
32
32
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
A2
D1
1 N
B1
e
E2
E2
E3
E1 E
F
B
0.51 (.020)
1.14 (.045)
D3
A
R
CP
D2
D2
PLCC-A
Drawing is not to scale.
14/16
M27C256B
Table 16. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.250
0.200
1.150
0.270
0.210
0.100
13.600
11.900
–
Typ
Max
0.0492
0.0079
0.0453
0.0106
0.0083
0.0039
0.5354
0.4685
–
A
A1
A2
B
0.950
0.170
0.100
0.0374
0.0067
0.0039
C
CP
D
13.200
11.700
–
0.5197
0.4606
–
D1
e
0.550
0.0217
E
7.900
0.500
0°
8.100
0.700
5°
0.3110
0.0197
0°
0.3189
0.0276
5°
L
α
N
28
28
Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale
15/16
M27C256B
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