M27C4002-10J6 [STMICROELECTRONICS]
256KX16 UVPROM, 100ns, CQCC44, WINDOWED, CERAMIC, LCC-44;
| 型号： | M27C4002-10J6 |
| 厂家： | 
ST |
| 描述： | 256KX16 UVPROM, 100ns, CQCC44, WINDOWED, CERAMIC, LCC-44 可编程只读存储器 |
| 文件： | 总17页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27C4002
4 Mbit (256Kb x16) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 45ns
■ LOW POWER CONSUMPTION:
– Active Current 70mA at 10MHz
– Standby Current 100µA
40
40
1
1
FDIP40W (F)
PDIP40 (B)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 44h
JLCC44W (J)
DESCRIPTION
The M27C4002 is a 4 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and
is organised as 262,144 words of 16 bits.
PLCC44 (C)
TSOP40 (N)
10 x 20 mm
The FDIP40W (window ceramic frit-seal package)
and the JLCC44W (J-lead chip carrier packages)
have transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
Figure 1. Logic Diagram
V
V
PP
For applications where the content is programmed
only one time and erasure is not required, the
M27C4002 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.
CC
18
16
A0-A17
Q0-Q15
E
M27C4002
G
V
SS
AI00727B
September 2000
1/17
M27C4002
Figure 2A. DIP Connections
Figure 2B. LCC Connections
V
1
2
3
4
5
6
7
8
9
40
V
CC
PP
E
39 A17
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
Q15
Q14
Q13
Q12
Q11
Q10
Q9
1 44
Q12
A13
A12
A11
A10
A9
Q11
Q10
Q9
Q8
Q8 10
M27C4002
V
12
M27C4002
34
V
SS
SS
V
11
30
V
SS
SS
NC
Q7
Q6
Q5
Q4
NC
A8
A7
A6
A5
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
23
AI00729
G
20
AI00728
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A17
Address Inputs
A9
A10
A11
A12
A13
A14
A15
A16
A17
1
40
V
SS
A8
Q0-Q15
Data Outputs
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
A7
E
A6
A5
G
A4
A3
V
PP
A2
A1
V
CC
V
10 M27C4002 31
(Normal)
A0
CC
V
V
11
30
G
SS
PP
E
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NC
Not Connected Internally
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
20
21
V
SS
AI01831
2/17
M27C4002
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
–2 to 7
V
CC
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
E
G
A9
X
Q15-Q0
Data Out
Hi-Z
PP
V
V
V
V
or V
or V
Read
IL
IL
IH
IH
CC
CC
SS
SS
Output Disable
Program
V
V
V
X
IL
V
Pulse
V
X
Data In
Data Out
Hi-Z
IL
PP
PP
PP
Verify
V
V
V
X
V
IH
IH
IH
IL
V
V
Program Inhibit
Standby
X
IH
V
V
or V
CC SS
X
X
Hi-Z
V
V
V
V
CC
Electronic Signature
Codes
IL
IL
ID
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
Hex Data
20h
V
0
0
IL
V
0
1
0
0
0
1
0
44h
IH
Note: Outputs Q15-Q8 are set to ’0’.
DEVICE OPERATION
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
The operating modes of the M27C4002 are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for V and 12V on A9 for Electronic
PP
(t
(t
) is equal to the delay from E to output
). Data is available at the output after a delay
GLQV
AVQV
ELQV
of t
Signature.
Read Mode
from the falling edge of G, assuming that
The M27C4002 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
E has been low and the addresses have been sta-
ble for at least t -t
.
AVQV GLQV
3/17
M27C4002
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3A. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
= 0V
Min
Max
6
Unit
pF
C
V
IN
Input Capacitance
Output Capacitance
IN
C
OUT
V
= 0V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
Standby Mode
a. the lowest possible memory power dissipation,
The M27C4002 has a standby mode which reduc-
es the supply current from 50mA to 100µA. The
M27C4002 is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
4/17
M27C4002
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 5% or 5V ± 10%; V = V
)
CC
A
CC
PP
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
Unit
µA
I
±10
±10
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
µA
LO
E = V , G = V ,
IL
IL
70
50
mA
mA
I
= 0mA, f = 10MHz
OUT
I
Supply Current
CC
E = V , G = V ,
IL
IL
I
= 0mA, f = 5MHz
OUT
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
E > V – 0.2V
CC
100
10
CC2
I
V
= V
PP CC
PP
V
Input Low Voltage
–0.3
2
0.8
IL
(2)
V
+ 1
Input High Voltage
V
V
CC
IH
V
I
= 2.1mA
= –400µA
= –100µA
Output Low Voltage
0.4
V
OL
OL
I
I
Output High Voltage TTL
Output High Voltage CMOS
2.4
V
OH
OH
V
OH
V
– 0.7V
V
CC
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
.
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 5% or 5V ± 10%; V = V
)
CC
A
CC
PP
M27C4002
(3)
(3)
Symbol Alt
Parameter
Test Condition
-80
-90
Unit
- 45
-60
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
t
t
t
t
E = V , G = V
45
45
25
30
30
60
60
30
30
30
80
80
40
30
30
90
90
40
30
30
ns
ns
ns
ns
ns
ns
AVQV
ELQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
CE
IL
Output Enable Low
to Output Valid
E = V
GLQV
OE
IL
Chip Enable High to
Output Hi-Z
(2)
t
G = V
0
0
0
0
0
0
0
0
0
0
0
0
t
t
DF
DF
IL
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
E = V
IL
GHQZ
Address Transition
to Output Transition
t
t
E = V , G = V
AXQX
OH
IL
IL
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
5/17
M27C4002
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 5% or 5V ± 10%; V = V
)
A
CC
PP
CC
M27C4002
-12 -15
Min Max Min Max Min Max Min Max
Symbol
Alt
Parameter
Test Condition
-10
-20
Unit
Address Valid to
Output Valid
t
t
E = V , G = V
100
100
50
120
120
60
150
150
60
200
200
70
ns
ns
ns
ns
ns
ns
AVQV
ACC
IL
IL
Chip Enable Low to
Output Valid
t
t
G = V
IL
ELQV
CE
Output Enable Low
to Output Valid
t
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
DF
G = V
IL
0
0
0
30
0
0
0
40
0
0
0
50
0
0
0
80
t
t
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
DF
E = V
IL
30
40
50
80
GHQZ
Address Transition
to Output Transition
t
t
E = V , G = V
IL IL
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A17
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q15
AI00731B
System Considerations
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
The power switching characteristics of Advanced
CMOS EPROMs requirecareful decoupling of the
devices. The supply current, I , has three seg-
ic capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
CC
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
output capacitive and inductive loading of the de-
vice. The associated transient voltage peaks can
be suppressed by complying with the two line out-
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/17
M27C4002
(1)
Table 9. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
Input Leakage Current
Supply Current
V
≤ V ≤ V
LI
IL
IN
IH
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
–0.3
2
0.8
IL
V
V
+ 0.5
CC
V
IH
V
OL
I
= 2.1mA
OL
0.4
V
V
I
= –400µA
2.4
V
OH
OH
V
11.5
12.5
V
ID
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
ns
t
t
t
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
AVEL
AS
t
2
QVEL
DS
t
t
V
V
High to Chip Enable Low
High to Chip Enable Low
2
VPHEL
VPS
VCS
PP
CC
t
t
2
VCHEL
t
t
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
95
2
105
ELEH
PW
t
t
DH
EHQX
t
t
2
QXGL
GLQV
OES
t
t
t
100
130
OE
t
0
0
ns
GHQZ
DFP
Output Enable High to Address
Transition
t
t
ns
GHAX
AH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
light (UV EPROM). The M27C4002 is in the pro-
gramming mode when V input is at 12.75V, G is
PP
When delivered (and after each erasure for UV
EPROM), all bits of the M27C4002 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ’0’ to a ’1’ is by die exposure to ultraviolet
at V and E is pulsed to V . The data to be pro-
IH
IL
grammed is applied to 16 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. V
6.25V ± 0.25V.
is specified to be
CC
7/17
M27C4002
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A17
tAVEL
Q0-Q15
DATA OUT
DATA IN
tQVEL
tEHQX
V
PP
tVPHEL
tGLQV
tGHQZ
tGHAX
V
CC
tVCHEL
tELEH
E
tQXGL
G
PROGRAM
VERIFY
AI00730
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
E = 100µs Pulse
NO
NO
++n
= 25
VERIFY
YES
++ Addr
Program Inhibit
Programming of multiple M27C4002s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C4002 may be common. A TTL low level
YES
Last
Addr
NO
FAIL
pulse applied to a M27C4002’s E input, with V
PP
at 12.75V, will program that M27C4002. A high
level E input inhibits the other M27C4002s from
being programmed.
YES
CHECK ALL WORDS
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
AI00726C
at V , E at V , V at 12.75V and V at 6.25V.
IL
IH
PP
CC
8/17
M27C4002
Electronic Signature
ERASURE OPERATION (applies to UV EPROM)
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C4002. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
The erasure characteristics of the M27C4002 are
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase atypical M27C4002 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C4002 is to be exposed to
these types of lighting conditions for extended pe-
riods of time, it is suggested that opaque labels be
put over the M27C4002 window to prevent unin-
tentional erasure. The recommended erasure pro-
cedure for the M27C4002 is exposure to short
wave ultraviolet light which has wavelength 2537
Å. The integrated dose (i.e. UV intensity x expo-
sure time) for erasure should be a minimum of 15
M27C4002 with V = V = 5V. Two identifier
PP
CC
bytes maythen be sequenced from the device out-
puts by toggling address line A0 from V to V . All
IL
IH
other address lines must be held at V during
IL
Electronic Signature mode. Byte 0 (A0 = V ) rep-
IL
resents the manufacturer code and byte 1
(A0 = V ) the device identifier code. For the
IH
STMicroelectronics M27C4002, these two identifi-
er bytes are given in Table 4 and can be read-out
on outputs Q7 to Q0.
2
W-sec/cm . The erasure time with this dosage is
approximately 15 to 20 minutes using an ultravio-
2
let lamp with 12000 µW/cm power rating. The
M27C4002 should be placed within 2.5cm (1 inch)
of the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be re-
moved before erasure.
9/17
M27C4002
Table 11. Ordering Information Scheme
Example:
M27C4002
-80
X
C
1
X
Device Type
M27
Supply Voltage
C = 5V
Device Function
4002 = 4 Mbit (256Kb x16)
Speed
(1)
-45
= 45 ns
= 60 ns
(1)
-60
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
V
Tolerance
CC
blank = ± 10%
X = ± 5%
Package
F = FDIP40W
B = PDIP40
J = JLCC44W
C = PLCC44
N = TSOP40: 10 x 20 mm
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Options
X = Additional Burn-in
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
10/17
M27C4002
Table 12. Revision History
Date
Revision Details
September 1998 First Issue
09/25/00
AN620 Reference removed
11/17
M27C4002
Table 13. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Min
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
51.79
–
0.30
52.60
–
0.009
2.039
–
0.012
2.071
–
D
D2
E
48.26
15.24
1.900
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
0.637
0.125
0.060
–
0.710
S
2.49
–
0.098
–
7.62
0.300
α
4°
11°
4°
11°
N
40
40
Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
12/17
M27C4002
Table 14. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
Min
–
inches
Min
–
Symbol
Typ
4.45
0.64
Max
–
Typ
Max
–
A
A1
A2
B
0.175
0.025
0.38
3.56
0.38
1.14
0.20
51.78
–
–
0.015
0.140
0.015
0.045
0.008
2.039
–
–
3.91
0.53
1.78
0.31
52.58
–
0.154
0.021
0.070
0.012
2.070
–
B1
C
D
D2
E
48.26
1.900
14.80
13.46
–
16.26
13.99
–
0.583
0.530
–
0.640
0.551
–
E1
e1
eA
eB
L
2.54
0.100
0.600
15.24
–
–
–
15.24
3.05
1.52
0°
17.78
3.81
2.29
15°
0.600
0.120
0.060
0°
0.700
0.150
0.090
15°
S
α
N
40
40
Figure 9. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
13/17
M27C4002
Table 15. JLCC44W - 44 lead Leadless Ceramic Chip Carrier, square window,
Package Mechanical Data
millimeters
Min
inches
Symbol
Typ
Max
4.83
3.05
0.53
0.81
17.65
16.89
16.26
–
Typ
Min
0.155
0.090
0.017
0.026
0.685
0.630
0.580
–
Max
0.190
0.120
0.021
0.032
0.695
0.665
0.640
–
A
A1
B
3.94
2.29
0.43
0.66
17.40
16.00
14.74
–
B1
D
D1
D2
D3
E
12.70
0.500
17.40
16.00
14.74
–
17.65
16.89
16.26
–
0.685
0.630
0.580
–
0.695
0.665
0.640
–
E1
E2
E3
e
12.70
1.27
0.500
0.050
0.400
–
–
–
–
K
10.16
–
–
–
–
N
44
44
CP
0.10
0.004
Figure 10. JLCC44W - 44 lead Leadless Ceramic Chip Carrier, square window, Package Outline
D
D1
A1
1 N
B1
e
E3
K
E1 E
D2/E2
B
K
D3
A
CP
JLCCW-a
Drawing is not to scale.
14/17
M27C4002
Table 16. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
4.70
3.04
0.51
0.53
0.81
17.65
16.66
16.00
17.65
16.66
16.00
–
Typ
Max
0.185
0.120
0.020
0.021
0.032
0.695
0.656
0.630
0.695
0.656
0.630
–
A
A1
A2
B
4.20
2.29
–
0.165
0.090
–
0.33
0.66
17.40
16.51
14.99
17.40
16.51
14.99
–
0.013
0.026
0.685
0.650
0.590
0.685
0.650
0.590
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
44
44
CP
0.10
0.004
Figure 11. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
15/17
M27C4002
Table 17. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
10.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.398
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
9.90
–
0.002
0.037
0.007
0.004
0.780
0.720
0.390
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
40
40
CP
0.10
0.004
Figure 12. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
16/17
M27C4002
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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