M27C405-70K1 [STMICROELECTRONICS]
512KX8 OTPROM, 70ns, PQCC32, PLASTIC, LCC-32;型号: | M27C405-70K1 |
厂家: | ST |
描述: | 512KX8 OTPROM, 70ns, PQCC32, PLASTIC, LCC-32 可编程只读存储器 |
文件: | 总14页 (文件大小:147K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M27C405
4 Mbit (512Kb x8) OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ PIN COMPATIBLE with the 4 Mbit, SINGLE
VOLTAGE FLASH MEMORY
32
■ ACCESS TIME: 70ns
■ LOW POWER CONSUMPTION:
– Active Current 30mA at 5MHz
– Standby Current 100µA
1
PDIP32 (B)
PLCC32 (K)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIMES
– Typical 48sec. (PRESTO II Algorithm)
– Typical 27sec. (On-Board Programming)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
TSOP32 (N)
8 x 20 mm
– Device Code: B4h
DESCRIPTION
Figure 1. Logic Diagram
The M27C405 is a 4 Mbit EPROM offered in the
OTP (one time programmable) range. It is ideally
suited for microprocessor systems requiring large
programs, in the application where the contents is
stable and needs to be programmed only one time
and is organised as 524,288 by 8 bits.
V
V
PP
CC
The M27C405 is pin compatible with the industry
standard 4 Mbit, single voltaFlash memory. It
can be considered as a Fsh Low Cost solution
for production quantes.
19
8
A0-A18
Q0-Q7
The M27C405 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
E
M27C405
G
V
SS
AI01601
September 2000
1/14
M27C405
Figure 2A. DIP Connections
Figure 2B. LCC Connections
A18
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32
31
V
V
CC
PP
30 A17
29 A14
28 A13
27 A8
1 32
A7
A14
A13
A8
A6
A5
A4
A6
A5
26 A9
A9
A4
25 A11
M27C405
A3
A2
A1
A0
Q0
9
M27C405
25 A11
G
A3
24
23 A10
22
G
A2 10
A1 11
A0 12
Q0 13
Q1 14
Q2 15
A10
E
E
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
Q7
17
V
16
SS
AI01603
AI01602
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A18
Q0-Q7
E
Address Inputs
Data Outputs
Chip Enable
Output Enable
A11
A9
1
32
G
A10
E
A8
G
A13
A14
A17
Q7
Q6
Q5
Q4
Q3
V
Program Supply
Supply Voltage
Ground
PP
V
CC
V
PP
V
8
9
M27C405
(Normal)
25
24
CC
V
SS
A18
A16
A15
A12
A7
V
SS
Q2
Q1
Q0
A0
A1
A2
A3
A6
A5
A4
16
17
AI01604
2/14
M27C405
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
(3)
T
A
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Ambient Operating Temperature
T
Temperature Under Bias
BIAS
T
STG
Storage Temperature
(2)
Input or Output Voltage (except A9)
V
IO
V
Supply Voltage
–2 to 7
–2 to 13.5
–2 to 14
V
V
V
CC
(2)
A9 Voltage
V
A9
V
Program Supply Voltage
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V +2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
E
G
A9
X
Q7-Q0
Data Out
Hi-Z
PP
V
V
V
V
or V
Read
IL
IL
IL
IH
IH
CC
SS
SS
V
V
V
or V
Output Disable
Program
X
CC
V
IL
Pulse
V
X
Data In
Data Out
Hi-Z
PP
PP
PP
V
V
V
V
Verify
X
IH
IH
IH
IL
V
V
V
Program Inhibit
Standby
X
IH
V
or V
SS
X
X
Hi-Z
CC
V
V
IL
V
ID
V
CC
Electronic Signature
Codes
IL
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
Q4
0
Q3
0
Q2
0
Q1
Q0
0
Hex Data
20h
V
IL
1
1
0
0
V
1
0
1
0
1
0
B4h
IH
3/14
M27C405
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
IN
C
V
OUT
12
pF
OUT
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
dresses are stable, the address access time
(t
(t
of t
) is equal to the delay from E to output
). Data is available at the output after a delay
AVQV
ELQV
The modes of operations of the M27C405 are list-
ed in the Operating Modes table. A single power
supply is required in the read mode. All inputs are
TTL levels except for V and 12V on A9 for Elec-
tronic Signature.
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been sta-
PP
ble for at least t
-t
.
AVQV GLQV
Standby Mode
Read Mode
The M27C405 has a standby mode which reduces
the active current from 30mA to 100µA. The
M27C405 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
The M27C405 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
4/14
M27C405
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 10%; V = V
)
A
CC
PP
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±10
±10
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
µA
E = V , G = V ,
IL
IL
I
Supply Current
30
mA
CC
I
= 0mA, f = 5MHz
OUT
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
E > V
– 0.2V
CC
100
10
CC2
I
PP
V
= V
PP CC
V
Input Low Voltage
–0.3
2
0.8
IL
(2)
V
+ 1
Input High Voltage
V
V
V
V
V
CC
IH
V
I
= 2.1mA
= –400µA
= –100µA
Output Low Voltage
0.4
OL
OL
I
Output High Voltage TTL
Output High Voltage CMOS
2.4
OH
OH
V
OH
I
V
– 0.7V
CC
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 10%; V = V
)
A
CC
PP
CC
M27C405
-80
(3)
Symbol
Alt
Parameter
Test Condition
-90
Unit
-70
Min Max Min Max Min Max
t
t
E = V , G = V
Address Valid to Output Valid
70
70
35
30
80
80
40
30
90
90
40
30
ns
ns
ns
ns
AVQV
ACC
IL
IL
t
t
G = V
IL
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
ELQV
CE
t
t
E = V
IL
GLQV
OE
(2)
t
t
G = V
0
0
0
0
0
0
t
DF
DF
IL
EHQZ
GHQZ
t
(2)
E = V
Output Enable High to Output Hi-Z
30
30
30
ns
ns
t
IL
Address Transition to Output
Transition
t
E = V , G = V
IL IL
0
0
0
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC Measurement conditions.
Two Line Output Control
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
5/14
M27C405
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 5V ± 10%; V = V
)
A
CC
PP
CC
M27C405
-120
Symbol
Alt
Parameter
Test Condition
-100
-150
Unit
Min Max Min Max Min Max
t
t
E = V , G = V
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
100
100
50
120
120
60
150 ns
150 ns
AVQV
ACC
IL
IL
t
t
G = V
IL
ELQV
CE
t
t
E = V
IL
60
50
50
ns
ns
ns
GLQV
OE
(2)
t
t
G = V
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
0
0
30
30
0
0
40
40
0
0
t
DF
DF
IL
EHQZ
(2)
E = V
t
IL
GHQZ
Address Transition to Output
Transition
t
t
E = V , G = V
IL IL
0
0
0
ns
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A18
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q7
AI00724B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
devices. The supply current, I , has three seg-
CC
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/14
M27C405
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
0 ≤ V ≤ V
Input Leakage Current
Supply Current
LI
IN
CC
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
–0.3
2
0.8
IL
V
IH
V
+ 0.5
CC
V
V
OL
I
= 2.1mA
OL
0.4
V
V
OH
I
= –400µA
2.4
V
OH
V
ID
11.5
12.5
V
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
µs
µs
µs
µs
µs
µs
µs
ns
ns
t
t
t
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
2
2
AVEL
AS
t
QVEL
DS
t
t
t
V
High to Chip Enable Low
High to Chip Enable Low
2
VPHEL
VPS
PP
CC
t
V
2
VCHEL
VCS
t
t
PW
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
95
2
105
ELEH
t
t
DH
EHQX
t
t
OES
2
QXGL
t
t
100
130
GLQV
OE
t
t
DFP
0
0
GHQZ
Output Enable High to Address
Transition
t
t
AH
ns
GHAX
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
12.75V, G is at V and E is pulsed to V . The data
IH IL
to be programmed is applied to 8 bits in parallel to
the data output pins. The levels required for the
When delivered, all bits of the M27C405 are in the
’1’ state.Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed, both ’1’s and ’0’s can
be present in the data word. The M27C405 is in
address and data inputs are TTL. V is specified
CC
to be 6.25V ±0.25V.
the programming mode when V
input is at
PP
7/14
M27C405
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A18
tAVPL
Q0-Q7
DATA IN
DATA OUT
tQVEL
tVPHEL
tVCHEL
tEHQX
V
PP
tGLQV
tGHQZ
tGHAX
V
CC
E
tELEH
tQXGL
G
PROGRAM
VERIFY
AI00725
PRESTO II Programming Algorithm
Program Verify
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V , E at V , V at 12.75V and V at 6.25V.
IL
IH
PP
CC
On-Board Programming
Programming the M27C405 may be performed di-
rectly in the application circuit, however this re-
quires modification to the PRESTO II Algorithm
(see Figure 8). For in-circuit programming V
is
CC
determined by the user and normally is compatible
with other components using the same supply volt-
age. It is recommended that the maximum value of
Program Inhibit
V
which remains compatible with the circuit is
CC
Programming of multiple M27C405s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C405 may be common. A TTL low level pulse
used.
Typically V = 5.5V for programming systems us-
CC
ing V = 5V is recommended. The value of V
CC
CC
does not affect the programming, it gives a higher
test capability in VERIFY mode.
applied to a M27C405's E input, with V
at
PP
12.75V, will program that M27C405. A high level E
input inhibits the other M27C405s from being pro-
grammed.
V
must be kept at 12.75 volts to maintain and
PP
enable the programming.
8/14
M27C405
Figure 7. Programming Flowchart
Figure 8. On-Board Programming Flowchart
V
= 12.75V
PP
V
= 6.25V, V
= 12.75V
PP
CC
SET MARGIN MODE
n = 0
n = 0
E = 100µs Pulse
E = 10µs Pulse
NO
NO
NO
++n
= 25
VERIFY
YES
++ Addr
NO
++n
= 25
VERIFY
++ Addr
?
YES
YES
YES
Last
Addr
NO
E = 10µs Pulse
FAIL
FAIL
YES
Last
NO
Addr
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
YES
CHECK ALL BYTES
= V
AI00760B
V
PP
CC
AI01349
Warning: compatibility with FLASH Memory
Electronic Signature
Compatibility issues may arise when replacing the
compatible Single Supply 4 Megabit FLASH Mem-
ory (the M29F040) by the M27C405.
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
This mode is functional in the 25°C ± 5°C ambient
temperature range that is required when program-
ming the M27C405. To activate the ES mode, the
programming equipment must force 11.5V to
12.5V on address line A9 of the M27C405 with
The V pin of the M27C405 corresponds to the
PP
"W" pin of the M29F040. The M27C405 V
pin
PP
can withstand voltages up to 12.75V, while the "W"
pin of the M29F040 is a normal control signal input
and may be damaged if a high voltage is applied;
special precautions must be taken when program-
ming in-circuit.
However if an already programmed M27C405 is
used, this can be directly put in place of the
V
= V = 5V. Two identifier bytes may then be
PP
CC
sequenced from the device outputs by toggling ad-
FLASH Memory as the V input, when not in pro-
PP
dress line A0 from V to V . All other address
IL
IH
gramming mode, is set to V or V
.
CC
SS
lines must be held at V during Electronic Signa-
IL
Changes to PRESTO II. The duration of the pro-
gramming pulse is reduced to 20µs, making the
programming time of the M27C405 comparable
with the counterpart FLASH Memory.
ture mode. Byte 0 (A0 = V ) represents the man-
IL
ufacturer code and byte 1 (A0 = V ) the device
IH
identifier code. For the STMicroelectronics
M27C405, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q7 to Q0.
9/14
M27C405
Table 11. Ordering Information Scheme
Example:
M27C405
-80
K
1
TR
Device Type
M27
Supply Voltage
C = 5V ±10%
Device Function
405 = 4 Mbit (512Kb x8)
Speed
(1)
-70
= 70 ns
-80 = 80 ns
-90 = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
Package
B = PDIP32
K = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Options
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 12. Revision History
Date
March 1998
09/25/00
Revision Details
First Issue
AN620 Reference removed
10/14
M27C405
Table 13. PDIP32 - 32 pin lead Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
inches
Min
–
Symbol
Typ
Min
–
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
41.78
–
0.30
42.04
–
0.008
1.645
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.600
15.24
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.03
10°
0.600
0.125
0.070
0°
0.700
0.135
0.080
10°
S
α
N
32
32
Figure 9. PDIP32 - 32 pin lead Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
11/14
M27C405
Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
3.56
2.41
Typ
Min
Max
0.140
0.095
A
A1
A2
B
2.54
0.100
0.060
0.015
0.013
0.026
0.485
0.447
0.390
1.52
0.38
0.33
0.53
0.81
0.021
0.032
0.495
0.455
0.430
B1
D
0.66
12.32
11.35
9.91
12.57
11.56
10.92
D1
D2
e
1.27
0.89
0.050
0.035
E
14.86
13.89
12.45
0.00
15.11
14.10
13.46
0.25
0.585
0.547
0.490
0.000
0.595
0.555
0.530
0.010
E1
E2
F
R
N
32
7
32
7
Nd
Ne
CP
9
9
0.10
0.004
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
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M27C405
Table 15. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.007
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
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M27C405
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