M27C801-150F1TR [STMICROELECTRONICS]
8 Mbit 1Mb x 8 UV EPROM and OTP EPROM; 8兆位的1Mb ×8 UV EPROM和OTP EPROM
| 型号： | M27C801-150F1TR |
| 厂家： | 
ST |
| 描述： | 8 Mbit 1Mb x 8 UV EPROM and OTP EPROM |
| 文件： | 总16页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27C801
8 Mbit (1Mb x 8) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 45ns
32
■ LOW POWER CONSUMPTION:
– Active Current 35mA at 5MHz
– Standby Current 100µA
32
1
1
FDIP32W (F)
PDIP32 (B)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 50µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 42h
TSOP32 (N)
8 x 20 mm
PLCC32 (K)
DESCRIPTION
The M27C801 is an 8 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for applica-
tions where fast turn-around and pattern experi-
mentation are important requirements and is
organized as 1,048,576 by 8 bits.
Figure 1. Logic Diagram
The FDIP32W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
V
CC
For applications where the content is programmed
only one time and erasure is not required, the
M27C801 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
20
8
A0-A19
Q0-Q7
E
M27C801
GV
PP
V
SS
AI01267
September 2000
1/16
M27C801
Figure 2A. DIP Connections
Figure 2B. PLCC Connections
A19
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A18
30 A17
29 A14
28 A13
27 A8
1 32
A7
A14
A13
A6
A5
A4
A6
A8
A5
26 A9
A9
A4
25 A11
M27C801
A3
A2
A1
A0
Q0
9
M27C801
25 A11
A3
24 GV
PP
23 A10
22
GV
PP
A2 10
A1 11
A0 12
Q0 13
Q1 14
Q2 15
A10
E
E
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
Q7
17
V
16
SS
AI01814
AI01268
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A19
Q0-Q7
E
Address Inputs
Data Outputs
Chip Enable
A11
A9
1
32
GV
PP
A10
GV
Output Enable / Program Supply
Supply Voltage
A8
E
PP
A13
A14
A17
A18
Q7
Q6
Q5
Q4
Q3
V
CC
V
SS
Ground
V
8
9
M27C801
(Normal)
25
24
CC
A19
V
SS
A16
A15
A12
A7
Q2
Q1
Q0
A0
A1
A2
A3
A6
A5
A4
16
17
AI01269
2/16
M27C801
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
(3)
T
A
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Ambient Operating Temperature
T
Temperature Under Bias
BIAS
T
STG
Storage Temperature
(2)
Input or Output Voltage (except A9)
V
IO
V
Supply Voltage
–2 to 7
–2 to 13.5
–2 to 14
V
V
V
CC
(2)
A9 Voltage
V
A9
V
Program Supply Voltage
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
GV
E
A9
X
Q7-Q0
Data Out
Hi-Z
pp
V
V
IL
Read
IL
V
V
IH
Output Disable
Program
X
IL
V
IL
Pulse
V
X
Data In
Hi-Z
PP
PP
V
IH
V
Program Inhibit
Standby
X
V
IH
X
X
Hi-Z
V
V
IL
V
Electronic Signature
Codes
IL
ID
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
Q0
0
Hex Data
V
IL
0
1
20h
42h
V
0
1
0
0
0
0
0
IH
3/16
M27C801
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns (10% to 90%)
0.4 to 2.4V
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
Input and Output Timing Ref. Voltages
0.8 and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
OUT
V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
dresses are stable, the address access time
(t
(t
) is equal to the delay from E to output
). Data is available at the output after a delay
AVQV
ELQV
The operating modes of the M27C801 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been sta-
levels except for GV and 12V on A9 for Elec-
PP
ble for at least t
-t
.
AVQV GLQV
tronic Signature and Margin Mode Set or Reset.
Standby Mode
Read Mode
The M27C801 has a standby mode which reduces
the supply current from 35mA to 100µA.
The M27C801 is placed in the standby mode by
applying a CMOS high signal to the E input. When
in the standby mode, the outputs are in a high im-
The M27C801 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
pedance state, independent of the GV input.
PP
4/16
M27C801
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 5V ± 10%)
A
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±10
±10
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
µA
E = V , GV = V ,
IL
PP
IL
I
Supply Current
35
mA
CC
I
= 0mA, f = 5MHz
OUT
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
E > V – 0.2V
CC
100
10
CC2
I
V
= V
PP CC
PP
V
Input Low Voltage
–0.3
2
0.8
IL
(2)
V
+ 1
Input High Voltage
V
V
V
V
V
IH
CC
V
I
= 2.1mA
= –1mA
Output Low Voltage
0.4
OL
OL
I
Output High Voltage TTL
Output High Voltage CMOS
3.6
OH
V
OH
I
= –100µA
V
– 0.7
CC
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 5V ± 10%)
A
CC
M27C801
-60
Test
Condition
(3)
Symbol
Alt
Parameter
Unit
-45
-70
Min Max Min Max Min Max
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
45
60
70
ns
AVQV
GV = V
PP
IL
t
t
GV = V
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
45
25
25
60
30
25
70
35
30
ns
ns
ns
ELQV
CE
PP
IL
t
t
E = V
GLQV
OE
IL
(2)
t
GV = V
0
0
0
0
0
0
t
t
DF
DF
PP
IL
EHQZ
(2)
t
E = V
Output Enable High to Output Hi-Z
25
25
30
ns
ns
IL
GHQZ
E = V ,
Address Transition to Output
Transition
IL
t
t
0
0
0
AXQX
OH
GV = V
PP
IL
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
PP.
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
5/16
M27C801
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 5V ± 10%)
A
CC
M27C801
-100/-120/-150 Unit
Symbol
Alt
Parameter
Test Condition
-80
Min
Max
80
Min
Max
100
100
t
t
E = V , GV = V
IL
Address Valid to Output Valid
ns
ns
AVQV
ACC
IL
PP
t
t
GV = V
Chip Enable Low to Output Valid
80
ELQV
CE
PP
IL
Output Enable Low to Output
Valid
t
t
E = V
40
35
35
50
40
40
ns
ns
ns
GLQV
OE
IL
(2)
t
t
GV = V
Chip Enable High to Output Hi-Z
0
0
0
0
t
t
DF
DF
PP
IL
EHQZ
Output Enable High to Output
Hi-Z
(2)
E = V
IL
GHQZ
Address Transition to Output
Transition
t
t
E = V , GV = V
IL PP IL
0
0
ns
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A19
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q7
AI01583B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
devices. The supply current, I , has three seg-
CC
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/16
M27C801
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
V
≤ V ≤ V
Input Leakage Current
Supply Current
LI
IL
IN
IH
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
–0.3
2
0.8
IL
V
IH
V
+ 0.5
CC
V
V
OL
I
= 2.1mA
= –1mA
0.4
V
OL
V
OH
I
OH
3.6
V
V
ID
11.5
12.5
V
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. MARGIN MODE AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
t
t
t
V
High to V High
A9HVPH
AS9
A9 PP
t
V
High to Chip Enable Low
PP
2
µs
VPHEL
VPS
AS10
AS10
AH10
t
t
t
t
V
A10
High to Chip Enable High (Set)
Low to Chip Enable High (Reset)
1
µs
A10HEH
t
V
A10
1
µs
A10LEH
t
Chip Enable Transition to V
Transition
1
µs
EXA10X
A10
t
t
Chip Enable Transition to V Transition
PP
2
µs
EXVPX
VPH
t
t
V Transition to V Transition
PP A9
2
µs
VPXA9X
AH9
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
Programming
light (UV EPROM). The M27C801 is in the pro-
gramming mode when V input is at 12.75V and
PP
When delivered (and after each erasure for UV
EPROM), all bits of the M27C801 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’ will be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ’0’ to a ’1’ is by die exposure to ultraviolet
E is pulsed to V . The data to be programmed is
IL
applied to 8 bits in parallel to the data output pins.
The levels required for the address and data in-
puts are TTL. V
is specified to be 6.25V ±
CC
0.25V.
7/16
M27C801
Figure 6. MARGIN MODE AC Waveforms
V
CC
A8
A9
tA9HVPH
tVPXA9X
GV
E
PP
tVPHEL
tEXVPX
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
(1)
Table 11. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
t
t
AS
Address Valid to Chip Enable Low
AVEL
t
t
Input Valid to Chip Enable Low
2
QVEL
DS
t
t
V
V
V
High to Chip Enable Low
High to Chip Enable Low
Rise Time
2
VCHEL
VCS
CC
PP
PP
t
t
2
VPHEL
OES
t
t
PRT
50
45
2
VPLVPH
t
t
PW
Chip Enable Program Pulse Width (Initial)
Chip Enable High to Input Transition
55
ELEH
t
t
DH
EHQX
t
t
Chip Enable High to V Transition
2
EHVPX
OEH
PP
t
t
V
PP
Low to Chip Enable Low
2
VPLEL
VR
t
t
DV
Chip Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Chip Enable High to Address Transition
1
ELQV
(2)
t
0
0
130
ns
ns
t
DFP
EHQZ
t
t
EHAX
AH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
8/16
M27C801
Figure 7. Programming and Verify Modes AC Waveforms
VALID
A0-A19
Q0-Q7
tAVEL
tQVEL
tEHAX
tEHQZ
DATA IN
DATA OUT
tEHQX
V
CC
tVCHEL
tVPHEL
tEHVPX
tELQV
GV
PP
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI01270
Figure 8. Programming Flowchart
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. This can
be achieved with STMicroelectronics M27C801
due to several design innovations to improve pro-
gramming efficiency and to provide adequate mar-
gin for reliability. Before starting the programming
the internal MARGIN MODE circuit is set in order
to guarantee that each cell is programmed with
enough margin. Then a sequence of 50µs pro-
gram pulses are applied to each byte until a cor-
rect verify occurs. No overprogram pulses are
applied since the verify in MARGIN MODE pro-
vides the necessary margin.
V
= 6.25V, V
= 12.75V
PP
CC
SET MARGIN MODE
n = 0
E = 50µs Pulse
NO
NO
++n
= 25
VERIFY
++ Addr
YES
YES
Program Inhibit
Programming of multiple M27C801s in parallel
with different data is also easily accomplished. Ex-
Last
Addr
NO
FAIL
cept for E, all like inputs including GV of the par-
PP
allel M27C801 may be common. A TTL low level
YES
pulse applied to a M27C801's E input, with V at
PP
RESET MARGIN MODE
12.75V, will program that M27C801. A high level E
input inhibits the other M27C801s from being pro-
grammed.
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
Program Verify
CC
CC
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
AI01271B
at V . Data should be verified with t
after the
IL
ELQV
falling edge of E.
9/16
M27C801
Electronic Signature
ERASURE OPERATION (applies to UV EPROM)
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C801. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C801. Two identifier bytes may then be se-
quenced from the device outputs by toggling ad-
The erasure characteristics of the M27C801 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range.
Research shows that constant exposure to room
level fluorescent lighting could erase a typical
M27C801 in about 3 years, while it would take ap-
proximately 1 week to cause erasure when ex-
posed to direct sunlight. If the M27C801 is to be
exposed to these types of lighting conditions for
extended periods of time, it is suggested that
opaque labels be put over the M27C801 window to
prevent unintentional erasure. The recommended
erasure procedure for the M27C801 is exposure to
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
dress line A0 from V to V . All other address
IL
IH
lines must be held at V during Electronic Signa-
IL
ture mode. Byte 0 (A0 = V ) represents the man-
IL
ufacturer code and byte 1 (A0 = V ) the device
IH
identifier code. For the STMicroelectronics
M27C801, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q7 to Q0.
2
of 30 W-sec/cm . The erasure time with this dos-
age is approximately 30 to 40 minutes using an ul-
2
traviolet lamp with 12000 µW/cm power rating.
The M27C801 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
10/16
M27C801
Table 12. Ordering Information Scheme
Example:
M27C801
-45
K
1
TR
Device Type
M27
Supply Voltage
C = 5V ±10%
Device Function
801 = 8Mbit (1Mb x8)
Speed
(1)
-45
= 45 ns
-60 = 60 ns
-70 = 70 ns
-80 = 80 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
Package
F = FDIP32W
B = PDIP32
K = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Options
X = Additional Burn-in
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 1. Revision History
Date
Revision Details
September 1998 First Issue
03/21/00
09/25/00
FDIP32W Package changed
AN620 Reference removed
11/16
M27C801
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
41.73
–
0.30
42.04
–
0.009
1.643
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
0.637
0.125
0.060
–
0.710
S
2.49
–
0.098
–
Ø
7.11
0.280
α
4°
11°
4°
11°
N
32
32
Figure 9. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
12/16
M27C801
Table 14. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
inches
Min
–
Symbol
Typ
Min
–
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
41.78
–
0.30
42.04
–
0.008
1.645
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.600
15.24
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.03
10°
0.600
0.125
0.070
0°
0.700
0.135
0.080
10°
S
α
N
32
32
Figure 10. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
13/16
M27C801
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
3.56
2.41
Typ
Min
Max
0.140
0.095
A
A1
A2
B
2.54
0.100
0.060
0.015
0.013
0.026
0.485
0.447
0.390
1.52
0.38
0.33
0.53
0.81
0.021
0.032
0.495
0.455
0.430
B1
D
0.66
12.32
11.35
9.91
12.57
11.56
10.92
D1
D2
e
1.27
0.89
0.050
0.035
E
14.86
13.89
12.45
0.00
15.11
14.10
13.46
0.25
0.585
0.547
0.490
0.000
0.595
0.555
0.530
0.010
E1
E2
F
R
N
32
7
32
7
Nd
Ne
CP
9
9
0.10
0.004
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
14/16
M27C801
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.20
0.17
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
15/16
M27C801
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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