M27V160-150XK1TR [STMICROELECTRONICS]
1MX16 OTPROM, 150ns, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44;型号: | M27V160-150XK1TR |
厂家: | ST |
描述: | 1MX16 OTPROM, 150ns, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44 可编程只读存储器 |
文件: | 总25页 (文件大小:274K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M27V160
16 Mbit (2Mb x8 or 1Mb x16)
Low Voltage UV EPROM and OTP EPROM
Features
■ 3V to 3.6V Low Voltage in Read Operation
■ Access Time: 100 ns
42
42
■ Byte-wide or Word-wide Configurable
■ 16 Mbit Mask ROM Replacement
1
1
FDIP42W (F)
PDIP42 (B)
■ Low Power Consumption
– Active Current: 30 mA at 8 MHz
– Standby Current: 60 µA
■ Programming Voltage: 12.5V ± 0.25V
■ Programming Time: 50 µs/word
42
1
■ Electronic Signature
– Manufacturer Code: 20h
– Device Code: B1h
SDIP42 (S)
■ ECOPACK® packages available
44
1
PLCC44 (K)
SO44 (M)
April 2006
Rev 5
1/25
www.st.com
1
Contents
M27V160
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Two-line output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
System considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Presto III programming algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Erasure operation (applies to UV EPROM) . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
4
5
5.1
5.2
5.3
5.4
5.5
42-pin Ceramic Frit-seal DIP with window (FDIP42WB) . . . . . . . . . . . . . 18
42-pin Plastic DIP, 600 mils width (PDIP42) . . . . . . . . . . . . . . . . . . . . . . . 19
42-lead Shrink Plastic DIP, 600 mils width (SDIP42) . . . . . . . . . . . . . . . . 20
44-lead Square Plastic Leaded Chip Carrier (PLCC44) . . . . . . . . . . . . . . 21
44-lead Plastic Small Outline, 525 mils body width (SO44) . . . . . . . . . . . 22
6
7
Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
M27V160
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Mode DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Programming Mode DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programming Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FDIP42WB package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PDIP42 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SDIP42 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PLCC44 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO44 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
List of figures
M27V160
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Word-Wide Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Byte-Wide Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. BYTE Transition AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Programming and Verify Modes AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. FDIP42WB package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. PDIP42 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. SDIP42 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. PLCC44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. SO44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/25
M27V160
Summary description
1
Summary description
The M27V160 is a low voltage 16 Mbit EPROM offered in the two ranges UV (ultra violet
erase) and OTP (one time programmable). It is ideally suited for microprocessor systems
requiring large data or program storage. It is organised as either 2 Mbit words of 8 bit or 1
Mbit words of 16 bit. The pin-out is compatible with a 16 Mbit Mask ROM.
The M27V160 operates in the read mode with a supply voltage as low as 3V. The decrease
in operating power allows either a reduction of the size of the battery or an increase in the
time between battery recharges.
The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the
user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be
written rapidly to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not
required, the M27V160 is offered in PDIP42, SDIP42, PLCC44 and SO44 packages.
In order to meet environmental requirements, ST offers the M27V160 in ECOPACK®
packages. ECOPACK packages are Lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK® specifications are available at: www.st.com.
See Figure 1: Logic Diagram and Table 1: Signal descriptions for a brief overview of the
signals connected to this device.
Figure 1.
Logic Diagram
V
CC
20
Q15A–1
Q0-Q14
A0-A19
15
E
M27V160
G
BYTEV
PP
V
SS
AI01898
5/26
Summary description
Table 1.
M27V160
Signal descriptions
Signal
Description
A0-A19
Q0-Q7
Q8-Q14
Q15A–1
E
Address Inputs
Data Outputs
Data Outputs
Data Output / Address Input
Chip Enable
G
Output Enable
BYTEVPP
VCC
Byte Mode / Program Supply
Supply Voltage
VSS
Ground
NC
Not Connected Internally
Figure 2.
DIP Connections
A18
A17
A7
1
2
3
4
5
6
7
8
9
42 A19
41 A8
40 A9
A6
39 A10
38 A11
37 A12
36 A13
35 A14
34 A15
33 A16
32 BYTEV
A5
A4
A3
A2
A1
A0 10
M27V160
E
11
12
13
PP
V
31
V
SS
SS
G
30 Q15A-1
29 Q7
Q0 14
Q8 15
Q1 16
Q9 17
Q2 18
28 Q14
27 Q6
26 Q13
25 Q5
Q10 19
Q3 20
24 Q12
23 Q4
Q11 21
22
V
CC
AI01899
6/26
M27V160
Summary description
Figure 3.
SO Connections
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
2
A19
A8
3
4
A9
5
A10
A11
A12
A13
A14
A15
A16
BYTEV
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M27V160
PP
V
V
SS
Q15A-1
SS
G
Q0
Q8
Q7
Q14
Q6
Q1
Q9
Q13
Q5
Q2
Q10
Q3
Q12
Q4
Q11
V
CC
AI01900
Figure 4.
PLCC Connections
1 44
A4
A3
A2
A1
A0
A12
A13
A14
A15
A16
E
12
M27V160
34 BYTEV
PP
V
V
SS
G
SS
Q15A–1
Q7
Q0
Q8
Q1
Q14
Q6
23
AI04829
7/26
Device description
M27V160
2
Device description
Table 2 lists the operating modes of the M27V160. A single power supply is required in the
read mode. All inputs are TTL compatible except for V and 12V on A9 for the Electronic
PP
Signature.
(1)
Table 2.
Operating Modes
Mode
E
G
BYTEVPP
A9
Q15A–1
Q14-Q8
Q7-Q0
Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIH
X
VIH
VIL
VIL
X
X
X
Data Out Data Out Data Out
VIH
VIL
Hi-Z
Hi-Z
Data Out
Data Out
Hi-Z
VIL
X
VIL
X
Hi-Z
Hi-Z
VIL Pulse
VIH
VPP
VPP
VPP
X
X
Data In
Data In
Data In
Verify
X
Data Out Data Out Data Out
Program Inhibit
Standby
VIH
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VIH
X
Electronic Signature
VIL
VIL
VIH
VID
Code
Codes
Codes
1. X = VIH or VIL, VID = 12V ± 0.5V.
2.1
Read mode
The M27V160 has two organisations, Word-wide and Byte-wide. The organisation is
selected by the signal level on the BYTEV pin. When BYTEV is at V the Word-wide
PP
PP
IH
organisation is selected and the Q15A–1 pin is used for Q15 Data Output. When the
BYTEV pin is at V the Byte-wide organisation is selected and the Q15A–1 pin is used for
PP
IL
the Address Input A–1. When the memory is logically regarded as 16 bit wide, but read in
the Byte-wide organisation, then with A–1 at V the lower 8 bits of the 16 bit data are
IL
selected and with A–1 at V the upper 8 bits of the 16 bit data are selected.
IH
The M27V160 has two control functions, both of which must be logically active in order to
obtain data at the outputs. In addition the Word-wide or Byte- wide organisation must be
selected.
Chip Enable (E) is the power control and should be used for device selection. Output Enable
(G) is the output control and should be used to gate data to the output pins independent of
device selection. Assuming that the addresses are stable, the address access time (t
)
AVQV
is equal to the delay from E to output (t
). Data is available at the output after a delay of
ELQV
t
from the falling edge of G, assuming that E has been low and the addresses have
GLQV
been stable for at least t
-t
.
AVQV GLQV
2.2
Standby mode
The M27V160 has a standby mode which reduces the active current from 20mA to 20µA
with low voltage operation V ≤ 3.6V, see Read Mode DC Characteristics table for
CC
details.The M27V160 is placed in the standby mode by applying a CMOS high signal to the
8/26
M27V160
Device description
E input. When in the standby mode, the outputs are in a high impedance state, independent
of the G input.
2.3
Two-line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
■
■
the lowest possible memory power dissipation,
complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4
System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the supplies to the devices. The supply current I has three segments of
CC
importance to the system designer: the standby current, the active current and the transient
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device outputs.
The associated transient voltage peaks can be suppressed by complying with the two line
output control and by properly selected decoupling capacitors. It is recommended that a
0.1µF ceramic capacitor is used on every device between V and V . This should be a
CC
SS
high frequency type of low inherent inductance and should be placed as close as possible to
the device. In addition, a 4.7µF electrolytic capacitor should be used between V and V
CC
SS
for every eight devices. This capacitor should be mounted near the power supply connection
point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive
effects of PCB traces.
2.5
Programming
The M27V160 has been designed to be fully compatible with the M27C160. As a result the
M27V160 can be programmed as the M27C160 on the same programming equipments
applying 12.75V on V and 6.25V on V by the use of the same PRESTO III algorithm.
PP
CC
When delivered (and after each erasure for UV EPROM), all bits of the M27V160 are in the
'1' state. Data is introduced by selectively programming '0's to the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27V160 is in the programming mode when V input is at 12.5V, G is at V and E is
pp
IH
pulsed to V . The data to be programmed is applied to 16 bits in parallel to the data output
IL
pins. The levels required for the address and data inputs are TTL. V is specified to be
CC
6.25V ± 0.25V.
9/26
Device description
M27V160
2.6
Presto III programming algorithm
The Presto III Programming Algorithm allows the whole array to be programed with a
guaranteed margin in a typical time of 52.5 seconds. Programming with Presto III consists of
applying a sequence of 50µs program pulses to each word until a correct Verify occurs (see
Figure 5.).
During programing and verify operation a Margin Mode circuit is automatically activated to
guarantee that each cell is programed with enough margin. No overprogram pulse is applied
since the Verify in Margin Mode at V much higher than 3.6V provides the necessary
CC
margin to each programmed cell.
Figure 5.
Programming Flowchart
V
= 6.25V, V = 12.5V
PP
CC
n = 0
E = 50µs Pulse
NO
NO
++n
VERIFY
YES
++ Addr
= 25
YES
Last
Addr
NO
FAIL
YES
CHECK ALL WORDS
BYTEV
1st: V
=V
IH
PP
CC
= 5V
= 3V
2nd: V
CC
AI00901B
2.7
2.8
Program Inhibit
Programming of multiple M27V160s in parallel with different data is also easily
accomplished. Except for E, all like inputs including G of the parallel M27V160 may be
common. A TTL low level pulse applied to a M27V160's E input and V at 12.5V, will
program that M27V160. A high level E input inhibits the other M27V160s from being
programmed.
PP
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were
correctly programmed. The verify is accomplished with E at V and G at V , V at 12.5V
IH
IL
PP
and V at 6.25V.
CC
10/26
M27V160
Device description
2.9
Electronic Signature
The Electronic Signature (ES) mode allows the reading out of a binary code from an
EPROM that will identify its manufacturer and type. This mode is intended for use by
programming equipment to automatically match the device to be programmed with its
corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C
ambient temperature range that is required when programming the M27V160. To activate
the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of
the M27V160, with V = V = 5V.
PP
CC
Two identifier bytes may then be sequenced from the device outputs by toggling address line
A0 from V to V . All other address lines must be held at V during Electronic Signature
IL
IH
IL
mode.
Byte 0 (A0 = V ) represents the manufacturer code and byte 1 (A0 = V ) the device
IL
IH
identifier code. For the STMicroelectronics M27V160, these two identifier bytes are given in
Table 3 and can be read-out on outputs Q7 to Q0. Note that the M27V160 and M27C160
have the same identifier bytes.
Table 3.
Electronic Signature
Q15 Q14 Q13 Q12 Q11 Q10
Q9
Q8
Hex
Data
Identifier
A0
and and and and and and and and
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Manufacturer’s Code
Device Code
VIL
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
1
20h
B1h
VIH
2.10
Erasure operation (applies to UV EPROM)
The erasure characteristics of the M27V160 is such that erasure begins when the cells are
exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted
that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å
range. Research shows that constant exposure to room level fluorescent lighting could
erase a typical M27V160 in about 3 years, while it would take approximately 1 week to
cause erasure when exposed to direct sunlight. If the M27V160 is to be exposed to these
types of lighting conditions for extended periods of time, it is suggested that opaque labels
be put over the M27V160 window to prevent unintentional erasure. The recommended
erasure procedure for M27V160 is exposure to short wave ultraviolet light which has a
wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure
2
should be a minimum of 30 W-sec/cm . The erasure time with this dosage is approximately
2
30 to 40 minutes using an ultraviolet lamp with 12000 µW/cm power rating. The M27V160
should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be removed before erasure.
11/26
Maximum ratings
M27V160
3
Maximum ratings
(1)
Table 4.
Symbol
Absolute Maximum Ratings
Parameter
Value
Unit
TA
Ambient Operating Temperature (2)
Temperature Under Bias
Storage Temperature
–40 to 125
–50 to 125
–65 to 150
–2 to 7
°C
°C
°C
V
TBIAS
TSTG
(3)
VIO
Input or Output Voltage (except A9)
Supply Voltage
VCC
–2 to 7
V
(3)
VA9
A9 Voltage
–2 to 13.5
–2 to 14
V
VPP
Program Supply Voltage
V
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute
Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents.
2. Depends on range.
3. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than
20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less
than 20ns.
12/26
M27V160
DC and AC parameters
4
DC and AC parameters
T = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%; V = V
A
CC
PP
CC
(1)
Table 5.
Symbol
Read Mode DC Characteristics
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
0V ≤ VIN ≤ VCC
±1
µA
µA
ILO
0V ≤ VOUT ≤ VCC
±10
E = VIL, G = VIL, IOUT = 0mA,
30
mA
f = 8MHz, VCC ≤ 3.6V
ICC
Supply Current
E = VIL, G = VIL, IOUT = 0mA,
20
1
mA
mA
µA
f = 5MHz, VCC ≤ 3.6V
ICC1
ICC2
Supply Current (Standby) TTL
E = VIH
E > VCC – 0.2V, VCC ≤ 3.6V
VPP = VCC
Supply Current (Standby)
CMOS
60
IPP
VIL
Program Current
10
µA
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
–0.3
0.2VCC
(2)
VIH
0.7VCC VCC + 1
V
VOL
VOH
IOL = 2.1mA
0.4
V
IOH = –400µA
2.4
V
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Maximum DC voltage on Output is VCC +0.5V.
.
T = 25 °C; V = 6.25V ± 0.25V; V = 12.5V ± 0.25V
A
CC
PP
(1)
Table 6.
Symbol
Programming Mode DC Characteristics
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
Supply Current
0 ≤ VIN ≤ VCC
±1
50
50
0.8
µA
mA
mA
V
ICC
IPP
VIL
Program Current
Input Low Voltage
E = VIL
–0.3
2.4
VCC
0.5
+
VIH
Input High Voltage
V
VOL
VOH
VID
Output Low Voltage
Output High Voltage TTL
A9 Voltage
IOL = 2.1mA
0.4
V
V
V
IOH = –2.5mA
3.6
11.5
12.5
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
13/26
DC and AC parameters
Table 7.
M27V160
AC Measurement Conditions
Parameter
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
0 to 3V
1.5V
≤ 20ns
Input Pulse Voltages
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
T = 25 °C, f = 1 MHz
A
(1)
Table 8.
Symbol
Capacitance
Parameter
Test Condition
Min.
Max.
Unit
Input Capacitance (except BYTEVPP
)
VIN = 0V
VIN = 0V
10
120
12
pF
pF
pF
CIN
Input Capacitance (BYTEVPP
Output Capacitance
)
COUT
VOUT = 0V
1. Sampled only, not 100% tested.
Figure 6.
AC Testing Input Output Waveform
High Speed
3V
0V
1.5V
Standard
2.4V
2.0V
0.8V
0.4V
AI01822
Figure 7.
AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
OUT
C
L
C
C
C
= 30pF for High Speed
L
= 100pF for Standard
L
includes JIG capacitance
L
AI01823B
14/26
M27V160
Table 9.
DC and AC parameters
T = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%; V = V
A
CC
PP
CC
(1)
Read Mode AC Characteristics
M27V160
-120
Min. Max. Min. Max. Min. Max.
Symbol Alt
Parameter
Test Condition
-100 (2)
-150
Unit
tAVQV
tBHQV
tACC Address Valid to Output Valid
tST BYTE High to Output Valid
E = VIL, G = VIL
E = VIL, G = VIL
100
100
120
120
150
150
ns
ns
Chip Enable Low to Output
Valid
tELQV
tGLQV
tCE
G = VIL
100
120
150
ns
Output Enable Low to Output
Valid
tOE
E = VIL
E = VIL, G = VIL
G = VIL
50
45
45
60
50
50
60
50
50
ns
ns
ns
(3)
tBLQZ
tSTD BYTE Low to Output Hi-Z
Chip Enable High to Output Hi-
Z
(3)
(3)
tEHQZ
tDF
0
0
0
0
0
0
Output Enable High to Output
Hi-Z
tGHQZ
tDF
E = VIL
45
50
50
ns
Address Transition to Output
Transition
tAXQX
tBLQX
tOH
E = VIL, G = VIL
E = VIL, G = VIL
5
5
5
5
5
5
ns
ns
tOH BYTE Low to Output Transition
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Speed obtained with High Speed measurement conditions.
3. Sampled only, not 100% tested.
.
T = 25 °C; V = 6.25V ± 0.25V; V = 12.5V ± 0.25V
A
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
Symbol
Alt
Parameter
Test Condition
Min.
Max.
Unit
tAVEL
tQVEL
tVPHAV
tVCHAV
tELEH
tEHQX
tQXGL
tGLQV
tAS
tDS
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
VPP High to Address Valid
2
2
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
tVPS
tVCS
tPW
tDH
2
VCC High to Address Valid
2
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
45
2
55
tOES
tOE
tDFP
tAH
2
120
130
(2)
tGHQZ
0
0
tGHAX
Output Enable High to Address Transition
1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Sampled only, not 100% tested.
.
15/26
DC and AC parameters
M27V160
Figure 8.
Word-Wide Read Mode AC Waveforms
VALID
tAVQV
VALID
A0-A19
E
tAXQX
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q15
AI00741B
Note:
BYTEV = V .
PP IH
Figure 9.
Byte-Wide Read Mode AC Waveforms
VALID
VALID
A–1,A0-A19
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q7
AI00742B
Note:
BYTEV = V .
PP IL
16/26
M27V160
DC and AC parameters
Figure 10. BYTE Transition AC Waveforms
A0-A19
VALID
A–1
VALID
tAVQV
tAXQX
BYTEV
Q0-Q7
PP
tBHQV
DATA OUT
DATA OUT
tBLQX
Hi-Z
Q8-Q15
tBLQZ
AI00743C
Note:
Chip Enable (E) and Output Enable (G) = V .
IL
Figure 11. Programming and Verify Modes AC Waveforms
A0-A19
Q0-Q15
VALID
tAVEL
DATA IN
tQVEL
DATA OUT
tEHQX
BYTEV
PP
tVPHAV
tVCHAV
tGLQV
tGHQZ
tGHAX
V
E
CC
tELEH
tQXGL
G
PROGRAM
VERIFY
AI00744
17/26
Package mechanical data
M27V160
5
Package mechanical data
5.1
42-pin Ceramic Frit-seal DIP with window (FDIP42WB)
Figure 12. FDIP42WB package outline
A2
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
K
E1
E
K1
FDIPW-C
Table 11. FDIP42WB package mechanical data
millimeters
Symbol
inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
B
5.71
1.78
5.08
0.55
1.52
0.31
54.81
–
0.225
0.070
0.200
0.022
0.060
0.012
2.158
–
0.50
3.90
0.40
1.27
0.22
0.020
0.154
0.016
0.050
0.009
B1
C
D
D2
E
–
50.80
15.24
–
2.000
0.600
E1
e
14.50
2.29
15.40
16.17
9.32
11.30
3.18
1.52
4°
14.90
2.79
15.80
18.32
9.47
11.55
4.10
2.49
15°
0.571
0.090
0.606
0.637
0.367
0.445
0.125
0.060
4°
0.587
0.110
0.622
0.721
0.373
0.455
0.161
0.098
15°
eA
eB
K
K1
L
S
α
N
42
42
18/26
M27V160
Package mechanical data
5.2
42-pin Plastic DIP, 600 mils width (PDIP42)
Figure 13. PDIP42 package outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Table 12. PDIP42 package mechanical data
millimeters
Symbol
inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
B
–
0.25
3.56
0.38
1.27
0.20
52.20
–
5.08
–
–
0.200
–
0.010
4.06
0.53
1.65
0.36
52.71
–
0.140
0.015
0.050
0.008
2.055
–
0.160
0.021
0.065
0.014
2.075
–
B1
C
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
–
14.99
–
–
–
15.24
3.18
0.86
0°
17.78
3.43
1.37
10°
0.600
0.125
0.034
0°
0.700
0.135
0.054
10°
S
α
N
42
42
19/26
Package mechanical data
M27V160
5.3
42-lead Shrink Plastic DIP, 600 mils width (SDIP42)
Figure 14. SDIP42 package outline
A2
A1
A
L
c
b2
b
e
eA
eB
D2
D
S
N
1
E1
E
SDIP
Table 13. SDIP42 package mechanical data
millimeters
Symbol
inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
b
5.08
0.200
0.51
3.05
0.38
0.89
0.23
36.58
–
0.020
0.120
0.015
0.035
0.009
1.440
–
3.81
0.46
1.02
0.25
36.83
1.78
4.57
0.56
1.14
0.38
37.08
–
0.150
0.018
0.040
0.010
1.450
0.070
0.180
0.022
0.045
0.015
1.460
–
b2
c
D
e
E
15.24
12.70
16.00
14.48
0.600
0.500
0.630
0.570
E1
eA
eB
L
13.72
15.24
0.540
0.600
18.54
3.56
0.730
0.140
2.54
3.30
0.64
42
0.100
0.130
0.025
42
S
N
20/26
M27V160
Package mechanical data
5.4
44-lead Square Plastic Leaded Chip Carrier (PLCC44)
Figure 15. PLCC44 package outline
D
A1
c
D1
1
N
B1
e
E2
E3
E1 E
B
D3
D2
A2
A
CP
PLCC-B
Table 14. PLCC44 package mechanical data
millimeters
Symbol
inches
Typ.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
B
4.200
2.290
3.650
0.331
0.661
4.570
3.040
3.700
0.533
0.812
0.101
0.1654
0.0902
0.1437
0.0130
0.0260
0.1799
0.1197
0.1457
0.0210
0.0320
0.0040
B1
CP
c
0.510
0.0201
0.5000
D
17.400
16.510
14.990
–
17.650
16.662
16.000
–
0.6850
0.6500
0.5902
–
0.6949
0.6560
0.6299
–
D1
D2
D3
E
12.700
17.400
16.510
14.990
–
17.650
16.660
16.000
–
0.6850
0.6500
0.5902
–
0.6949
0.6559
0.6299
–
E1
E2
E3
e
12.700
1.270
44
0.5000
0.0500
44
–
–
–
–
N
21/26
Package mechanical data
M27V160
5.5
44-lead Plastic Small Outline, 525 mils body width (SO44)
Figure 16. SO44 package outline
A2
A
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Table 15. SO44 package mechanical data
millimeters
Symbol
inches
Typ.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
2.80
0.1102
0.10
2.20
0.35
0.10
0.0039
0.0866
0.0138
0.0039
2.30
0.40
0.15
2.40
0.50
0.20
0.08
28.40
13.50
16.25
–
0.0906
0.0157
0.0059
0.0945
0.0197
0.0079
0.0030
1.1181
0.5315
0.6398
–
C
CP
D
28.00
13.20
15.75
–
28.20
13.30
16.00
1.27
1.1024
0.5197
0.6201
–
1.1102
0.5236
0.6299
0.0500
0.0315
E
EH
e
L
0.80
α
8°
8°
N
44
44
22/26
M27V160
Part Numbering
6
Part Numbering
Table 16. Ordering Information Scheme
Example:
M27V160
-100
X
M
1
Device Type
M27
Supply Voltage
V = 3V to 3.6V
Device Function
160 = 16 Mbit (2Mb x 8 or 1Mb x 16)
Speed
-100 (1)= 100 ns
-120 = 120 ns
-150 = 150 ns
VCC Tolerance
blank = 3.3V ± 10%
X = 3.3V ± 5%
Package
F = FDIP42W (2)
B = PDIP42
S = SDIP42
K = PLCC44
M = SO44 (2)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
1. High Speed, see AC Characteristics section for further information.
2. Packages option available on request. Please contact STMicroelectronics local Sales Office.
For a list of available options (Speed, Package, etc...) or for further information on any
aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
23/26
Revision history
M27V160
7
Revision history
Table 17. Document revision history
Date
Revision
Changes
10-Mar-2000
23-Apr-2001
19-Jul-2001
21-Mar-2002
1
2
3
4
First Issue
PLCC44 package added
SDIP42 package added
SO44 package mechanical and data clarified
Converted to new template. Added ECOPACK® information.
Removed “On-board Programming” section. Removed Tape & Reel
Packing option.
12-Apr-2006
5
24/26
M27V160
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