M27V201-120F1 [STMICROELECTRONICS]
256KX8 UVPROM, 120ns, CDIP32, WINDOWED, FRIT SEALED, CERAMIC, DIP-32;
| 型号： | M27V201-120F1 |
| 厂家： | 
ST |
| 描述： | 256KX8 UVPROM, 120ns, CDIP32, WINDOWED, FRIT SEALED, CERAMIC, DIP-32 可编程只读存储器 CD |
| 文件： | 总15页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27V201
2 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM
NOT FOR NEW DESIGN
■ M27V201 is replaced by the M27W201
■ 3V to 3.6V LOW VOLTAGE in READ
OPERATION
■ ACCESS TIME: 120ns
32
32
■ LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 20µA
1
1
FDIP32W (F)
PDIP32 (B)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
DESCRIPTION
The M27V201 is a low voltage 2 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organised as 262,144 by 8
bits.
Fure 1. Logic Diagram
The M27V201 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
V
V
PP
CC
The FDIP32W (window ceramc frit-seal package)
has a transparent lid which allow the user to ex-
pose the chip to ultraiolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
18
8
A0-A17
Q0-Q7
P
E
M27V201
For applications where the content is programmed
only otime and erasure is not required, the
M27V201 is offered in PDIP32, PLCC32 and
TOP32 (8 x 20 mm) packages.
G
V
SS
AI00693B
July 2000
1/15
This is information on a product still in production but not recommended for new designs.
M27V201
Figure 2A. DIP Connections
Figure 2B. LCC Connections
V
1
2
3
4
5
6
7
8
9
32
31
V
P
PP
CC
A16
A15
A12
A7
30 A17
29 A14
28 A13
27 A8
1 32
A7
A14
A13
A8
A6
A5
A4
A6
A5
26 A9
A9
A4
25 A11
M27V201
A3
A2
A1
A0
Q0
9
M27V201
25 A11
G
A3
24
23 A10
22
G
A2 10
A1 11
A0 12
Q0 13
Q1 14
Q2 15
A10
E
E
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
Q7
17
V
16
SS
AI00694
AI01901
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A17
Address Inputs
Q0-Q7
Data Outputs
Chip Enable
Output Enable
Program
A11
A9
1
32
G
E
G
P
A10
E
A8
A13
A14
A17
P
Q7
Q6
Q5
Q4
Q3
V
PP
Program Supply
Supply Voltage
Ground
V
8
9
M27V201
(Normal)
25
24
CC
V
CC
V
V
SS
PP
V
SS
A16
Q2
Q1
Q0
A0
A1
A2
A3
A15
A12
A7
A6
A5
A4
16
17
AI01154B
2/15
M27V201
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
(3)
T
A
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Ambient Operating Temperature
T
Temperature Under Bias
BIAS
T
STG
Storage Temperature
(2)
Input or Output Voltage (except A9)
V
IO
V
Supply Voltage
–2 to 7
–2 to 13.5
–2 to 14
V
V
V
CC
(2)
A9 Voltage
V
A9
V
Program Supply Voltage
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V +2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
V
E
G
P
A9
X
Q7-Q0
Data Out
Hi-Z
PP
V
V
V
V
or V
or V
Read
X
IL
IL
IL
IL
IL
IH
IH
CC
SS
SS
V
V
V
V
V
V
Output Disable
Program
X
X
CC
V
Pulse
V
X
Data In
Data Out
Hi-Z
IL
PP
PP
PP
V
IL
V
IH
V
Verify
X
V
Program Inhibit
Standby
X
X
X
IH
IH
V
V
or V
CC SS
X
X
X
Hi-Z
V
V
IL
V
IH
V
ID
V
CC
Electronic Signature
Codes
IL
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
Hex Data
20h
V
IL
0
1
V
0
1
1
0
0
0
0
61h
IH
3/15
M27V201
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
IN
C
V
OUT
12
pF
OUT
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
(t
(t
of t
) is equal to the delay from E to output
). Data is available at the output after a delay
AVQV
ELQV
The operating modes of the M27V201 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been sta-
ble for at least t
-t
.
AVQV GLQV
levels except for V and 12V on A9 for Electronic
PP
Signature.
Standby Mode
Read Mode
The M27V201 has a standby mode which reduces
the active current from 15mA to 20µA with low volt-
The M27V201 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
age operation V
≤ 3.6V, see Read Mode DC
CC
Characteristics table for details.The M27V201 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
4/15
M27V201
(1)
Table 7. Read Mode DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%; V = V )
CC
CC
PP
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±10
±10
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
µA
E = V , G = V , I
= 0mA,
IL
IL OUT
I
Supply Current
15
mA
CC
f = 5MHz, V ≤ 3.6V
CC
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
20
10
0.8
E > V – 0.2V, V ≤ 3.6V
CC2
CC
CC
I
V
= V
PP CC
PP
V
IL
Input Low Voltage
–0.3
2
(2)
V
+ 1
Input High Voltage
V
V
CC
IH
V
I
= 2.1mA
= –400µA
= –100µA
Output Low Voltage
0.4
V
V
V
OL
OL
OH
OH
I
I
Output High Voltage TTL
Output High Voltage CMOS
2.4
V
OH
V
–0.7V
CC
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85°; V = 3.3V ± 10%; V = V
)
A
CC
PP
CC
M27V201
Unit
Symbol
Alt
Parameter
Test Condition
-120
-150
Min
Max
Min
Max
t
t
E = V , G = V
Address Valid to Output Valid
120
120
50
150
150
60
ns
ns
ns
ns
AVQV
ACC
IL
IL
t
t
G = V
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
ELQV
CE
IL
t
t
E = V
G = V
E = V
GLQV
OE
IL
(2)
t
0
0
40
0
0
50
t
DF
DF
IL
IL
EHQZ
GHQZ
t
(2)
t
Output Enable High to Output Hi-Z
40
50
ns
ns
t
Address Transition to Output
Transition
t
E = V , G = V
IL IL
0
0
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Two Line Output Control
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
5/15
M27V201
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85 °C; V = 3.3V ± 10%; V = V
)
CC
A
CC
PP
M27V201
Unit
Symbol
Alt
Parameter
Test Condition
-180
-200
Min
Max
Min
Max
200
200
90
t
t
E = V , G = V
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
180
180
80
ns
ns
ns
AVQV
ACC
IL
IL
t
t
G = V
IL
ELQV
CE
t
t
E = V
IL
GLQV
OE
(2)
t
G = V
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
0
0
50
50
0
0
70
70
ns
ns
t
DF
DF
IL
EHQZ
(2)
t
E = V
t
IL
GHQZ
Address Transition to Output
Transition
t
t
E = V , G = V
IL IL
0
0
ns
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A17
tAVQV
tAXQX
E
tEHQZ
tGHQZ
G
tELQV
Hi-Z
Q0-Q7
AI00719B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
and V . This should be a high frequency capaci-
SS
devices. The supply current, I , has three seg-
CC
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
used between V and V for every eight devic-
CC
SS
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/15
M27V201
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
Input Leakage Current
Supply Current
0 ≤ V ≤ V
LI
IN
CC
I
CC
I
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
PP
IL
V
IL
–0.3
2
0.8
V
V
V
+ 0.5
V
IH
CC
I
= 2.1mA
OL
0.4
V
OL
V
I
= –400µA
OH
2.4
V
OH
V
11.5
12.5
V
ID
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
t
t
t
Address Valid to Program Low
Input Valid to Program Low
AVPL
AS
t
2
QVPL
DS
t
t
t
V
V
High to Program Low
High to Program Low
2
VPHPL
VPS
PP
t
2
VCHPL
VCS
CES
CC
t
t
Chip Enable Low to Program Low
Program Pulse Width
2
ELPL
t
t
95
2
105
PLPH
PW
t
t
DH
Program High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
PHQX
t
t
2
QXGL
OES
t
t
100
130
GLQV
OE
(2)
t
0
0
ns
ns
t
DFP
GHQZ
Output Enable High to Address
Transition
t
t
GHAX
AH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
though only ’0’s will be programmed, both ’1’s and
’0’s can be present in the data word. The only way
to change a ’0’ to a ’1’ is by die exposure to ultravi-
olet light (UV EPROM). The M27V201 is in the
The M27V201 has been designed to be fully com-
patible with the M27C2001 and has the same elec-
tronic signature. As a result the M27V201 can be
programmed as the M27C2001 on the same pro-
gramming equipments by applying 12.75V on V
and 6.25V on V
TO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V201
are in the ’1’ state.Data is introduced by selectively
programming ’0’s into the desired bit locations. Al-
programming mode when V input is at 12.75V,
PP
E is at V and P is pulsed to V . The data to be
IL
IL
PP
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
by the use of the same PRES-
CC
dress and data inputs are TTL. V is specified to
CC
be 6.25V ± 0.25V.
7/15
M27V201
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A17
tAVPL
Q0-Q7
DATA IN
DATA OUT
tQVPL
tVPHPL
tVCHPL
tELPL
tPHQX
V
PP
tGLQV
tGHQZ
tGHAX
V
CC
E
P
tPLPH
tQXGL
G
PROGRAM
VERIFY
AI00720
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
P = 100µs Pulse
since the verify in MARGIN MODE at V
higher than 3.6V provides the necessary margin to
each programmed cell.
much
CC
NO
NO
++n
= 25
VERIFY
YES
++ Addr
Program Inhibit
YES
Programming of multiple M27V201s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V201 may be common. A TTL low level pulse
applied to a M27V201's P input, with E low and
Last
NO
FAIL
Addr
YES
V
at 12.75V, will program that M27V201. A high
PP
level E input inhibits the other M27V201s from be-
ing programmed.
Program Verify
CHECK ALL BYTES
1st: V
= 6V
CC
CC
2nd: V
= 4.2V
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
AI00715C
and G at V , P at V , V at 12.75V and V at
IL
IH
PP
CC
6.25V.
8/15
M27V201
Electronic Signature
ERASURE OPERATION (applies to UV EPROM)
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27V201. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V201 with
The erasure characteristics of the M27V201 are
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Data
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27V201 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V201 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V201 window to prevent unintentional era-
sure. The recommended erasure procedure for
the M27V201 is exposure to short wave ultraviolet
light which has wavelength of 2537 Å. The inte-
grated dose (i.e. UV intensity x exposure time) for
V
= V = 5V. Two identifier bytes may then be
PP
CC
sequenced from the device outputs by toggling ad-
dress line A0 from V to V . All other address
IL
IH
lines must be held at V during Electronic Signa-
IL
ture mode. Byte 0 (A0 = V ) represents the man-
IL
ufacturer code and byte 1 (A0 = V ) the device
IH
identifier code. For the STMicroelectronics
M27V201, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q7 to Q0.
Note that the M27V201 and M27C2001 have the
same identifier bytes.
2
erasure should be a minimum of 15 W-sec/cm .
The erasure time with this dosage is approximate-
ly 15 to 20 minutes using an ultraviolet lamp with
2
12000µW/cm power rating. The M27V201 should
be placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before era-
sure.
9/15
M27V201
Table 11. Ordering Information Scheme
Example:
M27V201
-120 K
1
TR
Device Type
M27
Supply Voltage
V = 3V to 3.6V
Device Function
201 = 2 Mbit (256Kb x 8)
Speed
-120 = 120 ns
-150 = 150 ns
-180 = 180 ns
-200 = 200 ns
Package
F = FDIP32W
B = PDIP32
K = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Options
TR = Tape & Reel Packing
M27V201 is replaced by the M27W201
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
10/15
M27V201
Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
41.73
–
0.30
42.04
–
0.009
1.643
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
0.637
0.125
0.060
–
0.710
S
2.49
–
0.098
–
7.11
0.280
α
4°
11°
4°
11°
N
32
32
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
11/15
M27V201
Table 13. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm
Min
–
inches
Min
–
Symb
Typ
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
41.78
–
0.30
42.04
–
0.008
1.645
–
0.012
1.655
–
D
D2
E
38.10
15.24
1.500
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.600
15.24
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.03
10°
0.600
0.125
0.070
0°
0.700
0.135
0.080
10°
S
α
N
32
32
Figure 9. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
12/15
M27V201
Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
mm
Min
2.54
1.52
0.38
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
inches
Symb
Typ
Max
3.56
2.41
–
Typ
Min
Max
0.140
0.095
–
A
A1
A2
B
0.100
0.060
0.015
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
13/15
M27V201
Table 15. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.007
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
14/15
M27V201
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