M27W1282120M1 [STMICROELECTRONICS]
4MX16 OTPROM, 120ns, PDSO44, 0.500 INCH, PLASTIC, SO-44;
| 型号： | M27W1282120M1 |
| 厂家： | 
ST |
| 描述： | 4MX16 OTPROM, 120ns, PDSO44, 0.500 INCH, PLASTIC, SO-44 可编程只读存储器 OTP只读存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27W1282
128 Mbit (two 64 Mbit, x16, FlexibleROM™)
3V Supply, Multiple Memory Product
FEATURES SUMMARY
■ ONE TIME PROGRAMMABLE
Figure 1. Packages
■ TWO 64 Mbit FlexibleROM™ MEMORIES
STACKED IN A SINGLE PACKAGE
■ SUPPLY VOLTAGE
– V = 2.7 to 3.6V for Read
CC
– V = 11.4 to 12.6V for Program
PP
■ ACCESS TIME
– 90ns at V = 3.0 to 3.6V
CC
– 100, 120ns at V = 2.7 to 3.6V
CC
■ PROGRAMMING TIME
– 9µs per Word typical
SO44 (M)
– Multiple Word Programming Option
(16s typical Chip Program)
■ SUITABLE FOR ON-BOARD PROGRAMMING
■ PROGRAM CONTROLLER
– Embedded Word Program algorithms
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code : 8888h
November 2003
1/22
M27W1282
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
CC
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address/Voltage Supply (A22/V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PP)
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Verify Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. A22 Latch Procedure Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. A22 Latch Procedure AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Program Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Multiple Word Program Flowchart for 64Mbit Top and Bottom Die . . . . . . . . . . . . . . . . . 12
2/22
M27W1282
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
PP
Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Chip Enable Controlled, Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . . . . . . . . . 20
SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data. . . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21
3/22
M27W1282
SUMMARY DESCRIPTION
The M27W1282 is a 128 Mbit (8Mb x16) non-volatile,
One Time Programmable (OTP), FlexibleROM™
Memory. Read operations can be performed using a
single low voltage (2.7 to 3.6V) supply. Program op-
A22 selects the memory to be enabled. The other
memory is in Standby mode.
In Read mode the A22 pin works as an address
pin: A22 at V selects the Top die; A22 at V se-
IH
IL
erations require an additional V (11.4 to 12.6V)
PP
lectrs the Bottom die. At the beginning of any pro-
gram operation, a specific procedure (see Figure
4) must be performed to internally memorize the
A22 value that will be used during the program op-
eration.
The M27W1282 features an innovative command,
Multiple Word Program, used to program large
streams of data. It greatly reduces the total pro-
gramming time when a large number of Words are
written to the memory at any one time. Using this
command the entire memory can be programmed
in 8s, compared to 36s using the standard Word
Program.
power supply. On power-up the memory defaults to
Read mode where it can be read in the same way as
a ROM or EPROM.
The Mask-ROM compatibility is obtained using a
dual function Address/Voltage Supply pin (A22/
V
). In Read mode the A22/V pin works as an
PP
PP
address pin; in Program mode it also works as a
voltage supply pin. At the beginning of any pro-
gram operation, a specific procedure (see Figure
4) must be performed to internally memorize the
A22 value that will be used during the program op-
eration.
Program commands are written to the Command
Interface of the memory. An on-chip Program Con-
troller (PC) simplifies the process of programming
the memory by taking care of all of the special op-
erations that are required to update the memory
contents.
The device is composed of two 64Mbit memories
assembled side by side in a single package. Rec-
ommended operating conditions do not allow both
memories to be active at the same time. Address
The end of a program operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allow simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44 package and is
supplied with all the bits set to ’1’.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A21
Address Inputs
Address Input/Supply Voltage for
Program
A22/V
PP
V
A22/V
PP
CC
DQ0-DQ15
Data Inputs/Outputs
Chip Enable
E
22
16
A0-A21
DQ0-DQ15
G
Output Enable
Supply Voltage read
Ground
V
CC
M27W1282
E
V
SS
G
V
SS
AI08220
4/22
M27W1282
Figure 3. SO Connections
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
2
3
4
A9
5
A10
A11
A12
A13
A14
A15
A16
A22/V
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M27W1282
PP
V
V
SS
DQ15
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
DQ2
DQ10
DQ3
DQ12
DQ4
DQ11
V
CC
AI08221
5/22
M27W1282
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program Controller.
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Interface does not
use these bits. When reading the Status Register
these bits should be ignored.
Address/Voltage Supply (A22/V ). The
PP
A22/V signal has two functions.
PP
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
During read operations the A22/V signal works
as an address input, which is used to select the
PP
Top (A22 = V ) or Bottom (A22 = V ) die.
IH
IL
tions, when V is in the V range.
PP
HH
During program operations it also works as a V
PP
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operations of the memory. It
voltage supply pin. At the beginning of any pro-
gram operation, a specific procedure (see Figure
4) must be performed to internally memorize the
A22 value that will be used during the program op-
eration.
also allows Bus Write operations, when V is in
PP
the V range.
HH
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for Read operations.
When the V is in the V
range (see Table 11,
HH
PP
DC Characteristic, for the relevant values) pro-
gram operations are enabled. During such opera-
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CC
SS
tions V
must be stable in the V
range.
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
PP
HH
Program operation are not allowed when V
is
PP
below the V range.
HH
tions, I
Vss Ground. The V
for all voltage measurements.
.
CC3
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Ground is the reference
SS
6/22
M27W1282
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Table 2, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
be held within V ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program operation the memory will contin-
CC
ue to use the Program Supply Current, I
, for
CC3
Inputs and applying a Low signal, V , to Chip En-
IL
Program operation until the operation completes.
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 11, Read AC
Waveforms, and Table 12, Read AC Characteris-
tics, for details of when the output becomes valid.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
duced to the Standby Supply Current, I
. The
CC2
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
when V is set to V . A valid Bus Write opera-
PP
HH
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 2, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Enable. Output Enable must remain High, V ,
IH
during the whole Bus Write operation. See Figure
12, Write AC Waveforms, and Table 13, Write AC
Characteristics, for details of the timing require-
ments.
Table 2. Bus Operations
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15-DQ0
(2)
PP
Operation
Bus Read
E
G
A22/V
(3)
V
V
IL
Cell Address
Data Output
IL
IL
V /V
IL IH
(4)
V
V
IH
V
IH
Bus Write
Command Address
Data Input
Hi-Z
V
HH
Output Disable
Standby
X
X
X
X
V
X
X
Hi-Z
IH
A0 = V , A1 = V ,
Read Manufacturer
Code
IL
IL
V
V
V
V
0020h
8888h
IL
IL
IL
IL
HH
Others V or V
IL
IH
A0 = V , A1 = V ,
IH
IL
V
V
HH
Read Device Code
Others V or V
IL
IH
Note: 1. X = V or V
.
IH
IL
2. When reading the Status Register during a program operation A22/V must be kept at V
.
HH
PP
3. V enables the Bottom die, V enables the Top die during read array operation.
IL
IH
4. V after latching A22 at V or V .
IH
HH
IL
7/22
M27W1282
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 4 and 5, for a summary of the com-
mands.
Read/Reset Command.
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
V
must be set to V
during the Read/Reset
PP
HH
command. If V is set to either V or V the com-
once. V must be set to V during Multiple Word
Program. If V is set either V or V the com-
PP IL IH
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
PP
IL
IH
PP HH
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Auto Select Command.
The Auto Select command is used to read the
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Manufacturer Code and the Device Code. V
PP
must be set to V
during the Auto Select com-
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the PC has started (see Table 7 and
Figure 7).
HH
mand. If V is set to either V or V the com-
PP
IL
IH
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 5, Multiple Word Program and Figure
6, Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the PC is ready to accept the opera-
tion (see Table 7 and Figure 7).
with A0 = V and A1 = V . The other address bits
IL
IL
may be set to either V or V .
IL
IH
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V .
IL
IH
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. V must be
The Program Phase is executed in three different
sub-phases:
PP
set to V during Word Program. If V is set to ei-
HH
PP
ther V or V the command will be ignored, the
IL
IH
1. The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
Start Address and the first Word to be
programmed.
2. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A21 equal to the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the PC.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
8/22
M27W1282
Start Address), that indicates to the PC that the
Program Phase has to continue. A0 to A16 are
‘don’t care’.
but only a Continue Address, CA (A17 to A21
equal to the Start Address).
3. Finally, after all Words have been verified, a Bus
Write cycle with a Final Address, FA (A17 or a
higher address pin different from the Start
Address) ends the Verify Phase.
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 7
and Figure 7).
If the Verify Phase is successful, the memory re-
turns to Read mode and DQ6 stops toggling.
If the PC fails to reprogram a given location, the
Verify Phase terminates, DQ6 continues toggling
and error bit DQ5 is set in the Status Register. If
3. Finally, after all Words have been programmed,
th
a Bus Write operation (the (n+1) ) with a Final
Address, FA (A17 or a higher address pin
different from the Start Address), ends the
Program Phase.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the PC is ready for the next operation
or if the reprogram of the location has failed (see
Table 7 and Figure 7).
the error is due to a V failure DQ4 is also set.
PP
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
Three successive steps are required to execute
the Verify Phase of the command:
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 6.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
1. The first Bus Write operation of the Verify Phase
latches the Start Address and the Word to be
verified.
2. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
Note that the Multiple Word Program command
cannot change a bit set to ’0’ back to ’1’.
9/22
M27W1282
Figure 4. A22 Latch Procedure Waveforms
tA9HA9L
V
TL
A9
A22 latched on
TL rising edge
tA22VA9TL
A22
VALID
A0-A8;
A10-A21
E
AI08257
Note: G = V ; DQ0–DQ15 are Don’t care; V = 10.5 ± 0.25V; V = 2.7 to 3.6V; V = V or V .
IH
IH
TL
CC
PP
IL
Table 3. A22 Latch Procedure AC Characteristics
Symbol
Parameter
A22 valid to A9 at Third Level
A9 High to A9 Low
Min
1
Unit
t
µs
µs
A22VA9TL
t
1
A9HA9L
Figure 5. Programming Flowchart
Start
A22 Latch procedure
with A22 = V
IH
Program Command
execution on
64Mbit Top die
A22 Latch procedure
with A22 = V
IL
Program Command
execution on
64Mbit Bottom die
READ (verify pattern)
on 128Mbit
End
AI08208
10/22
M27W1282
Table 4. Standard Commands
Bus Write Operations
2nd 3rd
Command
1st
4th
Add
X
Data
F0
Add
Data
Add
Data
Add
Data
1
3
3
4
Read/Reset
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
X
F0
90
A0
Auto Select
555
555
Word Program
PA
PD
Note: X Don’t Care, PA Program Address, PD Program Data. All values in the table are in hexadecimal. The Command Interface only uses
A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Bus Write Operations
Phase
1st
Add Data Add Data Add Data Add Data Add Data
555 AA 2AA 55 555 20
2nd
3rd
4th
5th
nth
Final
Add Data Add Data
Set-Up
3
Program n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
Verify n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
CA
CA
PAn
PAn
FA
FA
X
X
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program Times
(1)
Parameter
Max
200
280
280
Unit
µs
s
Typ
Program (Word)
9
Chip Program (Multiple Word)
Chip Program (Word by Word)
16
72
s
Note: 1. T = 25°C, V = 12V.
A
PP
11/22
M27W1282
Figure 6. Multiple Word Program Flowchart for 64Mbit Top and Bottom Die
Start
Setup
Verify
Phase
Phase
Read Status
Register
Write AAh
Address 555h
Write 55h
Address 2AAh
NO
DQ0 = 0?
Write 20h
Address 555h
Write Data1
Start Address
Read Status
Register
Read Status
Register
NO
NO
DQ5 = 1 ?
NO
NO
DQ6
Setup time
exceeded?
NO
toggling?
DQ0 = 0?
YES
YES
YES
YES
Write Data 2
Continue Address
EXIT (setup failed)
DQ0 = 0?
YES
Write Data1
Start Address
Read Status
Register
Program
Phase
NO
Read Status
Register
NO
DQ0 = 0?
YES
DQ5 = 1?
YES
NO
NO
NO
DQ0 = 0?
Write Data n
Continue Address
YES
Write Data 2
Continue Address
Read Status
Register
NO
Read Status
Register
NO
DQ0 = 0?
YES
DQ5 = 1?
YES
Exit
Phase
DQ0 = 0?
YES
Read Status
Register
Write XX
Final Address
Write Data n
Continue Address
YES
NO
DQ4 = 0?
Read Status
Register
Fail error
Read Status
Register
Fail, VPP error
YES
DQ6
toggling?
Write F0h
Address XX
DQ0 = 0?
YES
NO
Write XX
Final Address
Exit (read mode)
AI05954b
12/22
M27W1282
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program opera-
tions. The bits in the Status Register are summa-
rized in Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program Controller
has successfully completed its operation. The
Data Polling Bit is output on DQ7 when the Status
Register is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement.
Figure 7, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed.
Figure 8, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program Controller.
The Error Bit is set to ’1’ when a Program opera-
tion fails to write the correct data to the memory. If
the Error Bit is set a Read/Reset command must
be issued before other commands are issued. The
Error bit is output on DQ5 when the Status Regis-
ter is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’.
V
Status Bit (DQ4). The V Status Bit can be
PP
PP
used to identify if any Program operation has failed
due to a V error. If V falls below V during
PP
PP
HH
any Program operation, the operation aborts and
DQ4 is set to ‘1’. If V remains at V throughout
PP
HH
the Program operation, the operation completes
and DQ4 is set to ‘0’.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program Controller has suc-
cessfully completed its operation. The Toggle Bit
is output on DQ6 when the Status Register is read.
During Program operations the Toggle Bit chang-
es from ’0’ to ’1’ to ’0’, etc., with successive Bus
Read operations at any address. After successful
completion of the operation the memory returns to
Read mode.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the Program Controller is active or inactive during
Multiple Word Program. When the Program Con-
troller has written one Word and is ready to accept
the next Word, the bit is set to ‘0’.
Status Register Bit DQ1 is reserved.
13/22
M27W1282
Table 7. Status Register Bits
(1)
P.C. Status
Programming
DQ7
–
DQ6
DQ5
DQ4
DQ3
DQ0
Command
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
1
0
1
–
0
0
0
0
0
1
0
1
–
–
Multiple Word Program
Word Program
Waiting for data
Program fail
–
–
(2)
–
Programming
Program error
DQ7
DQ7
–
(2)
Note: 1. Unspecified data bits should be ignored.
2. DQ4 = 0 if V ≥ V during Program algorithm execution; DQ4 = 1 if V < V during Program algorithm execution.
PP
HH
PP
HH
Figure 7. Data Polling Flowchart
Figure 8. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
PASS
YES
FAIL
PASS
AI03598
AI01370B
14/22
M27W1282
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings" table may cause
permanent damage to the device. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
–65
Max
125
150
Unit
°C
T
Temperature Under Bias
Storage Temperature
BIAS
T
°C
STG
(1,2)
V
+0.6
–0.6
–0.6
–0.6
V
V
V
V
CC
Input or Output Voltage
Read Supply Voltage
IO
V
4
CC
(3)
V
13.5
PP
Program Supply Voltage
Note: 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V for less than 20ns during transitions.
CC
3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. V must not remain at V for more than a total
PP
HH
of 80hrs.
15/22
M27W1282
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Parameter
M27W1282
100, 120
Unit
Min
2.7
11.4
0
Max
3.6
V
V
Read Supply Voltage
V
V
CC
Program Supply Voltage
12.6
70
PP
Ambient Operating Temperature
°C
pF
ns
V
Load Capacitance (C )
30
L
Input Rise and Fall Times
10
Input Pulse Voltages
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Figure 9. AC Measurement I/O Waveform
Figure 10. AC Measurement Load Circuit
1.3V
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
AI05546
UNDER
TEST
OUT
C
L
C = 30pF
L
C includes JIG capacitance
L
AI05447
Table 10. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
12
Unit
pF
C
IN
V
= 0V
= 0V
IN
C
V
OUT
24
pF
OUT
C
A22/V Capacitance
V
= 0V
50
pF
A22/Vpp
PP
A22/Vpp
Note: Sampled only, not 100% tested.
16/22
M27W1282
Table 11. DC Characteristics
(1)
Symbol
Test Condition
Min
Max
Unit
µA
Parameter
I
0V ≤ V ≤ V
Input Leakage Current
±1
±1
LI
IN
CC
I
LO
0V ≤ V ≤ V
OUT CC
Output Leakage Current
Supply Current (Read)
µA
E = V , G = V ,
IL
IH
I
10
mA
CC1
I
= 0mA, f = 6MHz
OUT
(2)
E = V ±0.2V
Supply Current (Standby)
Supply Current (Program)
Input Low Voltage
150
20
µA
mA
V
I
CC
CC2
I
PC active
CC3
V
–0.5
0.8
IL
V
0.7V
V
CC
+0.3
Input High Voltage
V
IH
CC
V
I
= 1.8mA
OL
Output Low Voltage
Output High Voltage
0.45
V
OL
V
OH
V
–0.4
CC
V
I
= –100µA
OH
V
V
V
Program Voltage
Current (Program)
11.4
12.6
10
V
HH
PP
I
PC Active
mA
HH
PP
Note: 1. V must be applied simultaneously or before V and removed simultaneously or after V .
PP
CC
PP
2. Average Value.
17/22
M27W1282
Figure 11. Read AC Waveforms
A0-A22
VALID
tAVQV
tAXQX
E
tELQV
tEHQZ
G
tGLQV
tGHQZ
VALID
DQ0-DQ15
AI08263
Table 12. Read AC Characteristics
M27W1282
(1)
Symbol Alt
Test Condition
100
120
Unit
Parameter
V
CC
= 3.0 to 3.6V V = 2.7 to 3.6V V = 2.7 to 3.6V
CC
CC
E = V ,
Address Valid to
Output Valid
IL
t
t
t
t
ACC
Max
90
90
35
30
30
0
100
100
35
30
30
0
120
120
35
30
30
0
ns
ns
ns
ns
ns
ns
AVQV
G = V
IL
Chip Enable Low to
Output Valid
t
G = V
Max
Max
Max
Max
Min
ELQV
CE
IL
Output Enable Low to
Output Valid
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
t
t
G = V
t
HZ
DF
IL
EHQZ
Output Enable High
to Output Hi-Z
(2)
E = V
t
IL
GHQZ
Address Transition to
Output Transition
t
AXQX
OH
Note: 1. V must be applied after V and with the Chip Enable (E) at V .
IH
PP
CC
2. Sampled only, not 100% tested.
18/22
M27W1282
Figure 12. Chip Enable Controlled, Write AC Waveforms
A0-A21
VALID
tELAX
tAVEL
tEHGL
G
E
tGHEL
tELEH
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ15
V
CC
tVCHEL
tVPHEL
A22/V
PP
AI08233
Table 13. Chip Enable Controlled, Write AC Characteristics
(1)
Symbol
Alt
M27W1282
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Parameter
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
50
50
0
ELEH
CP
t
t
DVEH
DS
t
t
Chip Enable High to Input Transition
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
EHDX
DH
t
t
CPH
50
0
EHEL
t
t
AS
AVEL
t
t
100
10
10
50
ELAX
AH
t
GHEL
t
t
OEH
EHGL
t
t
t
V
V
High to Chip Enable Low
High to Chip Enable Low
VCHEL
VCS
CC
PP
(2)
Min
500
ns
t
VCS
VPHEL
Note: 1. T = 25°C; V = 11.4 to 12.6V. V = 2.7 to 3.6V.
A
PP
CC
V
must be applied after V and with the Chip Enable (E) at V .
PP
CC IH
Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
19/22
M27W1282
PACKAGE MECHANICAL
Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline
D
44
23
c
E1 E
θ
1
22
A1
L
A2
A
L1
ddd
b
e
SO-F
Note: Drawing is not to scale.
Table 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
3.00
0.118
0.10
2.69
0.004
0.106
2.56
0.35
2.79
0.50
0.28
28.63
0.10
16.28
12.73
–
0.101
0.014
0.007
1.117
0.110
0.020
0.011
1.127
0.004
0.641
0.501
–
c
0.18
D
28.50
28.37
1.122
ddd
E
16.03
12.60
1.27
15.77
12.47
–
0.631
0.496
0.050
0.031
0.068
0.621
0.491
–
E1
e
L
0.79
L1
θ
1.73
8°
8°
N
44
44
20/22
M27W1282
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M27W128 2
100 N
1
T
Device Type
M27 = FlexibleROM™ Memory
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
128 = 128 Mbit (x16)
Device Function
2 = 2 dice
Speed
(1)
100
= 100 ns
120 = 120 ns
Package
M = SO44, 500mils body width
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Note: 1. This speed also guarantees 90ns access time at V = 3.0 to 3.6V.
CC
Devices are shipped from the factory with all the bits set to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 16. Document Revision History
Date
Version
1.0
Revision Details
29-Apr-2003
17-Sep-2003
17-Nov-2003
First Issue
1.1
From Preliminary Data to Datasheet
1.2
100ns speed class also guarantees 90ns
21/22
M27W1282
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
FlexibleROM is a pending trademark of STMicroelectronics Group
All other names are the property of their respective owners
© 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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