M28256-15BS1 [STMICROELECTRONICS]
32KX8 EEPROM 5V, 150ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | M28256-15BS1 |
| 厂家： | 
ST |
| 描述： | 32KX8 EEPROM 5V, 150ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总21页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28256
256 Kbit (32Kb x8) Parallel EEPROM
with Software Data Protection
PRELIMINARY DATA
FASTACCESSTIME:
– 90ns at 5V
– 120ns at 3V
SINGLE SUPPLY VOLTAGE:
±
– 5V 10% for M28256
28
– 2.7V to 3.6V for M28256-xxW
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
1
PDIP28 (BS)
PLCC32 (KA)
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle
ENHANCED END of WRITEDETECTION:
– Data Polling
28
– Toggle Bit
1
STATUS REGISTER
HIGH RELIABILITYDOUBLE POLYSILICON,
CMOS TECHNOLOGY:
SO28 (MS)
300 mils
TSOP28 (NS)
8 x13.4mm
– Endurance >100,000 Erase/Write Cycles
– Data Retention >10 Years
JEDEC APPROVEDBYTEWIDE PIN OUT
ADDRESS and DATA LATCHED ON-CHIP
SOFTWARE DATA PROTECTION
Figure 1. Logic Diagram
V
CC
DESCRIPTION
The M28256and M28256-Ware 32K x8 low power
ParallelEEPROMfabricatedwithSTMicroelectron-
ics proprietary double polysilicon CMOS technol-
ogy.
15
8
A0-A14
DQ0-DQ7
W
E
M28256
Table 1. Signal Names
A0-A14
Address Input
Data Input / Output
Write Enable
Chip Enable
DQ0-DQ7
G
W
E
V
SS
G
Output Enable
Supply Voltage
Ground
AI01885
VCC
VSS
January 1999
1/21
This is preliminaryinformationon a new productnow in developmentor undergoingevaluation.Detail s aresubject to change without notice.
M28256
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
A14
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
1 32
26 A13
25 A8
24 A9
23 A11
A6
A8
A6
A5
A4
A3
A9
A5
A11
NC
G
A4
A3
22
G
M28256
A2
A1
9
M28256
25
A2
21 A10
20
A10
E
A1
E
A0
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
NC
DQ7
DQ6
DQ0
17
V
SS
14
AI01886
AI01887
Warning:
NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
G
A11
A9
22
21
A10
E
A14
A12
A7
1
28
27
V
CC
W
2
DQ7
DQ6
DQ5
DQ4
DQ3
3
26
A13
A8
A6
4
25
A8
A5
5
24
A9
A13
W
A4
6
23
A11
G
V
28
1
15
14
A3
7
22
CC
M28256
M28256
A14
V
A2
8
21
A10
E
SS
A1
9
20
A12
A7
A6
A5
A4
A3
DQ2
DQ1
DQ0
A0
A0
10
11
12
13
14
19
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
18
17
16
A1
7
8
A2
V
SS
15
AI01888
AI01889
2/21
M28256
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
– 40 to 85
Unit
Ambient Operating Temperature (2)
Storage TemperatureRange
Supply Voltage
°C
TSTG
VCC
VIO
– 65 to 150
– 0.3 to 6.5
– 0.3 to VCC +0.6
– 0.3 to 6.5
4000
C
°
V
V
V
V
Input/Output Voltage
VI
Input Voltage
VESD
Electrostatic Discharge Voltage (Human Body model) (3)
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
3. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Figure 3. Block Diagram
E
G
W
V
GEN
RESET
CONTROL LOGIC
PP
ADDRESS
LATCH
A6-A14
(Page Address)
256K ARRAY
ADDRESS
LATCH
A0-A5
Y
DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01697
3/21
M28256
Table 3. Operating Modes (1)
Mode
E
VIL
VIL
VIH
X
G
VIL
VIH
X
W
VIH
VIL
X
DQ0 - DQ7
Data Out
Read
Write
Data In
Standby / Write Inhibit
Write Inhibit
Hi-Z
X
VIH
X
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
Write Inhibit
X
VIL
VIH
Output Disable
X
X
Notes: 1. X = VIH or VIL.
DESCRIPTION
Read
(Cont’d)
The device is accessedlike a static RAM. When E
and G are low with W high, the data addressed is
presented on the I/O pins. The I/O pins are high
impedancewhen either G or E is high.
The devices offer fast access time with low power
dissipationand requires a 5V or 3V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The
devices support a 64 byte page write operation. A
Software Data Protection (SDP) is also possible
using the standard JEDEC algorithm.
Write
Write operations are initiated when both W and E
are low and G is high.The device supportsboth E
and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the risingedge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion and
the status of the Data Polling and the Toggle Bit
functions on DQ7 and DQ6 is controlled accord-
ingly.
PIN DESCRIPTION
Addresses (A0-A14).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
Page Write
low to enableall read/writeoperations.When Chip
Enable is high, power consumptionis reduced.
Page write allows up to 64 bytes within the same
page to be consecutivelylatched into the memory
prior to initiating a programming cycle. All bytes
must be located in a single page address, that is
A14-A6 must be the same for all bytes;if not,the
Page Write instruction is not executed. The page
write can be initiated by any byte write operation.
Output Enable (G).
The Output Enableinput con-
trols the data output buffers and is used to initiate
read operations.
DataIn/ Out (DQ0-DQ7).
Data is writtento or read
from the memory through the I/O pins.
Write Enable (W).
A page write is composed of successive Write
instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
smaller than the tWHWH value (see Table 12 and
Table 13).
TheWrite Enableinput controls
the writing of data to the memory.
OPERATIONS
Write Protection
In orderto preventdata corruptionand inadvertent
write operations;an internalVCC comparatorinhib-
its Write operationsif VCC is below VWI (see Table
7 andTable 9).Accessto thememoryinwrite mode
is allowed after a power-upas specifiedin Table 7
and Table 9.
If this period of time exceeds the tWHWH value, the
internalprogrammingcycle will start.Once initiated
the write operationis internallytimed until comple-
tion and the status of the Data Polling and the
ToggleBit functionson DQ7and DQ6 is controlled
accordingly.
4/21
M28256
Status Register
Software Data Protection
The devices offer a software controlled write pro-
tectionfacility thatallowstheuser toinhibit allwrite
modes to the device.This can be usefulin protect-
ing the memory from inadvertentwrite cycles that
may occur due to uncontrolledbus conditions.
Thedevicesareshippedas standardin the”unpro-
tected” state meaning that the memory contents
can be changedas required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents.
The devices remain in this mode until a valid
SoftwareData Protection(SDP) disable sequence
is received whereby the device reverts to its ”un-
protected”state. The Software Data Protection is
fully non-volatile and is not changed by power
on/off sequences. To enable the Software Data
Protection (SDP) the device requires the user to
write (with a Page Write addressing three specific
databytestothreespecificmemorylocations,each
location in a different page) as per Figure 6. Simi-
larly to disable the Software Data Protection the
userhas to write specific data bytes into six differ-
ent locations as per Figure 5 (with a Page Write
adressing different bytes in differentpages).
Thedevicesprovide severalWrite operationstatus
flags that can be used to minimize the application
write time. These signals are available on the I/O
port bits during programming cycle only.
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The devices offer another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read any byte of the memory. When the internal
cycle is completed the toggling will stop and the
data read on DQ7-DQ0 is the addressed memory
byte.The deviceis nowaccessiblefor a newRead
or Writeoperation.
PageLoadTimerStatus bit(DQ5). Duringa Page
Write instruction, the devices expect to receivethe
stream of data with a minimum period of time
between each data byte. This period of time
(tWHWH) is defined by the on-chip Page Load timer
which running/overflowstatusis availableon DQ5.
DQ5 Low indicates that the timer is running, DQ5
High indicates the time-out after which the internal
write cycle will start.
Thiscomplexseriesensuresthattheuserwill never
enable or disable the Software Data Protection
accidentally.
To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
An extension tothis is where SDPis required to be
set, and data is to be written.
DP
TB PLTS
X
X
X
X
X
Using the same sequence as above, the data can
be written and SDP is set at the same time, giving
both these actions in the same Write cycle (tWC).
DP
TB
= Data Polling
= Toggle Bit
PLTS = Page Load Timer Status
5/21
M28256
Figure 5. Software Data Protection Enable Algorithm and Memory Write
SDP
Set
SDP
not Set
WRITE AAh in
Address 5555h
WRITE AAh in
Address 5555h
Page
Write
Instruction
WRITE 55h in
Address 2AAAh
WRITE 55h in
Address 2AAAh
Page
Write
Instruction
WRITE A0h in
Address 5555h
WRITE A0h in
Address 5555h
WRITE
is enabled
SDP is set
WRITE Data to
be Written in
any Address
Write
Write Data
in Memory
+
SDP ENABLE ALGORITHM
SDP Set
after tWC
AI01698B
Figure 6. Software Data Protection Disable Algorithm
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 80h in
Address 5555h
Page
Write
Instruction
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 20h in
Address 5555h
Unprotected State
after
tWC (Write Cycle time)
AI01699B
6/21
M28256
Table 4. AC MeasurementConditions
Input Rise and Fall Times
≤ 20ns
Input Pulse Voltages (M28256)
0.4V to 2.4V
0V to VCC –0.3V
0.8V to 2.0V
0.5 VCC
Input Pulse Voltages (M28256-W)
Input and Output Timing Ref. Voltages (M28256)
Input and Output Timing Ref. Voltages (M28256-W)
Figure 7. AC Testing Input Output Waveforms
Figure 8. AC Testing Equivalent Load Circuit
4.5V to 5.5V Operating Voltage
2.4V
2.0V
0.8V
I
OL
0.4V
DEVICE
UNDER
TEST
OUT
2.7V to 3.6V Operating Voltage
I
OH
V
– 0.3V
CC
C
= 100pF
L
0.5 V
CC
0V
AI02101B
C
includes JIG capacitance
L
AI02102B
Table 5. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
CIN
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
12
pF
Note:
1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristicsfor M28256
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
Unit
10
10
30
25
1
µA
µA
mA
mA
mA
µA
V
ILO
Output Leakage Current
Supply Current (TTL inputs)
Supply Current (CMOS inputs)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
0V ≤ VIN ≤ VCC
E = VIL, G = VIL , f = 5 MHz
E = VIL, G = VIL , f = 5 MHz
E = VIH
(1)
ICC
(1)
ICC1
(1)
ICC2
E > VCC –0.3V
100
0.8
VIL
VIH
– 0.3
2
Input High Voltage
VCC + 0.5
0.4
V
VOL
VOH
Output Low Voltage
IOL = 2.1 mA
V
Output High Voltage
IOH = –400 µA
2.4
Note: 1. All I/O’s open circuit.
7/21
M28256
Table 7. Power Up Timing for M28256 (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
tPUR
Parameter
Time Delay to Read Operation
Min
Max
1
Unit
µs
tPUW
Time Delay to Write Operation (once VCC ≥ VWI
)
5
ms
V
VWI
Write Inhibit Threshold
3.0
4.2
Note:
1. Sampled only, not 100% tested.
Table 8. Read Mode DC Characteristicsfor M28256-W
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
Unit
10
10
µA
µA
ILO
0V ≤ VIN ≤ VCC
E = VIL, G = VIL, f = 5 MHz, VCC = 3.3V
E = VIL, G = VIL, f = 5 MHz, VCC = 3.6V
E > VCC –0.3V
15
mA
mA
(1)
ICC
Supply Current (CMOS inputs)
15
(1)
ICC2
Supply Current (Standby) CMOS
Input Low Voltage
20
A
µ
VIL
VIH
– 0.3
2
0.6
V
Input High Voltage
VCC + 0.5
0.2 VCC
V
V
V
VOL
VOH
Output Low Voltage
IOL = 2.1 mA
Output High Voltage
IOH = –400
A
0.8 VCC
µ
Note:
1. All I/O’s open circuit.
Table 9. Power Up Timing for M28256-W (1)
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 2.7V to 3.6V)
Symbol
tPUR
Parameter
Time Delay to Read Operation
Min
Max
1
Unit
µs
tPUW
Time Delay to Write Operation (once VCC
Write Inhibit Threshold
V
WI
)
10
ms
V
≥
VWI
1.5
2.5
Note: 1. Sampled only, not 100% tested.
8/21
M28256
Table 10. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
M28256
Symbol
Alt
Parameter
Test Condition
Unit
-90
-12
-15
-20
min max min max min max min max
Address Valid to
Output Valid
tAVQV
tELQV
tGLQV
tACC
tCE
tOE
tDF
tDF
tOH
E = VIL, G = V
90
90
40
40
40
120
120
45
150
150
50
200
200
50
ns
ns
ns
ns
ns
ns
IL
Chip Enable Low to
Output Valid
G = VIL
E = VIL
Output Enable Low
to Output Valid
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
0
0
0
45
0
0
0
50
0
0
0
50
Output Enable High
to Output Hi-Z
(1)
tGHQZ
E = VIL
45
50
50
Address Transition
to Output Transition
tAXQX
E = VIL, G = VIL
Note:
1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 11. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
M28256-W
-15 -20
min max min max min max min max
Symbol
Alt
Parameter
Test Condition
Unit
-12
-25
Address Valid to
Output Valid
tAVQV
tELQV
tGLQV
tACC
tCE
tOE
tDF
tDF
tOH
E = VIL, G = V
120
120
45
150
150
70
200
200
80
250
250
100
60
ns
ns
ns
ns
ns
ns
IL
Chip Enable Low to
Output Valid
G = VIL
E = VIL
Output Enable Low
to Output Valid
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
45
0
0
0
50
0
0
0
55
0
0
0
Output Enable High
to Output Hi-Z
(1)
tGHQZ
E = VIL
45
50
55
60
Address Transition
to Output Transition
tAXQX
E = VIL, G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
9/21
M28256
Table 12. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
M28256
Symbol
Alt
Parameter
Test Condition
Unit
Min
Max
tAVWL
tAVEL
tELWL
tAS
tAS
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
E = VIL, G = VIH
G = VIH, W = VIL
G = VIH
0
0
0
ns
ns
ns
tCES
Output Enable High to Write Enable
Low
tGHWL
tOES
E = VIL
0
ns
tGHEL
tWLEL
tWLAX
tELAX
tWLDV
tELDV
tELEH
tWHEH
tOES
tWES
tAH
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
W = VIL
G = VIH
0
0
ns
ns
ns
ns
50
50
tAH
tDV
E = VIL, G = VIH
G = VIH, W = VIL
1
1
s
µ
tDV
Chip Enable Low to Input Valid
µs
ns
ns
tWP
tCEH
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
50
0
Write Enable High to Output Enable
Low
tWHGL
tOEH
0
ns
tEHGL
tEHWH
tWHDX
tEHDX
tOEH
tWEH
tDH
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Byte Load Repeat Cycle Time
0
0
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
ns
0
tDH
0
tWHWL
tWLWH
tWHWH
tWHRH
tEL, tWL
tDVWH
tDVEH
tWPH
tWP
100
50
0.15
tBLC
tWC
150
5
Write Cycle Time
E or W Input Filter Pulse Width
Note 1
10
50
50
tDS
tDS
Data Valid before Write Enable High
Data Valid before Chip Enable High
Note: 1. Characterized only but not testedin production.
10/21
M28256
Table 13. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
M28256-W
Symbol
Alt
Parameter
Test Condition
Unit
Min
0
Max
tAVWL
tAVEL
tELWL
tAS
tAS
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
E = VIL, G = VIH
G = VIH, W = VIL
G = VIH
ns
ns
ns
0
tCES
0
Output Enable High to Write Enable
Low
tGHWL
tOES
E = VIL
0
ns
tGHEL
tWLEL
tWLAX
tELAX
tWLDV
tELDV
tELEH
tWHEH
tOES
tWES
tAH
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
W = VIL
G = VIH
0
0
ns
ns
ns
ns
70
70
tAH
tDV
E = VIL, G = VIH
G = VIH, W = VIL
1
1
s
µ
tDV
Chip Enable Low to Input Valid
µs
ns
ns
tWP
tCEH
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
100
0
Write Enable High to Output Enable
Low
tWHGL
tOEH
0
ns
tEHGL
tEHWH
tWHDX
tEHDX
tOEH
tWEH
tDH
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Byte Load Repeat Cycle Time
0
0
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
ns
0
tDH
0
tWHWL
tWLWH
tWHWH
tWHRH
tEL, tWL
tDVWH
tDVEH
tWPH
tWP
100
100
0.2
tBLC
tWC
150
5
Write Cycle Time
E or W Input Filter Pulse Width
Note 1
10
50
50
tDS
tDS
Data Valid before Write Enable High
Data Valid before Chip Enable High
Note: 1. Characterized only but not testedin production.
11/21
M28256
Figure 9. Read Mode AC Waveforms
A0-A14
VALID
tAVQV
tAXQX
E
tGLQV
tEHQZ
tGHQZ
G
tELQV
Hi-Z
DQ0-DQ7
DATA OUT
AI01700
Note: Write Enable (W) = High.
Figure 10. Write Mode AC Waveforms - Write Enable Controlled
A0-A14
VALID
tAVWL
tELWL
tGHWL
tWLAX
E
tWHEH
tWHGL
G
tWLWH
W
tWLDV
tWHWL
DATA IN
tDVWH
DQ0-DQ7
tWHDX
AI01701
12/21
M28256
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
A0-A14
VALID
tAVEL
tGHEL
tWLEL
tELAX
E
tELEH
G
tEHGL
W
tELDV
tEHWH
DATA IN
tDVEH
DQ0-DQ7
tEHDX
AI01702
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A14
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
tWHRH
W
tWLWH
tWHWH
Byte 2
tWHWH
Byte n
DQ0-DQ7
DQ5
Byte 0
Byte 1
Byte n
AI01703B
13/21
M28256
Figure 13. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
tWHWH
W
tAVEL
tWLAX
2AAAh
A0-A5
Byte Address
Page Address
Byte 0
tWHDX
5555h
A6-A14
DQ0-DQ7
5555h
tDVWH
AAh
55h
A0h
Byte 62
Byte 63
AI01704
Note: A6 through A14 must specify the same page address during each high tolow transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.
Figure 14. Data Polling Waveform Sequence
A0-A14
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI01705
14/21
M28256
Figure 15. Toggle Bit Waveform Sequence
A0-A14
E
G
W
DQ6
(1)
DQ6
DQ6
LAST WRITE
TOGGLE
INTERNAL WRITE SEQUENCE
READY
AI01706
Note:
1. First Toggle bit is forced to ’0’.
15/21
M28256
ORDERING INFORMATION SCHEME
Example:
M28256 – 15
W
KA
6
T
Speed
90ns
Operating Voltage
blank 4.5V to 5.5V
2.7V to 3.6V
Package
BS PDIP28
KA PLCC32
Temperature Range
1 (3) 0 to 70 °C
Option
90 (1)
12
T
Tape & Reel
Packing
120ns
150ns
200ns
250ns
W
6
–40 to 85 °C
15
MS SO28 300 mils
20
25 (2)
NS TSOP28
8 x 13.4mm
Notes: 1. Not available for ”W” operatingvoltage.
2. Available for ”W” operating voltage only.
3. Temperature Range on request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFh).
Fora list ofavailableoptions(Speed, Package,etc...)or for furtherinformationon anyaspect of thisdevice,
please contact the STMicroelectronics Sales Office nearest to you.
16/21
M28256
PDIP28 - 28 pin Plastic DIP, 600 mils width
mm
Min
–
inches
Symb
Typ
Max
5.08
–
Typ
Min
–
Max
0.200
–
A
A1
A2
B
0.38
3.56
0.38
–
0.015
0.140
0.015
–
4.06
0.51
–
0.160
0.020
–
B1
C
1.52
0.060
0.20
36.83
–
0.30
37.34
–
0.008
1.450
–
0.012
1.470
–
D
D2
E
33.02
15.24
1.300
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
14.99
–
–
–
–
15.24
3.18
1.78
0°
17.78
3.43
2.08
10°
0.600
0.125
0.070
0°
0.700
0.135
0.082
10°
S
α
N
28
28
A2
A
A1
e1
L
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
17/21
M28256
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
–
inches
Min
0.100
0.060
–
Symb
Typ
Max
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
7
7
9
9
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
18/21
M28256
SO28 - 28 lead Plastic Small Outline, 300 mils body width
mm
Min
2.46
0.13
0.35
0.23
17.81
7.42
–
inches
Min
Symb
Typ
Max
2.64
0.29
0.48
0.32
18.06
7.59
–
Typ
Max
0.104
0.011
0.019
0.013
0.711
0.299
–
A
A1
B
0.097
0.005
0.014
0.009
0.701
0.292
–
C
D
E
e
1.27
0.050
H
10.16
0.61
0°
10.41
1.02
8°
0.400
0.024
0°
0.410
0.040
8°
L
α
N
28
28
CP
0.10
0.004
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
19/21
M28256
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
mm
Min
inches
Min
Symb
Typ
Max
1.25
0.20
1.15
0.27
0.21
13.60
11.90
8.10
-
Typ
Max
0.049
0.008
0.045
0.011
0.008
0.535
0.469
0.319
-
A
A1
A2
B
0.95
0.17
0.10
13.20
11.70
7.90
-
0.037
0.007
0.004
0.520
0.461
0.311
-
C
D
D1
E
e
0.55
0.022
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
28
28
CP
0.10
0.004
A2
22
21
e
28
1
E
B
7
8
D1
D
A
CP
DIE
C
TSOP-c
A1
α
L
Drawing is not to scale.
20/21
M28256
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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21/21
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