M28C17-120K1T [STMICROELECTRONICS]

16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTION; 16K 2K ×8并行EEPROM与软件数据保护
M28C17-120K1T
型号: M28C17-120K1T
厂家: ST    ST
描述:

16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTION
16K 2K ×8并行EEPROM与软件数据保护

存储 内存集成电路 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器
文件: 总17页 (文件大小:166K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
M28C17  
16K (2K x 8) PARALLEL EEPROM  
with SOFTWARE DATA PROTECTION  
NOT FOR NEW DESIGN  
FAST ACCESS TIME: 90ns  
SINGLE 5V ± 10% SUPPLY VOLTAGE  
LOW POWER CONSUMPTION  
FAST WRITE CYCLE:  
– 64 Bytes Page Write Operation  
– Byte or Page Write Cycle: 3ms Max  
28  
ENHANCED END OF WRITE DETECTION:  
– Ready/Busy Open Drain Output  
– Data Polling  
1
PDIP28 (P)  
PLCC32 (K)  
Toggle Bit  
PAGE LOAD TIMER STATUS BIT  
28  
HIGH RELIABILITY SINGLE POLYSILICON,  
CMOS TECHNOLOGY:  
1
– Endurance >100,000 Erase/Write Cycles  
– Data Retention >40 Years  
SO28 (MS)  
300 mils  
JEDEC APPROVED BYTEWIDE PIN OUT  
SOFTWARE DATA PROTECTION  
M28C17 is replaced by the products  
described on the document M28C16A  
Figure 1. Logic Diagram  
DESCRIPTION  
The M28C17 is a 2K x 8 low power Parallel  
EEPROM fabricated with SGS-THOMSON pro-  
prietary single polysilicon CMOS technology. The  
device offers fast access time with low power dis-  
sipation and requires a 5V power supply.  
V
CC  
11  
8
The M28C17 offers the same features than the  
M28C16, in addition to the Ready/Busy pin.  
A0-A10  
DQ0-DQ7  
The circuit has been designed to offer a flexible  
microcontroller interface featuring both hardware  
W
M28C17  
Table 1. Signal Names  
E
RB  
A0 - A10  
Address Input  
G
DQ0 - DQ7 Data Input / Output  
W
Write Enable  
Chip Enable  
Output Enable  
Ready / Busy  
Supply Voltage  
Ground  
E
V
SS  
G
AI01487  
RB  
VCC  
VSS  
November 1997  
1/17  
This is information on a product still in production but not recommended for new design.  
M28C17  
Figure 2A. DIP Pin Connections  
Figure 2B. LCC Pin Connections  
RB  
NC  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
9
28  
27  
V
CC  
W
1 32  
26 NC  
25 A8  
24 A9  
23 NC  
A6  
A8  
A5  
A4  
A3  
A9  
NC  
NC  
G
22  
G
M28C17  
A2  
A1  
9
M28C17  
25  
21 A10  
20  
A10  
E
E
A0  
A0 10  
DQ0 11  
DQ1 12  
DQ2 13  
19 DQ7  
18 DQ6  
17 DQ5  
16 DQ4  
15 DQ3  
NC  
DQ7  
DQ6  
DQ0  
17  
V
14  
SS  
AI01506B  
AI01508C  
Warning: NC = Not Connected.  
Warning: NC = Not Connected, DU = Don’t Use.  
DESCRIPTION (cont’d)  
Figure 2C. SO Pin Connections  
and software handshaking with Ready/Busy, Data  
Polling and Toggle Bit. The M28C17 supports 64  
byte page write operation. ASoftware Data Protec-  
tion (SDP) is also possible using the standard  
JEDEC algorithm.  
RB  
NC  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
W
2
3
NC  
A8  
PIN DESCRIPTION  
A6  
4
Addresses (A0-A10). The address inputs select  
an 8-bit memory location during a read or write  
operation.  
A5  
5
A9  
A4  
6
NC  
G
A3  
7
Chip Enable (E). The chip enable input must be  
low to enable all read/write operations. When Chip  
Enable is high, power consumption is reduced.  
M28C17  
A2  
8
A10  
E
A1  
9
A0  
10  
11  
12  
13  
14  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
Output Enable (G). The Output Enable input con-  
trols the data output buffers and is used to initiate  
read operations.  
DQ0  
DQ1  
DQ2  
Data In/ Out(DQ0 - DQ7). Data is written to or read  
from the M28C17 through the I/O pins.  
V
SS  
Write Enable (W). The Write Enable input controls  
the writing of data to the M28C17.  
AI01507B  
Ready/Busy (RB). Ready/Busy is an open drain  
output that can be used to detect the end of the  
internal write cycle.  
Warning: NC = Not Connected.  
2/17  
M28C17  
Table 2. Absolute Maximum Ratings (1)  
Symbol  
TA  
Parameter  
Value  
– 40 to 125  
– 65 to 150  
– 0.3 to 6.5  
– 0.3 to VCC +0.6  
– 0.3 to 6.5  
4000  
Unit  
°C  
°C  
V
Ambient Operating Temperature  
Storage Temperature Range  
Supply Voltage  
TSTG  
VCC  
VIO  
Input/Output Voltage  
V
VI  
Input Voltage  
V
VESD  
Electrostatic Discharge Voltage (Human Body model) (2)  
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may  
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions  
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other  
relevant quality documents.  
2. 100pF through 1500; MIL-STD-883C, 3015.7  
Table 3. Operating Modes (1)  
Mode  
E
1
X
X
0
0
G
X
1
W
X
X
1
DQ0 - DQ7  
Hi-Z  
Standby  
Output Disable  
Write Disable  
Read  
Hi-Z  
X
0
Hi-Z  
1
Data Out  
Data In  
Write  
1
0
Chip Erase  
0
V
0
Hi-Z  
Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH; V = 12 ± 5%.  
OPERATION  
Page Write  
In order to prevent data corruption and inadvertent  
writeoperationsaninternalVCCcomparatorinhibits  
Write operation if VCC is below VWI (see Table 7).  
Accesstothememoryinwritemodeisallowedafter  
a power-up as specified in Table 7.  
Page write allows up to 64 bytes to be consecu-  
tively latched into the memory prior to initiating a  
programming cycle. All bytes must be located in a  
single page address, that is A6-A10 must be the  
same for all bytes. The page write can be initiated  
during any byte write operation.  
Read  
Following the first byte write instruction the host  
may send another address and data with a mini-  
mum data transfer rate of 1/tWHWH (see Figure 13).  
If atransitionof Eor Wisnotdetected within tWHWH  
the internal programming cycle will start.  
The M28C17 is accessed like a static RAM. When  
E and G are low with W high, the data addressed  
is presented on the I/O pins. The I/O pins are high  
impedance when either G or E is high.  
,
Write  
Chip Erase  
Write operations are initiated when both W and E  
are low and G is high.The M28C17 supports both  
E and W controlled write cycles. The Address is  
latched by the falling edge of E or W which ever  
occurs last and the Data on the rising edge of E or  
W which ever occurs first. Once initiated the write  
operation is internally timed until completion.  
The contents of the entire memory may be erased  
to FFh by use of the Chip Erase command by  
setting Chip Enable (E) Low and Output Enable  
(G) to VCC + 7.0V. The chip is cleared when a 10ms  
low pulse is applied to the Write Enable pin.  
3/17  
M28C17  
Figure 3. Block Diagram  
RB  
E
G
W
V
GEN  
RESET  
CONTROL LOGIC  
PP  
ADDRESS  
LATCH  
A6-A10  
(Page Address)  
64K ARRAY  
ADDRESS  
LATCH  
A0-A5  
Y
DECODE  
SENSE AND DATA LATCH  
I/O BUFFERS  
PAGE LOAD  
TIMER STATUS  
TOGGLE BIT  
DATA POLLING  
DQ0-DQ7  
AI01488  
Microcontroller Control Interface  
ished the true logic value appears on DQ7 in the  
read cycle.  
The M28C17 provides two write operation status  
bits andone status pinthat can be used to minimize  
the system write cycle. These signals are available  
on the I/O port bits DQ7 or DQ6 of the memory  
during programming cycle only, or as the RB signal  
on a separate pin.  
Toggle bit (DQ6). The M28C17 offers another way  
for determining when the internal write cycle is  
completed. During the internal Erase/Write cycle,  
DQ6 will toggle from "0" to "1" and "1" to "0" (the  
first read value is "0") on subsequent attempts to  
read the memory. When the internal cycle is com-  
pleted the toggling will stop and the device will be  
accessible for a new Read or Write operation.  
Figure 4. Status Bit Assignment  
Page Load Timer Status bit (DQ5). In the Page  
Write mode data may be latched by E or W. Up to  
64 bytes may be input. The Data output (DQ5)  
indicates the status of the internal Page Load  
Timer. DQ5 may be read by asserting Output En-  
able Low (tPLTS). DQ5 Low indicates the timer is  
running, High indicates time-out after which the  
write cycle will start and no new data may be input.  
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0  
DP  
TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z  
DP = Data Polling  
TB = Toggle Bit  
PLTS = Page Load Timer Status  
Data Polling bit (DQ7). During the internal write  
cycle, any attempt to read the last byte written will  
produce on DQ7 the complementary value of the  
previously latched bit. Once the write cycle is fin-  
Ready/Busy pin. The RB pin provides a signal at  
its open drain output which is low during the  
erase/write cycle, but which is released at the  
completion of the programming cycle.  
4/17  
M28C17  
Figure 5. Software Data Protection Enable Algorithm and Memory Write  
WRITE AAh in  
Address 555h  
WRITE AAh in  
Address 555h  
Page  
Write  
Instruction  
(Note 1)  
Page  
Write  
Instruction  
(Note 1)  
WRITE 55h in  
Address 2AAh  
WRITE 55h in  
Address 2AAh  
WRITE A0h in  
Address 555h  
WRITE A0h in  
Address 555h  
WRITE  
is enabled  
SDP is set  
Write Page  
(1 up to 64 bytes)  
SDP ENABLE ALGORITHM  
WRITE IN MEMORY  
WHEN SDP IS SET  
AI01509B  
Note: 1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.  
Software Data Protection  
Figure 6. Software Data Protection Disable  
Algorithm  
The M28C17 offers a software controlled write  
protection facility that allows the user to inhibit all  
write modes to the device including the Chip Erase  
instruction. This can be useful in protecting the  
memory from inadvertent write cycles that may  
occur due to uncontrolled bus conditions.  
WRITE AAh in  
Address 555h  
The M28C17 is shipped as standard in the "unpro-  
tected" state meaning that the memory contents  
can be changed as required by the user. After the  
Software Data Protection enable algorithm is is-  
sued, the device enters the "Protect Mode" of  
operation where no further write commands have  
any effect on the memory contents. The device  
remains in this mode until a valid Software Data  
Protection (SDP) disable sequence is received  
whereby the device reverts to its "unprotected"  
state. The Software Data Protection is fully non-  
volatile and is not changed by power on/off se-  
quences.  
To enable the Software Data Protection (SDP) the  
device requiresthe usertowrite(with aPageWrite)  
three specific data bytes to three specific memory  
locations as per Figure 5. Similarly to disable the  
Software Data Protection the user has to write  
specific data bytesinto six differentlocations asper  
Figure 6 (with a Page Write). This complex series  
ensures that the user will never enable or disable  
the Software Data Protection accidentally.  
WRITE 55h in  
Address 2AAh  
WRITE 80h in  
Address 555h  
Page  
Write  
Instruction  
WRITE AAh in  
Address 555h  
WRITE 55h in  
Address 2AAh  
WRITE 20h in  
Address 555h  
Unprotected State  
AI01510  
5/17  
M28C17  
Table 4. AC Measurement Conditions  
Figure 8. AC Testing Equivalent Load Circuit  
Input Rise and Fall Times  
20ns  
1.3V  
Input Pulse Voltages  
0.4V to 2.4V  
0.8V to 2.0V  
1N914  
Input and Output Timing Ref. Voltages  
Note that Output Hi-Z is defined as the point where data is no  
longer driven.  
3.3kΩ  
Figure 7. AC Testing Input Output Waveforms  
DEVICE  
UNDER  
TEST  
OUT  
2.4V  
C
= 30pF  
L
2.0V  
0.8V  
0.4V  
C
includes JIG capacitance  
L
AI00826  
AI01129  
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )  
Symbol  
CIN  
Parameter  
Input Capacitance  
Output Capacitance  
Test Condition  
VIN = 0V  
Min  
Max  
6
Unit  
pF  
COUT  
VOUT = 0V  
12  
pF  
Note: 1. Sampled only, not 100% tested.  
Table 6. Read Mode DC Characteristics  
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)  
Symbol  
ILI  
Parameter  
Input Leakage Current  
Test Condition  
0V VIN VCC  
Min  
Max  
10  
Unit  
µA  
µA  
mA  
mA  
mA  
µA  
V
ILO  
Output Leakage Current  
Supply Current (TTL inputs)  
Supply Current (CMOS inputs)  
Supply Current (Standby) TTL  
Supply Current (Standby) CMOS  
Input Low Voltage  
0V VIN VCC  
10  
E = VIL, G = VIL , f = 5 MHz  
E = VIL, G = VIL , f = 5 MHz  
E = VIH  
30  
(1)  
ICC  
25  
(1)  
ICC1  
1
(1)  
ICC2  
E > VCC –0.3V  
100  
0.8  
VIL  
VIH  
– 0.3  
2
Input High Voltage  
VCC +0.5  
0.4  
V
VOL  
VOH  
Output Low Voltage  
IOL = 2.1 mA  
V
Output High Voltage  
IOH = –400 µA  
2.4  
V
Note: 1. All I/O’s open circuit.  
Table 7. Power Up Timing (1) (TA = 0 to 70°C or –40 to 85°C)  
Symbol  
tPUR  
Parameter  
Time Delay to Read Operation  
Min  
1
Max  
Unit  
µs  
ms  
V
tPUW  
Time Delay to Write Operation (once VCC 4.5V)  
10  
3.0  
VWI  
Write Inhibit Threshold  
4.2  
Note: 1. Sampled only, not 100% tested.  
6/17  
M28C17  
Table 8. Read Mode AC Characteristics  
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)  
M28C17  
-120  
Test  
Condition  
Symbol  
Alt  
Parameter  
Unit  
-90  
-150  
min  
max  
min  
max  
min  
max  
Address Valid to  
Output Valid  
E = VIL,  
G = VIL  
tAVQV  
tELQV  
tGLQV  
tACC  
tCE  
tOE  
tDF  
90  
120  
120  
45  
150  
150  
50  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Low to  
Output Valid  
G = VIL  
E = VIL  
G = VIL  
E = VIL  
90  
40  
40  
40  
Output Enable Low  
to Output Valid  
Chip Enable High  
to Output Hi-Z  
(1)  
tEHQZ  
0
0
0
0
0
0
45  
0
0
0
50  
Output Enable High  
to Output Hi-Z  
(1)  
tGHQZ  
tDF  
45  
50  
Address Transition  
to Output Transition  
E = VIL,  
G = VIL  
tAXQX  
tOH  
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.  
Figure 9. Read Mode AC Waveforms  
A0-A10  
E
VALID  
tAVQV  
tAXQX  
tGLQV  
tEHQZ  
tGHQZ  
G
tELQV  
Hi-Z  
DQ0-DQ7  
DATA OUT  
AI01511B  
Note: Write Enable (W) = High  
7/17  
M28C17  
Table 9. Write Mode AC Characteristics  
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)  
Symbol  
tAVWL  
Alt  
tAS  
Parameter  
Test Condition  
E = VIL, G = VIH  
G = VIH, W = VIL  
G = VIH  
Min  
0
Max  
Unit  
ns  
Address Valid to Write Enable Low  
Address Valid to Chip Enable Low  
Chip Enable Low to Write Enable Low  
tAVEL  
tAS  
0
ns  
tELWL  
tCES  
0
ns  
Output Enable High to Write Enable  
Low  
tGHWL  
tOES  
E = VIL  
0
ns  
tGHEL  
tWLEL  
tWLAX  
tELAX  
tWLDV  
tELDV  
tELEH  
tWHEH  
tOES  
tWES  
tAH  
Output Enable High to Chip Enable Low  
Write Enable Low to Chip Enable Low  
Write Enable Low to Address Transition  
Chip Enable Low to Address Transition  
Write Enable Low to Input Valid  
W = VIL  
G = VIH  
0
0
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ns  
50  
50  
tAH  
tDV  
E = VIL, G = VIH  
G = VIH, W = VIL  
1
1
tDV  
Chip Enable Low to Input Valid  
tWP  
tCEH  
Chip Enable Low to Chip Enable High  
Write Enable High to Chip Enable High  
50  
0
Write Enable High to Output Enable  
Low  
tWHGL  
tOEH  
0
ns  
tEHGL  
tEHWH  
tWHDX  
tEHDX  
tWHWL  
tWLWH1  
tWHWH  
tWHRH  
tWHRL  
tEHRL  
tOEH  
tWEH  
tDH  
Chip Enable High to Output Enable Low  
Chip Enable High to Write Enable High  
Write Enable High to Input Transition  
Chip Enable High to Input Transition  
Write Enable High to Write Enable Low  
Write Enable Low to Write Enable High  
Byte Load Repeat Cycle Time  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ms  
ns  
ns  
ns  
ns  
0
tDH  
0
tWPH  
tWP  
tBLC  
tWC  
tDB  
50  
50  
0.15  
100  
3
Write Cycle Time  
Write Enable High to Ready/Busy Low  
Chip Enable High to Ready/Busy Low  
Data Valid before Write Enable High  
Data Valid before Chip Enable High  
Note 1  
Note 1  
150  
150  
tDB  
tDVWH  
tDVEH  
tDS  
50  
50  
tDS  
Note: 1. With a 3.3 kexternal pull-up resistor.  
8/17  
M28C17  
Figure 10. Write Mode AC Waveforms - Write Enable Controlled  
A0-A10  
VALID  
tAVWL  
tELWL  
tGHWL  
tWLAX  
E
tWHEH  
tWHGL  
G
tWLWH1  
W
tWLDV  
tWHWL  
DATA IN  
tDVWH  
DQ0-DQ7  
tWHDX  
RB  
tWHRL  
AI01128  
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled  
A0-A10  
VALID  
tAVEL  
tGHEL  
tWLEL  
tELAX  
E
tELEH  
G
tEHGL  
W
tELDV  
tEHWH  
DATA IN  
tDVEH  
DQ0-DQ7  
tEHDX  
RB  
tEHRL  
AI01513  
9/17  
M28C17  
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled  
A0-A10  
Addr 0  
Addr 1  
Addr 2  
Addr n  
E
tPLTS  
G
tWHWL  
tWHRH  
W
tWLWH  
tWHWH  
Byte 2  
tWHWH  
Byte 0  
Byte 1  
Byte n  
DQ0-DQ7  
DQ5  
Byte n  
tWHRL  
RB  
AI01514  
Figure 13. Software Protected Write Cycle Waveforms  
G
E
tWLWH  
tWHWL  
tWHWH  
W
tAVEL  
tWLAX  
2AAh  
A0-A5  
Byte Address  
Page Address  
Byte 0  
tWHDX  
555h  
A6-A10  
DQ0-DQ7  
555h  
tDVWH  
AAh  
55h  
A0h  
Byte 62  
Byte 63  
AI01515  
Note: A6 through A10 must specify the same page address during each high to low transition of W (or E) after the software code has been  
entered. G must be high only when W and E are both low.  
10/17  
M28C17  
Figure 14. Data Polling Waveform Sequence  
A0-A10  
Address of the last byte of the Page Write instruction  
E
G
W
DQ7  
DQ7  
DQ7  
DQ7  
DQ7  
DQ7  
LAST WRITE  
INTERNAL WRITE SEQUENCE  
READY  
AI01516  
Figure 15. Toggle Bit Waveform Sequence  
A0-A10  
E
G
W
DQ6  
(1)  
LAST WRITE  
TOGGLE  
READY  
INTERNAL WRITE SEQUENCE  
AI01517  
Note: 1. First Toggle bit is forced to ’0’.  
11/17  
M28C17  
Figure 16. Chip Erase Wavforms  
tWHEH  
E
G
tGLWH  
W
tELWL  
tWLWH2  
tWHRH  
AI01484B  
Table 10. Chip Erase AC Characteristics  
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)  
Symbol  
tELWL  
Parameter  
Test Condition  
G = VCC + 7V  
G = VCC + 7V  
G = VCC + 7V  
G = VCC + 7V  
G = VCC + 7V  
Min  
1
Max  
Unit  
Chip Enable Low to Write Enable Low  
Write Enable High to Chip Enable High  
Write Enable Low to Write Enable High  
Output Enable Low to Write Enable High  
Write Enable High to Write Enable Low  
µs  
ns  
tWHEH  
tWLWH2  
tGLWH  
0
10  
1
ms  
µs  
tWHRH  
3
ms  
12/17  
M28C17  
ORDERING INFORMATION SCHEME  
Example: M28C17  
-90 K  
1
T
Speed  
Package  
Temperature Range  
Option  
-90  
-120  
-150  
90ns  
P
K
PDIP28  
1
6
0 to 70 °C  
T
Tape & Reel  
Packing  
120ns  
150ns  
PLCC32  
–40 to 85 °C  
MS SO28 300mils  
Devices are shipped from the factory with the memory content set at all "1’s" (FFh).  
For a list of available options (Package, etc...) or for further information on any aspect of this device, please  
contact the SGS-THOMSON Sales Office nearest to you.  
13/17  
M28C17  
PDIP28 - 28 pin Plastic DIP, 600 mils width  
mm  
Min  
3.94  
0.38  
3.56  
0.38  
1.14  
0.20  
34.70  
14.80  
12.50  
inches  
Symb  
Typ  
Max  
5.08  
1.78  
4.06  
0.56  
1.78  
0.30  
37.34  
16.26  
13.97  
Typ  
Min  
0.155  
0.015  
0.140  
0.015  
0.045  
0.008  
1.366  
0.583  
0.492  
Max  
0.200  
0.070  
0.160  
0.021  
0.070  
0.012  
1.470  
0.640  
0.550  
A
A1  
A2  
B
B1  
C
D
E
E1  
e1  
eA  
L
2.54  
0.100  
15.20  
3.05  
1.02  
0°  
17.78  
3.82  
2.29  
15°  
0.598  
0.120  
0.040  
0°  
0.700  
0.150  
0.090  
15°  
S
α
N
28  
28  
PDIP28  
A2  
A
A1  
e1  
L
B1  
B
D
α
C
eA  
S
N
1
E1  
E
PDIP  
Drawing is not to scale.  
14/17  
M28C17  
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular  
mm  
Min  
2.54  
1.52  
0.33  
0.66  
12.32  
11.35  
9.91  
14.86  
13.89  
12.45  
inches  
Min  
Symb  
Typ  
Max  
3.56  
2.41  
0.53  
0.81  
12.57  
11.56  
10.92  
15.11  
14.10  
13.46  
Typ  
Max  
0.140  
0.095  
0.021  
0.032  
0.495  
0.455  
0.430  
0.595  
0.555  
0.530  
A
A1  
B
0.100  
0.060  
0.013  
0.026  
0.485  
0.447  
0.390  
0.585  
0.547  
0.490  
B1  
D
D1  
D2  
E
E1  
E2  
e
1.27  
0.89  
0.050  
0.035  
j
N
32  
32  
Nd  
Ne  
CP  
7
7
9
9
0.10  
0.004  
PLCC32  
D
A1  
D1  
j
1 N  
B1  
e
Ne  
E1 E  
D2/E2  
B
Nd  
A
CP  
PLCC  
Drawing is not to scale.  
15/17  
M28C17  
SO28 - 28 lead Plastic Small Outline, 300 mils body width  
mm  
Min  
2.46  
0.13  
2.29  
0.35  
0.23  
17.81  
7.42  
inches  
Min  
Symb  
Typ  
Max  
2.64  
0.29  
2.39  
0.48  
0.32  
18.06  
7.59  
Typ  
Max  
0.104  
0.011  
0.094  
0.019  
0.013  
0.711  
0.299  
A
A1  
A2  
B
0.097  
0.005  
0.090  
0.014  
0.009  
0.701  
0.292  
C
D
E
e
1.27  
0.050  
H
L
10.16  
0.61  
0°  
10.41  
1.02  
8°  
0.400  
0.024  
0°  
0.410  
0.040  
8°  
α
N
28  
28  
CP  
0.10  
0.004  
SO28  
A2  
A
C
B
CP  
e
D
N
1
E
H
A1  
α
L
SO-b  
Drawing is not to scale.  
16/17  
M28C17  
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No  
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned  
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.  
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express  
written approval of SGS-THOMSON Microelectronics.  
© 1997 SGS-THOMSON Microelectronics - All Rights Reserved  
SGS-THOMSON Microelectronics GROUP OF COMPANIES  
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -  
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.  
17/17  

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