M28C64-90WNS1 [STMICROELECTRONICS]
8KX8 EEPROM 3V, 90ns, PDSO28, 8 X 13.40 MM, PLASTIC, TSOP-28;型号: | M28C64-90WNS1 |
厂家: | ST |
描述: | 8KX8 EEPROM 3V, 90ns, PDSO28, 8 X 13.40 MM, PLASTIC, TSOP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
文件: | 总21页 (文件大小:138K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M28C64
64 Kbit (8K x 8) Parallel EEPROM
With Software Data Protection
■ Fast Access Time:
– 90 ns at V =5V for M28C64 and M28C64-A
CC
– 120 ns at V =3V for M28C64-xxW
CC
■ Single Supply Voltage:
– 4.5 V to 5.5 V for M28C64 and M28C64-A
– 2.7 V to 3.6 V for M28C64-xxW
■ Low Power Consumption
28
1
■ Fast BYTE and PAGE WRITE (up to 64 Bytes)
PLCC32 (KA)
PDIP28 (BS)
– 1 ms at V =4.5V for M28C64-A
CC
– 3 ms at V =4.5V for M28C64
CC
– 5 ms at V =2.7V for M28C64-xxW
CC
■ Enhanced Write Detection and Monitoring:
– Ready/Busy Open Drain Output
– Data Polling
28
1
– Toggle Bit
SO28 (MS)
300 mil width
TSOP28 (NS)
8 x 13.4 mm
– Page Load Timer Status
■ JEDEC Approved Bytewide Pin-Out
■ Software Data Protection
■ 100000 Erase/Write Cycles (minimum)
■ Data Retention (minimum):
– 40 Years for M28C64 and M28C64-xxW
– 10 Years for M28C64-A
Figure 1. Logic Diagram
V
CC
Table 1. Signal Names
13
8
A0-A12
Address Input
Data Input / Output
Write Enable
A0-A12
DQ0-DQ7
DQ0-DQ7
W
E
W
E
M28C64
Chip Enable
RB
G
Output Enable
Ready / Busy
Supply Voltage
G
RB
V
CC
V
SS
V
AI01350C
Ground
SS
January 1999
1/21
M28C64
Figure 2C. SO Connections
Figure 2A. DIP Connections
RB
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
RB
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 NC
25 A8
24 A9
23 A11
3
NC
A8
A6
A6
4
A5
A5
5
A9
A4
A4
6
A11
G
A3
22
G
A3
7
M28C64
M28C64
A2
21 A10
20
A2
8
A10
E
A1
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
SS
V
SS
AI01351C
AI01353C
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
Figure 2B. PLLC Connections
Figure 2D. TSOP Connections
G
A11
A9
22
21
A10
E
1 32
DQ7
DQ6
DQ5
DQ4
DQ3
A6
A8
A8
A5
A4
A3
A9
NC
W
A11
NC
G
V
28
1
15
14
CC
RB
M28C64
A2
A1
9
M28C64
25
V
SS
A10
E
A12
A7
A6
A5
A4
A3
DQ2
DQ1
DQ0
A0
A0
NC
DQ7
DQ6
DQ0
17
A1
7
8
A2
AI01354C
AI01352D
Note: 1. NC = Not Connected
2. DU = Do Not Use
Note: 1. NC = Not Connected
DESCRIPTION
and software handshaking, with Ready/Busy,
Data Polling and Toggle Bit. The device supports
a 64 byte Page Write operation. Software Data
Protection (SDP) is also supported, usingthe stan-
dard JEDEC algorithm.
The M28C64 devices consist of 8192x8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary single polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a sin-
gle voltage supply (5V or 3V, depending on the op-
tion chosen).
The device has been designed to offer a flexible
microcontroller interface, featuring both hardware
2/21
M28C64
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
-40 to 125
-65 to 150
-0.3 to VCC+1
-0.6 to VCC+0.6
-0.3 to 6.5
4000
Unit
°C
°C
V
TA
TSTG
VCC
VIO
VI
Ambient Operating Temperature
Storage Temperature
Supply Voltage
Input or Output Voltage
Input Voltage
V
V
2
VESD
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
Figure 3. Block Diagram
RB
E
G
W
V
GEN
RESET
CONTROL LOGIC
PP
ADDRESS
LATCH
A6-A12
(Page Address)
64K ARRAY
ADDRESS
LATCH
A0-A5
Y
DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01355
3/21
M28C64
1
Table 3. Operating Modes
Mode
E
1
X
X
0
0
0
G
X
1
W
X
X
1
DQ0-DQ7
Hi-Z
Stand-by
Output Disable
Write Disable
Read
Hi-Z
X
0
Hi-Z
1
Data Out
Data In
Hi-Z
Write
1
0
Chip Erase
V
0
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V ± 5%.
SIGNAL DESCRIPTION
The external connections to the device are sum-
marized in Table 1, and their use in Table 3.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the in-
ternal write cycle.
Addresses (A0-A12). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V
hibits the Write operations if the V
comparator in-
CC
CC
voltage is
lower than V (see Table 4A and Table 4B). Once
WI
the voltage applied on the V
pin goes over the
CC
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input con-
trols the data output buffers, and is used to initiate
read operations.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
V
threshold (V >V ), write access to the
WI
CC WI
memory is allowed after a time-out t
, as spec-
PUW
ified in Table 4A and Table 4B.
Further protection against data corruption is of-
fered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
1
Table 4A. Power-Up Timing for M28C64 (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Min.
Max.
1
Unit
µs
t
Time Delay to Read Operation
Time Delay to Write Operation (once VCC ≥ VWI
Write Inhibit Threshold
PUR
t
)
10
ms
V
PUW
VWI
3.0
4.2
Note: 1. Sampled only, not 100% tested.
1
Table 4B. Power-Up Timing for M28C64-xxW (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Min.
Max.
1
Unit
µs
t
Time Delay to Read Operation
Time Delay to Write Operation (once VCC ≥ VWI
Write Inhibit Threshold
PUR
t
)
15
ms
V
PUW
VWI
1.5
2.5
Note: 1. Sampled only, not 100% tested.
4/21
M28C64
Read
The page write can be initiated during any byte
write operation. Following the first byte write in-
struction the host may send another address and
data with a minimum data transfer rate of:
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
1/t
.
WLQ5H
The internal write cycle can start at any instant af-
ter t . Onceinitiated, the write operation is in-
WLQ5H
Write
ternally timed, and continues, uninterrupted, until
completion.
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first). Af-
All bytes must be located on the same page ad-
dress (A12-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not execut-
ed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
ter a delay, t
, that cannot be shorter than the
WLQ5H
value specified in Table 10A and Table 10B, the
internal write cycle starts. It continues, under inter-
nal timing control, until the write operation is com-
plete. The commencement of this period can be
detected by reading the Page Load Timer Status
on DQ5. The end of the cycle can be detected by
reading the status of the Data Polling and the Tog-
gle Bit functions on DQ7 and DQ6.
Software Data Protection (SDP)
The device offers a software-controlled write-pro-
tection mechanism that allows the user to inhibit all
write operations to the device. This can be useful
for protecting the memory from inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write op-
erations, no two of which are separated by more
than the t
and Table 10B).
By default, the device is shipped in the “unprotect-
ed” state: the memory contents can be freely
changed by the user. Once the SoftwareData Pro-
tection Mode is enabled, all write commands are
value (as specified in Table 10A
WLQ5H
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Write AAh in
Write AAh in
Address 1555h
Address 1555h
Page Write
Timing
(see note 1)
Page Write
Timing
(see note 1)
Write 55h in
Address 0AAAh
Write 55h in
Address 0AAAh
Write A0h in
Write A0h in
Address 1555h
Address 1555h
Write
is enabled
SDP is set
Physical
Page Write
Instruction
Page Write
(1 up to 64 bytes)
SDP Enable Algorithm
WRITE to Memory
When SDP is SET
AI01356C
Note: 1. The most significant address bits (A12 to A6) differ during these specific Page Write operations.
5/21
M28C64
Figure 5. Software Data Protection Disable Algorithm
Write AAh in
Address 1555h
Write 55h in
Address 0AAAh
Write 80h in
Address 1555h
Page Write
Timing
Write AAh in
Address 1555h
Write 55h in
Address 0AAAh
Write 20h in
Address 1555h
Unprotected State
AI01357B
Software Chip Erase
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft-
ware Data Protection disable sequence is re-
ceived. The device reverts to its “unprotected”
state.
The status of the Software Data Protection (en-
abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
Using this function, available on the M28C64 but
not on the M28C64-A or M28C64-xxW, the con-
tents of the entire memory are erased (set to FFh)
by holding Chip Enable (E) low, and holding Out-
put Enable (G) at V +7.0V. The chip is cleared
CC
when a 10 ms low pulse is applied to the Write En-
able (W) signal (see Figure 7 and Table 5 for de-
tails).
Status Bits
The devices provide three status bits (DQ7, DQ6
and DQ5), and one output pin (RB), for use during
write operations. These allow the application to
use the write time latency of the device for getting
on with other work. These signals are available on
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the userhas to write specific data bytes into six dif-
ferent locations, as shown in Figure 5. This com-
plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
Figure 6. Status Bit Assignment
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from inad-
vertent use). The sequence is as shown in Figure
4. This consists of an unlock key, to enable the
write action, at the end of which theSDP continues
to be enabled. This allows the SDP to be enabled,
and data to be written, within a single Write cycle
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z Hi-Z
Hi-Z
DP
TB
= Data Polling
= Toggle Bit
PLTS = Page Load Timer Status
Hi-Z = High impedance
(t ).
WC
AI02815
6/21
M28C64
Figure 7. Chip Erase AC Waveforms (M28C64 and M28C64-xxW)
tWHEH
E
G
tGLWH
W
tELWL
tWLWH2
tWHRH
AI01484B
1
Table 5. Chip Erase AC Characteristics for M28C64 and M28C64-xxW
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V or 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
G = VCC + 7V
G = VCC + 7V
G = VCC + 7V
G = VCC + 7V
G = VCC + 7V
Min.
Max.
Unit
µs
t
Chip Enable Low to Write Enable Low
Write Enable High to Chip Enable High
Write Enable Low to Write Enable High
Output Enable Low to Write Enable High
Write Enable High to Write Enable Low
1
0
ELWL
t
ns
WHEH
t
10
1
ms
µs
WLWH2
t
GLWH
t
3
ms
WHRH
Note: 1. Sampled only, not 100% tested.
the I/O port bits DQ7, DQ6 and DQ5 (but only dur-
ing programming cycle, once a byte or more has
been latched into the memory) or continuously on
the RB output pin.
device is again available for new Read and Write
operations.
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period between suc-
Data Polling bit (DQ7). The internally timed write
cessive Write operations, up to t
(defined in
WLQ5H
cycle starts after t
(defined in Table 10A and
Table 10A and Table 10B). The DQ5 line is held
low to show when this timer is running (hence
showing that the device has received one write op-
eration, and is waiting for the next). The DQ5 line
is held high when the counter has overflowed
(hence showing that the device is now starting the
internal write to the memory array).
Ready/Busy pin. The RBpin is an open drain out-
put that is held low during the erase/write cycle,
and that is released (allowed to float) at the com-
pletion of the programming cycle.
WLQ5H
Table 10B) has elapsed since the previous byte
was latched in to the memory. The value of the
DQ7 bit of this last byte, is used as a signal
throughout this write operation: it is inverted while
the internal write operation is underway, and is in-
verted back to its original value once the operation
is complete.
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first
read value being ’0’) on subsequent attempts to
read any byte of the memory. When the internal
write cycle is complete, the toggling is stopped,
and the values read on DQ7-DQ0 are those of the
addressed memory byte. This indicates that the
7/21
M28C64
Table 6A. Read Mode DC Characteristics for M28C64 and M28C64-A (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
10
Unit
µA
ILI
ILO
0 V ≤ VOUT ≤ VCC
10
µA
Supply Current (TTL inputs)
Supply Current (CMOS inputs)
Supply Current (Stand-by) TTL
E = VIL, G = VIL , f = 5 MHz
E = VIL, G = VIL , f = 5 MHz
30
mA
mA
1
ICC
25
1
E = V
1
mA
ICC1
IH
1
Supply Current (Stand-by) CMOS
E > VCC - 0.3V
100
µA
ICC2
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.3
2
0.8
CC + 0.5
0.4
V
V
V
V
V
I
OL = 2.1 mA
IOH = -400 µA
2.4
Note: 1. All inputs and outputs open circuit.
Table 6B. Read Mode DC Characteristics for M28C64-xxW (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
10
10
8
Unit
µA
ILI
ILO
0 V ≤ VOUT ≤ VCC
µA
E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V
E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V
E > VCC - 0.3V
mA
mA
µA
1
Supply Current (CMOS inputs)
ICC
10
20
1
Supply Current (Stand-by) CMOS
ICC2
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.3
2
0.6
V
V
V
V
V
CC + 0.5
IOL = 1.6 mA
0.2 VCC
IOH = -400 µA
0.8 VCC
Note: 1. All inputs and outputs open circuit.
8/21
M28C64
1
Table 7. Input and Output Parameters (T = 25 °C, f = 1 MHz)
A
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0 V
Min.
Max.
6
Unit
pF
COUT
VOUT = 0 V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 8. AC Measurement Conditions
Input Rise and Fall Times
≤ 20 ns
Input Pulse Voltages (M28C64, M28C64-A)
Input Pulse Voltages (M28C64-xxW)
0.4 V to 2.4 V
0 V to V -0.3V
CC
Input and Output Timing Reference Voltages (M28C64, M28C64-A)
Input and Output Timing Reference Voltages (M28C64-xxW)
0.8 V to 2.0 V
0.5 V
CC
Figure 8. AC Testing Input Output Waveforms
Figure 9. AC Testing Equivalent Load Circuit
4.5V to 5.5V Operating Voltage
2.4V
2.0V
0.8V
I
OL
0.4V
DEVICE
UNDER
TEST
OUT
2.7V to 3.6V Operating Voltage
I
OH
V
– 0.3V
C
= 100pF
CC
L
0.5 V
CC
0V
AI02101B
C
includes JIG capacitance
L
AI02102B
Table 9A. Read Mode AC Characteristics for M28C64 and M28C64-A (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
M28C64
-12
Test
Condit
ion
Symbol
Alt.
Parameter
-90
-15
Unit
Min
Max
Min
Max
Min
Max
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
90
120
150
ns
AVQV
G = V
G = V
E = V
IL
t
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
90
40
40
120
45
150
50
ns
ns
ns
ELQV
CE
IL
t
t
GLQV
OE
IL
1
t
G = V
0
0
0
0
45
0
0
50
t
DF
IL
IL
EHQZ
1
t
E = V
Output Enable High to Output Hi-Z
40
45
50
ns
ns
t
DF
GHQZ
E = V ,
Address Transition to Output
Transition
IL
t
t
0
0
0
AXQX
OH
G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
9/21
M28C64
Table 9B. Read Mode AC Characteristics for M28C64-xxW (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
M28C64-xxW
-20
Test
Condit
ion
Symbol Alt.
Parameter
-12
-15
-25
-30
Unit
Min Max Min Max Min Max Min Max Min Max
E =V ,
Address Valid to
Output Valid
IL
t
t
ACC
120
120
80
150
150
80
200
200
100
55
250
250
150
60
300
300
150
60
ns
ns
ns
ns
ns
ns
AVQV
G = V
IL
Chip Enable Low to
Output Valid
t
t
CE
G = V
ELQV
IL
Output Enable Low
to Output Valid
t
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
1
t
t
t
G = V
0
0
0
45
0
0
0
50
0
0
0
0
0
0
0
0
0
t
DF
DF
IL
EHQZ
Output Enable High
to Output Hi-Z
1
E = V
45
50
55
60
60
t
IL
GHQZ
E =V ,
Address Transition
IL
t
AXQX
OH
to Output Transition G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 10. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A12
E
VALID
tAVQV
tAXQX
tGLQV
tEHQZ
G
tELQV
tGHQZ
Hi-Z
DQ0-DQ7
DATA OUT
AI00749B
Note: 1. Write Enable (W) = V
IH
10/21
M28C64
Table 10A. Write Mode AC Characteristics for M28C64 and M28C64-A (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
M28C64
Max
Symbol
Alt.
Parameter
Test Condition
Unit
Min
0
t
t
E = V , G = V
IH
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
ns
ns
AVWL
AS
IL
t
t
G = V , W = V
0
AVEL
AS
IH
IL
t
t
G = V
0
ELWL
CES
IH
t
t
E = V
IL
0
GHWL
OES
t
t
W = V
IL
0
GHEL
OES
t
t
G = V
0
WLEL
WLAX
WES
IH
t
t
50
50
AH
t
t
ELAX
AH
t
t
E = V , G = V
IL
1
1
WLDV
DV
IH
t
t
G = V , W = V
Chip Enable Low to Input Valid
ELDV
ELEH
WHEH
DV
IH
IL
t
t
WP
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out after last byte write (M28C64)
Time-out after last byte write (M28C64-A)
Write Cycle Time (M28C64)
50
0
t
t
CEH
OEH
OEH
t
t
t
0
WHGL
t
0
EHGL
EHWH
WHDX
t
t
t
0
WEH
t
0
DH
t
t
0
EHDX
DH
t
t
WPH
50
50
100
20
1000
WHWL
t
t
WLWH
WP
t
t
BLC
WLQ5H
3
t
t
WC
Q5HQ5X
Write Cycle Time (M28C64-A)
1
t
t
t
Write Enable High to Ready/Busy Low
Chip Enable High to Ready/Busy Low
Data Valid before Write Enable High
Data Valid before Chip Enable High
Note 1
Note 1
150
150
WHRL
DB
DB
DS
DS
t
t
t
t
EHRL
50
50
DVWH
t
DVEH
Note: 1. With a 3.3 kΩ pull-up resistor.
11/21
M28C64
Table 10B. Write Mode AC Characteristics for M28C64-xxW (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
M28C64-xxW
Min Max
Symbol
Alt.
Parameter
Test Condition
Unit
t
t
E = V , G = V
IH
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
0
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
ns
ns
AVWL
AS
IL
t
t
G = V , W = V
AVEL
AS
IH
IL
t
t
G = V
0
ELWL
CES
IH
t
t
E = V
IL
0
GHWL
OES
t
t
W = V
IL
0
GHEL
OES
t
t
G = V
0
WLEL
WLAX
WES
IH
t
t
100
100
AH
t
t
ELAX
AH
t
t
E = V , G = V
IL
1
1
WLDV
DV
IH
t
t
G = V , W = V
Chip Enable Low to Input Valid
ELDV
ELEH
WHEH
DV
IH
IL
t
t
WP
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out after the last byte write
100
0
1000
t
t
CEH
OEH
OEH
t
t
t
0
WHGL
t
0
EHGL
EHWH
WHDX
t
t
t
0
WEH
t
0
DH
t
t
0
EHDX
DH
t
t
WPH
50
100
100
1000
WHWL
t
t
WLWH
WP
t
t
BLC
WLQ5H
t
t
WC
Write Cycle Time
5
Q5HQ5X
t
t
Write Enable High to Ready/Busy Low
Chip Enable High to Ready/Busy Low
Data Valid before Write Enable High
Data Valid before Chip Enable High
Note 1
Note 1
150
150
WHRL
DB
DB
DS
DS
t
t
t
t
EHRL
t
50
50
DVWH
t
DVEH
Note: 1. With a 3.3 kΩ pull-up resistor.
12/21
M28C64
Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A12
VALID
tAVWL
tELWL
tGHWL
tWLAX
E
tWHEH
tWHGL
G
tWLWH
W
tWLDV
tWHWL
DATA IN
tDVWH
DQ0-DQ7
tWHDX
RB
tWHRL
AI01126
Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A12
VALID
tAVEL
tGHEL
tWLEL
tELAX
E
tELEH
G
tEHGL
W
tELDV
tEHWH
DATA IN
tDVEH
DQ0-DQ7
tEHDX
RB
tEHRL
AI00751
13/21
M28C64
Figure 13. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A12
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
W
tWLWH
Byte 0
Byte 1
Byte 2
Byte n
DQ0-DQ7 (in)
DQ5 (out)
tWHRL
tWLQ5H
tQ5HQ5X
RB
AI00752D
Figure 14. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
W
tAVEL
tWLAX
A0-A5
Byte Address
tWHDX
1555h
A6-A12
DQ0-DQ7
1555h
tDVWH
AAh
0AAAh
Page Address
Byte 0
55h
A0h
Byte 62
Byte 63
AI01358B
Note: 1. A12 to A6 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E
are both low.
14/21
M28C64
Figure 15. Data Polling Sequence Waveforms
A0-A12
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI00753C
Figure 16. Toggle Bit Sequence Waveforms
A0-A12
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE
INTERNAL WRITE SEQUENCE
READY
AI00754D
Note: 1. The Toggle Bit is first set to ‘0’.
15/21
M28C64
Table 11. Ordering Information Scheme
Example:
M28C64
–
A
12
BS
6
T
Write Time
Option
t
t
= 3 ms at 4.5V to 5.5V;
= 5 ms at 2.7V to 3.6V
WC
WC
blank
T
Tape and Reel Packing
1
t
= 1 ms at 4.5V to 5.5V
A
WC
Speed
Temperature Range
0 °C to 70 °C
2
90 ns
1
6
90
12
15
120 ns
150 ns
–40 °C to 85 °C
3
200 ns
250 ns
300 ns
20
3
25
3
Package
PDIP28
30
BS
KA
Operating Voltage
PLCC32
blank 4.5 V to 5.5 V
MS SO28 (300 mil width)
TSOP28 (8 x 13.4 mm)
NS
4
2.7 V to 3.6 V
W
Note: 1. Available only with 120 ns speed (-12), 5V operating range (-blank), and -40 to 85 °C temperature range (-6).
2. Available for the M28C64 only.
3. Available for the 3V range (-xxW) only.
4. Not available for the 1 ms write time option (-A).
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
16/21
M28C64
Table 12. PDIP28 - 28 pin Plastic DIP, 600 mils width
mm
inches
Min.
Symb.
Typ.
Min.
3.94
0.38
3.56
0.38
1.14
0.20
34.70
14.80
12.50
–
Max.
5.08
1.78
4.06
0.56
1.78
0.30
37.34
16.26
13.97
–
Typ.
Max.
0.200
0.070
0.160
0.021
0.070
0.012
1.470
0.640
0.550
–
A
A1
A2
B
0.155
0.015
0.140
0.015
0.045
0.008
1.366
0.583
0.492
–
B1
C
D
E
E1
e1
eA
L
2.54
0.100
15.20
3.05
1.02
0°
17.78
3.82
2.29
15°
0.598
0.120
0.040
0°
0.700
0.150
0.090
15°
S
α
N
28
28
Figure 17. PDIP28 (BS)
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Note: 1. Drawing is not to scale.
17/21
M28C64
Table 13. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
inches
Min.
0.100
0.060
–
Symbol
Typ.
Min.
2.54
1.52
–
Max.
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ.
Max.
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
Figure 18. PLCC (KA)
D
A1
D1
A2
1
N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Note: 1. Drawing is not to scale.
18/21
M28C64
Table 14. SO28 - 28 lead Plastic Small Outline, 300 mils body width
mm
inches
Min.
0.097
0.005
0.090
0.014
0.009
0.701
0.292
–
Symb.
Typ.
Min.
2.46
0.13
2.29
0.35
0.23
17.81
7.42
–
Max.
2.64
0.29
2.39
0.48
0.32
18.06
7.59
–
Typ.
Max.
0.104
0.011
0.094
0.019
0.013
0.711
0.299
–
A
A1
A2
B
C
D
E
e
1.27
0.050
H
10.16
0.61
0°
10.41
1.02
8°
0.400
0.024
0°
0.410
0.040
8°
L
α
N
28
28
CP
0.10
0.004
Figure 19. SO28 wide (MS)
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: 1. Drawing is not to scale.
19/21
M28C64
Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm
mm
inches
Min.
Symb.
Typ.
Min.
Max.
1.25
0.20
1.15
0.27
0.21
13.60
11.90
8.10
–
Typ.
Max.
0.049
0.008
0.045
0.011
0.008
0.535
0.469
0.319
–
A
A1
A2
B
0.95
0.17
0.10
13.20
11.70
7.90
–
0.037
0.007
0.004
0.520
0.461
0.311
–
C
D
D1
E
e
0.55
0.022
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
28
28
CP
0.10
0.004
Figure 20. TSOP32 (NS)
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: 1. Drawing is not to scale.
20/21
M28C64
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
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