M28F101-150N3R [STMICROELECTRONICS]
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| 型号： | M28F101-150N3R |
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ST |
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M28F101
1 Mb (128K x 8, Chip Erase) FLASH MEMORY
5V ±10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMING TIME: 10µs typical
ELECTRICALCHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
32
– Stand-by Current: 100µAmax
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
1
PLCC32 (K)
PDIP32 (P)
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE
– ManufacturerCode: 20h
– Device Code: 07h
TSOP32 (N)
8 x 20 mm
DESCRIPTION
The M28F101 FLASH Memory is a non-volatile
memory which may be erased electrically at the
chip level and programmed byte-by-byte. It is or-
ganisedas128Kbytes of8 bits.It usesa command
register architecture to select the operating modes
and thus provides a simple microprocessor inter-
face. The M28F101 FLASH Memory is suitable for
applications where the memory has to be repro-
grammed in the equipment. The access time of
70ns makes the device suitable for use in high
speed microprocessor systems.
Figure 1. Logic Diagram
V
V
PP
CC
17
8
A0-A16
DQ0-DQ7
Table 1. Signal Names
W
E
M28F101
A0-A16
Address Inputs
Data Inputs / Outputs
Chip Enable
DQ0-DQ7
G
E
G
Output Enable
Write Enable
W
V
SS
AI00666B
VPP
VCC
VSS
Program Supply
Supply Voltage
Ground
April 1997
1/23
M28F101
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
V
1
2
3
4
5
6
7
8
9
32
31
V
CC
W
PP
A16
A15
A12
A7
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
1 32
A7
A14
A13
A8
A6
A5
A4
A6
A5
A9
A4
M28F101
A3
A2
9
M28F101
25 A11
G
A3
24
23 A10
22
G
A2 10
A1 11
A1
A10
E
E
A0
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0
DQ7
DQ0 13
DQ1 14
DQ2 15
17
V
16
SS
AI00668
AI00667
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
Figure 2D. TSOP Reverse Pin Connections
A11
A9
1
32
G
G
A10
E
A11
A9
1
32
A10
E
A8
A8
A13
A14
NC
W
DQ7
DQ6
DQ5
DQ4
DQ3
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
NC
W
V
8
9
M28F101
(Normal)
25
24
8
9
M28F101
(Reverse)
25
24
V
V
CC
PP
CC
V
V
V
SS
PP
SS
A16
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
A16
A15
A12
A7
A15
A12
A7
A6
A1
A1
A6
A5
A2
A2
A5
A4
16
17
A3
A3
16
17
A4
AI00669B
AI00670C
Warning: NC = Not Connected.
Warning: NC = Not Connected.
2/23
M28F101
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Value
–40 to 125
–65 to 150
–0.6 to 7
Unit
°C
°C
V
Ambient Operating Temperature
Storage Temperature
Input or Output Voltages
Supply Voltage
TSTG
VIO
VCC
–0.6 to 7
V
VA9
A9 Voltage
–0.6 to 13.5
V
Program Supply Voltage, during Erase
or Programming
VPP
–0.6 to 14
V
Note: Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION
Output Disable Mode. When the Output Enable
(G) is High the outputs are in a high impedance
state.
The M28F101 FLASH Memory employs atechnol-
ogy similar to a 1 Megabit EPROM but adds to the
device functionality by providing electrical erasure
and programming. These functions are managed
by a command register. The functions that are
addressed via the command register depend on
the voltage applied to the VPP, program voltage,
input. When VPP is less than or equal to 6.5V, the
command register is disabled and M28F101 func-
tions as a read only memory providing operating
modes similar to an EPROM (Read, Output Dis-
able, Electronic Signature Read and Standby).
When VPP is raised to 12V the command regsiter
is enabledand this provides,in addition,Eraseand
Program operations.
ElectronicSignatureMode. This mode allows the
read outof two binary codes from the device which
identify the manufacturer and device type. This
mode is intended for use by programming equip-
ment to automatically select the correct erase and
programming algorithms. The Electronic Signature
Mode is active when a high voltage (11.5V to 13V)
isappliedto addressline A9with Eand G Low. With
A0 Low the output data is the manufacturercode,
when A0 is High the outputis the devicetype code.
All other address lines should be maintained Low
while reading the codes. The electronic signature
may also be accessed in Read/Write modes.
READ ONLY MODES, VPP ≤ 6.5V
READ/WRITE MODES, 11.4V ≤ VPP ≤ 12.6V
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
StandbyMode this input is don’t care.
Read Mode. TheM28F101 has two enable inputs,
E and G, both of which must be Low in order to
output data from the memory. The Chip Enable (E)
is the power control and should be used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independantof the device selection.
Standby Mode. In the Standby Mode the maxi-
mum supply current is reduced. The device is
placed in the StandbyMode by applying a High to
the Chip Enable (E) input. When in the Standby
Mode the outputs are in a high impedance state,
independantof the Output Enable (G) input.
When VPP is High both read and write operations
may be performed. These are defined by the con-
tents of an internal command register. Commands
may be written to this register to set-up and exe-
cute, Erase, Erase Verify, Program, ProgramVerify
and Reset modes. Each of these modes needs 2
cycles. Eah mode starts with a write operation to
set-upthe command,this is followed byeither read
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
data at any location in the memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
Electronic SignatureRead mode is set-up with one
cycle and followed by a read cycle to output the
manufactureror device codes.
3/23
M28F101
(1)
Table 3. Operations
VPP
Operation
Read
E
G
VIL
VIH
X
W
VIH
A9
A9
X
DQ0 - DQ7
Data Output
Hi-Z
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
Output Disable
Standby
VIH
Read Only
VPPL
X
X
Hi-Z
Electronic Signature
Read
VIL
VIL
VIH
VIH
X
VIH
VID
A9
A9
X
Codes
VIH
Data Output
Data Input
Hi-Z
Read/Write (2)
VPPH
Write
VIL Pulse
VIH
Output Disable
Standby
X
X
Hi-Z
Notes: 1. X = VIL or VIH.
2. Refer also to the Command table.
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
VIL
VIH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex Data
20h
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
07h
Table 5. Commands (1)
1st Cycle
A0-A16
X
2nd Cycle
A0-A16
Command
Cycles
Operation
DQ0-DQ7
Operation
DQ0-DQ7
Read
1
2
Write
00h
Read
Read
00000h
00001h
20h
07h
Electronic
Write
Write
X
X
90h
20h
Signature (2)
Setup Erase/
Erase
2
Write
Read
X
X
20h
Erase Verify
Setup Program/
Program
2
2
Write
Write
A0-A16
X
A0h
40h
Data Output
Write
Read
Write
A0-A16
Data Input
Data Output
FFh
Program Verify
2
2
Write
Write
X
X
C0h
FFh
X
X
Reset
Notes: 1. X = VIL or VIH.
2. Refer also to the Electronic Signature table.
4/23
M28F101
Table 6. AC Measurement Conditions
SRAM Interface Levels
EPROM Interface Levels
Input Rise and Fall Times
≤ 10ns
0 to 3V
1.5V
≤ 10ns
Input Pulse Voltages
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
EPROM Interface
C
2.4V
L
2.0V
0.8V
0.45V
C
C
C
= 30pF for SRAM Interface
L
L
L
AI01275
= 100pF for EPROM Interface
includes JIG capacitance
AI01276
Table 7. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
Unit
pF
6
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% test.ed
READ/WRITE MODES (cont’d)
The system designer may chose to provide a con-
stant high VPP and use the register commands for
all operations,or to switch the VPP from low to high
only when needing to erase or program the mem-
ory. All command register access is inhibited when
VCC falls below the Erase/Write Lockout Voltage
(VLKO) of 2.5V.
Awriteto thecommand registeris madebybringing
WLowwhile Eis Low. Thefalling edgeofW latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage VCC and the program voltage
VPP can be applied in any order. When the device
is powered up or when VPP is ≤ 6.5V the contents
of the command register defaults to 00h, thus
automatically setting-up Read operations. In addi-
tion a specific command may be used to set the
command register to 00h for reading the memory.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operationsare terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. The device remains in an inactivestate, ready
to start a Verify or ResetMode operation.
5/23
M28F101
Table 8. DC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%)
Symbol
ILI
Parameter
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, f = 6MHz
E = VIH
Min
Max
±1
Unit
µA
Input Leakage Current
ILO
Output Leakage Current
±10
30
µA
ICC
Supply Current (Read)
mA
mA
µA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Supply Current (Programming)
Supply Current (Program Verify)
Supply Current (Erase)
1
ICC1
E = VCC ± 0.2V
During Programming
During Verify
50
(1)
ICC2
10
mA
mA
mA
mA
µA
(1)
ICC3
15
(1)
ICC4
During Erasure
During Erase Verify
15
(1)
ICC5
Supply Current (Erase Verify)
Program Leakage Current
15
ILPP
IPP
V
PP ≤ VCC
VPP > VCC
PP ≤ VCC
±10
120
±10
30
µA
Program Current (Read or
Standby)
V
µA
(1)
IPP1
Program Current (Programming)
VPP = VPPH, During Programming
VPP = VPPH, During Verify
mA
(1)
Program Current (Program
Verify)
IPP2
5
mA
(1)
IPP3
Program Current (Erase)
Program Current (Erase Verify)
Input Low Voltage
VPP = VPPH, During Erase
30
5
mA
mA
V
(1)
IPP4
VPP = VPPH, During Erase Verify
VIL
VIH
–0.5
2
0.8
Input High Voltage TTL
Input High Voltage CMOS
VCC + 0.5
VCC + 0.5
0.45
V
0.7 VCC
V
IOL = 5.8mA (grade 1)
V
VOL
Output Low Voltage
IOL = 2.1mA (grade 6)
0.45
V
IOH = –100µA
4.1
0.85 VCC
2.4
V
Output High Voltage CMOS
Output High Voltage TTL
VOH
I
I
OH = –2.5mA
OH = –2.5mA
V
V
Program Voltage (Read
Operations)
VPPL
0
6.5
V
V
Program Voltage (Read/Write
Operations)
VPPH
VID
11.4
11.5
12.6
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
13
V
(1)
IID
A9 = VID
200
µA
Supply Voltage, Erase/Program
Lock-out
VLKO
2.5
V
Note: 1. Not 100% tested. Characterisation Data available.
6/23
M28F101
Table 9A. Read Only Mode AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; 0V ≤ VPP ≤ 6.5V)
M28F101
-90
-70
-100
Symbol
Alt
Parameter
Test Condition
Unit
VCC=5V±5% VCC=5V±10% VCC=5V±10%
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
Write Enable High to
Output Enable Low
tWHGL
tAVAV
6
6
6
µs
ns
ns
tRC
Read Cycle Time
E = VIL, G = VIL
E = VIL, G = VIL
70
90
100
Address Validto
Output Valid
tAVQV
tACC
70
70
90
90
100
100
Chip Enable Low to
Output Transition
(1)
tELQX
tLZ
tCE
tOLZ
tOE
G = VIL
G = VIL
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
Chip Enable Low to
Output Valid
tELQV
Output Enable Low to
Output Transition
(1)
tGLQX
E = VIL
Output Enable Low to
Output Valid
tGLQV
E = VIL
40
30
30
40
45
30
45
45
30
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
0
0
0
0
0
0
(1)
Output Enable High to
Output Hi-Z
tGHQZ
tDF
tOH
E = VIL
Address Transitionto
Output Transition
tAXQX
E = VIL, G = VIL
Note: 1. Sampled only, not 100% tested
Read Mode. The Read Mode is the default at
power up or may be set-up by writing 00h to the
command register. Subsequent read operations
outputdatafromthememory. The memoryremains
in the Read Mode until a new command is written
to the command register.
Electronic Signature Mode. In order to select the
correct erase and programming algorithms for on-
board programming, the manufacturerand device
codes may be read directly. It is not neccessaryto
apply a high voltage to A9 when using the com-
mand register. The Electronic Signature Mode is
set-upby writing 90hto the command register. The
following read cycles, with address inputs 00000h
or 00001h, output the manufactureror device type
codes. The command is terminated by writing an-
other valid command to the command register (for
example Reset).
7/23
M28F101
Table 9B. Read Only Mode AC Characteristics
((TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; 0V ≤ VPP ≤ 6.5V)
M28F101
-150
-120
-200
Symbol
Alt
Parameter
Test Condition
Unit
VCC=5V±10% VCC=5V±10% VCC=5V±10%
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
Write Enable High to
Output Enable Low
tWHGL
tAVAV
6
6
6
µs
ns
ns
tRC
Read Cycle Time
E = VIL, G = VIL
E = VIL, G = VIL
120
150
200
Address Valid to
Output Valid
tAVQV
tACC
120
120
150
150
200
200
Chip Enable Low to
Output Transition
(1)
tELQX
tLZ
tCE
tOLZ
tOE
G = VIL
G = VIL
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
Chip Enable Low to
Output Valid
tELQV
Output Enable Low to
Output Transition
(1)
tGLQX
E = VIL
Output Enable Low to
Output Valid
tGLQV
E = VIL
50
55
30
55
55
35
60
60
40
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
0
0
0
0
0
0
(1)
Output Enable High to
Output Hi-Z
tGHQZ
tDF
tOH
E = VIL
Address Transition to
Output Transition
tAXQX
E = VIL, G = VIL
Note: 1. Sampled only, not 100% tested
Erase and Erase Verify Modes. The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the com-
mand register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an ad-
dressed byte.
Erase Verify Mode is set-up by writing A0h to the
command register and at the same time supplying
the address of the byte to be verified. The rising
edgeof W during the set-up of the first EraseVerify
Mode stops the Erase operation. The following
read cycle is made with an internally generated
margin voltage applied; reading FFh indicates that
all bits of the addressed byte are fully erased. The
whole contents of the memory are verified by re-
peating the Erase Verify Operation, first writing the
set-up code A0h with the address of the byte to be
verified and then reading the byte contents in a
second read cycle.
8/23
M28F101
Figure 5. Read Mode AC Waveforms
tAVAV
A0-A16
E
tAVQV
tELQV
tAXQX
tEHQZ
tELQX
G
tGLQV
tGLQX
tGHQZ
DQ0-DQ7
DATA OUT
AI00671
Figure 6. Read Command Waveforms
V
PP
tVPHEL
VALID
A0-A16
tAVQV
tAXQX
tEHQZ
tGHQZ
E
tELWL
tWHEH
tELQV
G
tGHWL
tWHGL
W
tWLWH
tGLQV
tDVWH
tWHDX
DQ0-DQ7
COMMAND
DATA OUT
READ SET-UP
READ
AI00672
9/23
M28F101
Figure 7. Electronic Signature Command Waveforms
V
PP
tVPHEL
00000h-00001h
A0-A16
tAVQV
tELQV
tAXQX
tEHQZ
tGHQZ
E
tELWL
tWHEH
G
tGHWL
tWHGL
W
tWLWH
tDVWH
tGLQV
tWHDX
DQ0-DQ7
COMMAND
DATA OUT
READ ELECTRONIC
SIGNATURE SET-UP
READ
MANUFACTURER
OR DEVICE
AI00673
READ/WRITE MODES (cont’d)
ProgramVerify Modeis set-up bywriting C0h to the
command register. The rising edge of W duringthe
set-up of the Program Verify Mode stops the Pro-
gramming operation. The following read cycle, of
the address already latched during programming,
is made with an internally generated margin volt-
ageapplied,reading validdataindicatesthatallbits
have been programmed.
ResetMode. This commandis usedto safelyabort
Erase or Program Modes. The Reset Mode is
set-up and performed by writing FFh two times to
the command register. The command should be
followed by writing a valid command to the the
command register (for example Read).
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not FFh, another
Erase operationis performedand verification con-
tinuesfromthe addressofthelastverifiedbyte.The
command is terminated by writing another valid
command to the command register (for example
Program or Reset).
Program and Program Verify Modes. The Pro-
gramModeis set-up bywriting 40htothecommand
register. This is followed by a second write cycle
which latches the address and data of the byte to
be programmed. The rising edge of W during this
secind cycle starts the programming operation.
Programmingis followed by aProgram Verify ofthe
data written.
10/23
M28F101
Table 10A. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F101
-90
VCC=5V±10% VCC=5V±10%
-70
-100
Symbol
Alt
Parameter
Unit
VCC=5V±5%
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min
1
Max
Min
Max
Min
Max
tVPHEL
tVPHWL
tWHWH3
tAVWL
tAVEL
VPP High to Chip Enable Low
1
1
1
1
µs
µs
ns
ns
ns
ns
ns
ns
ns
VPP High to Write Enable Low
1
tWC
tAS
Write Cycle Time
70
0
90
0
100
0
Address Validto Write Enable Low
Address Validto Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
0
0
0
tWLAX
tELAX
tAH
40
50
10
0
40
60
15
0
40
60
15
0
tELWL
tCS
tWLEL
Output Enable High to Write Enable
Low
tGHWL
0
0
0
µs
tGHEL
tDVWH
tDVEH
Output Enable High to Chip Enable Low
Input Validto Write Enable High
Input Validto Chip Enable High
0
0
0
µs
ns
ns
tDS
30
30
40
35
40
40
Write Enable Low to Write Enable High
(Write Pulse)
tWLWH
tELEH
tWP
35
35
40
45
40
45
ns
ns
Chip Enable Low to Chip Enable High
(Write Pulse)
tWHDX
tEHDX
tDH
Write Enable High to InputTransition
Chip Enable High to Input Transition
Duration of Program Operation
10
10
9.5
9.5
9.5
0
10
10
9.5
9.5
9.5
0
10
10
9.5
9.5
9.5
0
ns
ns
µs
µs
ms
ns
ns
ns
ns
tWHWH1
tEHEH1
tWHWH2
tWHEH
tEHWH
tWHWL
tEHEL
Duration of Program Operation
Duration of Erase Operation
tCH
Write Enable High to Chip Enable High
Chip Enable High to Write Enable High
0
0
0
tWPH Write Enable High to Write Enable Low
Chip Enable High to Chip Enable Low
20
20
20
20
20
20
Write Enable High to Output Enable
Low
tWHGL
6
6
6
6
6
6
µs
tEHGL
tAVQV
Chip Enable High to Output Enable Low
tACC Addess Validto data Output
µs
ns
ns
ns
ns
ns
ns
ns
ns
70
70
90
90
100
100
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
0
0
0
0
0
0
tELQV
tCE
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
tGLQV
tOE
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transitionto Output Transition
40
30
30
40
40
30
45
40
30
(1)
tEHQZ
(1)
tGHQZ
tDF
tOH
tAXQX
0
0
0
Note: 1. Sampled only, not 100% tested.
11/23
M28F101
Table 10B. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F101
-150
VCC=5V±10% VCC=5V±10% VCC=5V±10%
-120
-200
Symbol
Alt
Parameter
Unit
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
tVPHEL
tVPHWL
tWHWH3
tAVWL
tAVEL
VPP High to Chip Enable Low
1
1
1
1
1
1
µs
µs
ns
ns
ns
ns
ns
ns
ns
VPP High to Write Enable Low
tWC
tAS
Write Cycle Time
120
0
150
0
200
0
Address Validto Write Enable Low
Address Validto Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
0
0
0
tWLAX
tELAX
tAH
60
80
20
0
60
80
20
0
75
80
20
0
tELWL
tCS
tWLEL
Output Enable High to Write Enable
Low
tGHWL
0
0
0
µs
tGHEL
tDVWH
tDVEH
Output Enable High to Chip Enable Low
Input Valid to Write Enable High
Input Valid to Chip Enable High
0
0
0
µs
ns
ns
tDS
50
50
50
50
50
50
Write Enable Low to Write Enable High
(Write Pulse)
tWLWH
tELEH
tWP
60
70
60
70
60
70
ns
ns
Chip Enable Low to Chip Enable High
(Write Pulse)
tWHDX
tEHDX
tDH
Write Enable High to Input Transition
Chip Enable High to Input Transition
Duration of Program Operation
10
10
9.5
9.5
9.5
0
10
10
9.5
9.5
9.5
0
10
10
9.5
9.5
9.5
0
ns
ns
µs
µs
ms
ns
ns
ns
ns
tWHWH1
tEHEH1
tWHWH2
tWHEH
tEHWH
tWHWL
tEHEL
Duration of Program Operation
Duration of Erase Operation
tCH
Write Enable High to Chip Enable High
Chip Enable High to Write Enable High
0
0
0
tWPH Write Enable High to Write Enable Low
Chip Enable High to Chip Enable Low
20
20
20
20
20
20
Write Enable High to Output Enable
Low
tWHGL
6
6
6
6
6
6
µs
tEHGL
tAVQV
Chip Enable High to Output Enable Low
tACC Addess Valid to data Output
µs
ns
ns
ns
ns
ns
ns
ns
ns
120
120
150
150
200
200
(1)
tELQX
tLZ
tCE
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
0
0
0
0
0
0
tELQV
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
tGLQV
tOE
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
50
50
30
55
55
35
60
60
40
(1)
tEHQZ
(1)
tGHQZ
tDF
tOH
tAXQX
0
0
0
Note: 1. Sampled only, not 100% tested.
12/23
M28F101
Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled
13/23
M28F101
Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled
14/23
M28F101
Figure 10. Program Set-up and Program Verify Commands Waveforms, W Controlled
15/23
M28F101
Figure 11. Program Set-up and Program Verify Commands Waveforms, E Controlled
16/23
M28F101
Figure 12. Erasing Flowchart
Figure 13. Programming Flowchart
V
= 12V
PP
V
= 12V
PP
PROGRAM ALL
BYTES TO 00h
n = 0
n=0, Addr=00000h
PROGRAM SET-UP
Latch Addr, Data
ERASE SET-UP
Wait 10ms
Wait 10µs
NO
PROGRAM VERIFY
ERASE VERIFY
Latch Addr.
NO
++n
LIMIT
YES
++n
= 25
Wait 6µs
YES
Wait 6µs
READ DATA OUTPUT
V
<
FAIL
6.5V
PP
READ DATA OUTPUT
V
<
6.5V
PP
FAIL
NO
Data
OK
Addr++
NO
Data
OK
Addr++
YES
YES
Last
NO
Addr
Last
NO
Addr
YES
READ COMMAND
YES
READ COMMAND
V
< 6.5V, PASS
PP
AI00677
V
< 6.5V, PASS
PP
AI00678
Limit: 1000 at grade 1; 6000 at grades 3 & 6.
PRESTO F ERASE ALGORITHM
PRESTO F PROGRAM ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithm first programmsall bytes to 00h in order
to ensure uniform erasure. The programming fol-
lows the PRESTO F Programming Algorithm.
Erase is set-up by writing 20h to the command
register, the erasure is started by repeating this
write cycle. Erase Verifyis set-up by writing A0h to
the command registertogether with the address of
the byte to be verified. The subsequent read cycle
reads the data which is compared to FFh. Erase
Verify begins at address 0000h and continues to
the last address oruntil the comparison of the data
to 0FFh fails. If this occurs, the address of the last
byte checked is stored and a new Erase operation
performed. Erase Verify then continues from the
address of the stored location.
The PRESTO F Programming Algorithm applies a
series of 10µs programming pulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-up by writing 40h to the command register, the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the command register, followed by a read
cycle and a compare of the data read to the data
expected. During Program and Program Verify op-
erations a MARGIN MODE circuit is activated to
guaranteethat the cell is programmedwith asafety
margin.
17/23
M28F101
ORDERING INFORMATION SCHEME
Example:
M28F101
-70
X
N
1
TR
Operating Voltage
Option
F
5V
R
Reverse Pinout
TR Tape & Reel
Packing
Speed
Power Supplies
Package
PDIP32
PLCC32
Temp. Range
-70
-90
70ns
90ns
blank
X
V
V
CC ± 10%
CC ± 5%
P
K
N
1
3
6
0 to 70 °C
–40 to 125 °C
–40 to 85 °C
-100
-120
-150
-200
100ns
120ns
150ns
200ns
TSOP32
8 x 20mm
Devices are shipped from the factory with the memory content erased (to FFh).
For alist of availableoptions(Speed, Package, etc...) or for furtherinformationon any aspect of this device,
please contact the SGS-THOMSON Sales Office nearest to you.
18/23
M28F101
PDIP32 - 32 pin Plastic DIP, 600 mils width
mm
Min
inches
Symb
Typ
Max
4.83
–
Typ
Min
Max
0.190
–
A
A1
A2
B
0.38
–
0.015
–
–
–
–
–
0.41
1.14
0.20
41.78
15.24
13.46
–
0.51
1.40
0.30
42.04
15.88
13.97
–
0.016
0.045
0.008
1.645
0.600
0.530
–
0.020
0.055
0.012
1.655
0.625
0.550
–
B1
C
D
E
E1
e1
eA
L
2.54
0.100
0.600
15.24
–
–
–
–
3.18
1.78
0°
3.43
2.03
15°
0.125
0.070
0°
0.135
0.080
15°
S
α
N
32
32
PDIP32
A2
A
A1
e1
L
B1
B
D
α
C
eA
S
N
1
E1
E
PDIP
Drawing is not to scale.
19/23
M28F101
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
inches
Min
Symb
Typ
Max
3.56
2.41
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
B
0.100
0.060
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.050
N
32
32
Nd
Ne
7
7
9
9
CP
0.10
0.004
PLCC32
D
D1
A1
1 N
B1
e
Ne
E1 E
D2/E2
B
Nd
A
CP
PLCC
Drawing is not to scale.
20/23
M28F101
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
1.04
0.05
0.95
0.15
0.10
19.90
18.24
7.90
–
inches
Min
Symb
Typ
Max
1.24
0.20
1.06
0.27
0.21
20.12
18.49
8.10
–
Typ
Max
0.049
0.008
0.042
0.011
0.008
0.792
0.728
0.319
–
A
A1
A2
B
0.041
0.002
0.037
0.006
0.004
0.783
0.718
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.30
0°
0.70
5°
0.012
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
TSOP32
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
21/23
M28F101
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
1.04
0.05
0.95
0.15
0.10
19.90
18.24
7.90
–
inches
Min
Symb
Typ
Max
1.24
0.20
1.06
0.27
0.21
20.12
18.49
8.10
–
Typ
Max
0.049
0.008
0.042
0.011
0.008
0.792
0.728
0.319
–
A
A1
A2
B
0.041
0.002
0.037
0.006
0.004
0.783
0.718
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.30
0°
0.70
5°
0.012
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
TSOP32
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-b
A1
α
L
Drawing is not to scale.
22/23
M28F101
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea- Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.
23/23
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