M28F102-150XN1TR [STMICROELECTRONICS]
64KX16 FLASH 12V PROM, 150ns, PDSO40, 10 X 14 MM, PLASTIC, TSOP-40;
| 型号： | M28F102-150XN1TR |
| 厂家： | 
ST |
| 描述： | 64KX16 FLASH 12V PROM, 150ns, PDSO40, 10 X 14 MM, PLASTIC, TSOP-40 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28F102
1 Megabit (64K x 16, Chip Erase) FLASH MEMORY
FAST ACCESS TIME: 90ns
LOW POWER CONSUMPTION
– Standby Current: 100µA Max
10,000 ERASE/PROGRAM CYCLES
12V PROGRAMMING VOLTAGE
TYPICAL BYTE PROGRAMMING TIME 10µs
(PRESTO F ALGORITHM)
ELECTRICALCHIP ERASE in 1s RANGE
PLCC44 (K)
TSOP40 (N)
10 x 14mm
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and
PINOUTS for PLCC44 and TSOP40
Figure 1. Logic Diagram
EXTENDED TEMPERATURE RANGES
DESCRIPTION
The M28F102 FLASH MEMORY is a non-volatile
memory which may be erased electrically at the
chip level and programmed word-by-word. It is
organised as 64K words of 16 bits. It uses a com-
mand register architecture to select the operating
modes and thus provides a simple microprocessor
interface. The M28F102 FLASH MEMORY is suit-
able for applications where the memory has to be
reprogrammed in the equipment. The access time
of 100ns makes the device suitable for use in high
speed microprocessor systems.
V
V
PP
CC
16
16
A0-A15
DQ0-DQ15
W
E
M28F102
Table 1. Signal Names
G
A0 - A15
Address Inputs
Data Inputs / Outputs
Chip Enable
DQ0 - DQ15
E
V
SS
AI00627B
G
Output Enable
Write Enable
W
VPP
VCC
VSS
Program Supply
Supply Voltage
Ground
September 1995
1/20
M28F102
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
A9
A10
A11
A12
A13
A14
A15
NC
1
40
V
SS
A8
A7
A6
A5
1 44
DQ12
A13
A12
A11
A10
A9
A4
DQ11
DQ10
DQ9
A3
A2
W
A1
DQ8
V
10
11
M28F102
(Normal)
31
30
A0
CC
V
12
M28F102
34
V
SS
SS
V
G
PP
E
NC
DQ7
DQ6
DQ5
DQ4
NC
A8
A7
A6
A5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
23
AI00629D
DQ8
20
21
V
SS
AI01263
Warning: NC = Not Connected
Warning: NC = Not Connected
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
grade 1
grade 3
grade 6
0 to 70
–40 to 125
–40 to 85
°C
TSTG
VIO
Storage Temperature
Input or Output Voltages
Supply Voltage
–65 to 150
–0.6 to 7
°C
V
VCC
VA9
–0.6 to 7
V
A9 Voltage
–0.6 to 13.5
V
Program Supply Voltage, during Erase
or Programming
VPP
–0.6 to 14
V
Note: Except forthe rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION
input. When VPP is less than or equal to 6.5V,the
command register is disabled and M28F102 func-
tions as a read only memory providing operating
modes similar to an EPROM (Read, Output Dis-
able, Electronic Signature Read and Standby).
When VPP is raised to 12V the command register
is enabled and this provides,in addition,Erase and
Program operations.
The M28F102 FLASH MEMORY employs a tech-
nology similar to a 1 Megabit EPROM but adds to
the device functionalityby providing electrical era-
sure and programming. These functions are man-
agedbya commandregister.The functionsthat are
addressed via the command register depend on
the voltage applied to the VPP, program voltage,
2/20
M28F102
READ ONLY MODES, VPP ≤ 6.5V
READ/WRITE MODES, 11.4V ≤ VPP ≤ 12.6V
When VPP is High both read and write operations
may be performed. These are defined by the con-
tents of an internal command register. Commands
may be written to this register to set-up and exe-
cute, Erase, EraseVerify,Program, ProgramVerify
and Reset modes. Each of these modes needs 2
cycles. Every mode starts with a write operation to
set-up the command,this is followed by eitherread
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
data at any location in memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
Electronic SignatureRead mode is set-up with one
cycle and followed by a read cycle to output the
manufactureror device codes.
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
StandbyMode this input is ’don’t care’.
Read Mode. The M28F102 has two enableinputs,
E and G, both of which must be Low in order to
output data from the memory. The Chip Enable (E)
is the power control and should be used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independantof the device selection.
Standby Mode. In the Standby Mode the maxi-
mum supply current is reduced. The device is
placed in the StandbyMode by applying a High to
the Chip Enable (E) input. When in the Standby
Mode the outputs are in a high impedance state,
independantof the Output Enable (G) input.
Awrite tothe command registeris madebybringing
W Lowwhile E is Low.Thefalling edgeofWlatches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
Output Disable Mode. When the Output Enable
(G) is High the outputs are in a high impedance
state.
Electronic Signature Mode. Thismode allows the
read out of two binary codes from thedevice which
identify the manufacturer and device type. This
mode is intended for use by programming equip-
ment to automaticallyselect the correct erase and
programming algorithms. The Electronic Signature
Mode is active when a high voltage (11.5V to 13V)
is appliedtoaddresslineA9 with EandG Low. With
A0 Low the output data is the manufacturer code,
when A0is High the output is the devicetype code.
All other address lines should be maintained Low
while reading the codes. The electronic signature
may also be accessed in Read/Write modes.
The supply voltage VCC and the program voltage
V
PP can be applied in any order. When the device
is powered up or when VPP is ≤ 6.5V the contents
of the command register default to 00h, thus auto-
matically setting-up Read operations. In addition a
specific command may be used to set the com-
mand register to 00h for reading the memory.
The system designer may chose to provide a con-
stant high VPP and use the register commands for
all operations,or to switch the VPP from low to high
only when needing to erase or program the mem-
ory. All command register access is inhibited when
(1)
Table 3. Operations
VPP
Operation
Read
E
G
VIL
VIH
X
W
VIH
A9
A9
X
DQ0 - DQ15
Data Output
Hi-Z
Read Only
VPPL
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
Output Disable
Standby
VIH
X
X
Hi-Z
Electronic Signature
Read
VIL
VIL
VIH
VIH
X
VIH
VID
A9
A9
X
Codes
Read/Write (2)
VPPH
VIH
Data Output
Data Input
Hi-Z
Write
VIL Pulse
VIH
Output Disable
Standby
X
X
Hi-Z
Notes: 1. X = VIL or VIH
2. Refer also to the Command Table
3/20
M28F102
Table 4. Electronic Signature
Identifier
A0
VIL
VIH
DQ15-DQ8 DQ7
DQ6
DQ5
DQ4 DQ3
DQ2
DQ1
DQ0
Hex Data
0020h
Manufacturer’s
Code
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
Device Code
0050h
Table 5. Commands (1)
1st Cycle
A0-A15
X
2nd Cycle
A0-A15
Command
Cycles
Operation
DQ0-DQ15 (2)
Operation
DQ0-DQ15 (2)
Read
1
2
Write
xx00h
Read
Read
0000h
0001h
0020h
0050h
Electronic
Signature
Write
Write
X
X
xx90h
xx20h
Setup Erase/
Erase
2
Write
Read
X
X
xx20h
Erase Verify
Setup Program/
Program
2
2
Write
Write
A0-A15
X
xxA0h
xx40h
Data Output
Write
Read
Write
A0-A15
Data Input
Data Output
0FFFFh
Program Verify
Reset
2
2
Write
Write
X
X
xxC0h
X
X
0FFFFh
Notes: 1. X = VIL or VIH
2. x = Don’t Care.
READ/WRITE MODES (cont’d)
Electronic Signature Mode. Inorder to select the
correct erase and programming algorithms for on-
boardprogramming, themanufacturerand devices
code may be read directly. It is not neccessaryto
apply a high voltage to A9 when using the com-
mand register. The Electronic Signature Mode is
set-up by writing ’xx90h’ to the command register.
The following read cycle, with address inputs
0000hor 0001h, outputthe manufacturer or device
type codes. The command is terminated by writing
another valid command to the command register
(for example Reset).
VCC falls below the Erase/Write Lockout Voltage
(VLKO) of 2.5V.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. Thedevice remains in an inactive state, ready
to start a Verify or ResetMode operation.
Erase and Erase Verify Modes. The memory is
erased by first Programming all words to 0000h,
the Erase command then erases them to 0FFFFh.
TheErase Verify command is then usedto read the
memory word-by-word for a content of 0FFFFh.
Read Mode. The Read Mode is the default at
power up or may be set-up by writing ’xx00h’ to the
command register. Subsequent read operations
outputdata from thememory. Thememory remains
in the Read Mode until a new command is written
to the command register.
The Erase Mode is set-up by writing ’xx20h’ to the
command register.Thewrite cycle is thenrepeated
to start the erase operation. Erasure starts on the
rising edge of Wduring this second cycle.
4/20
M28F102
Erase is followed by an Erase Verify which reads
an addressed byte.
Program and Program Verify Modes. The Pro-
gram Mode is set-up by writing ’xx40h’ to the com-
mand register. This is followed by a second write
cycle which latches the address and data of the
word to be programmed. The rising edge of W
during this secind cycle starts the programming
operation. Programming is followed by a Program
Verify of the data written.
Erase Verify Mode is set-up by writing ’xxA0h’ to
the command register and at the same time sup-
plying the address of the word to be verified. The
rising edge of W during the set-up of the first Erase
Verify Mode stops the Erase operation. The follow-
ing read cycle ismade with an internally generated
margin voltage applied; reading 0FFFFh indicates
that all bits of the addressed byte are fully erased.
The whole contents of the memoryare verified by
repeating the Erase Verify Operation, first writing
the set-up code ’xxA0h’ with the address of the
word to be verified and then reading the byte
contents in a second read cycle.
ProgramVerify Mode is set-upby writing ’xxC0h’ to
the command register. The rising edge of W during
the set-up of the Program Verify Mode stops the
Programming operation. The following read cycle,
of the address already latched during program-
ming, is made with an internally generated margin
voltageapplied,reading validdata indicatesthatall
bits have been programmed.
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not 0FFFFh, an-
other Erase operationis performedand verification
continuesfromtheaddressofthe lastverifiedword.
The command is terminated by writing another
validcommandto the command register(for exam-
ple Program or Reset).
ResetMode. This command is usedto safelyabort
Erase or Program Modes. The Reset Mode is
set-upand performed by writing 0FFFFh two times
to the command register. Thecommand should be
followed by writing a valid command to the the
command register (for example Read).
AC MEASUREMENT CONDITIONS
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 10ns
1.3V
Input Pulse Voltages
0.45V to 2.4V
0.8V to 2V
Input and Output Timing Ref. Voltages
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
DEVICE
UNDER
TEST
OUT
C
= 100pF
2.4V
L
2.0V
0.8V
0.45V
C
includes JIG capacitance
L
AI00828
AI00827
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested
5/20
M28F102
Table 7. DC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%)
Symbol
ILI
Parameter
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, f = 8MHz
E = VIH
Min
Max
±1
Unit
µA
Input Leakage Current
ILO
Output Leakage Current
±10
50
µA
ICC
Supply Current (Read)
mA
mA
µA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Supply Current (Programming)
Supply Current (Program Verify)
Supply Current (Erase)
1
ICC1
E = VCC ± 0.2V
During Programming
During Verify
100
10
(1)
ICC2
mA
mA
mA
mA
(1)
ICC3
30
(1)
ICC4
During Erasure
During Erase Verify
15
(1)
ICC5
Supply Current (Erase Verify)
30
Supply Current
(Electronic Signature)
(1)
ICC6
A9 = VID
30
mA
ILPP
IPP
Program Leakage Current
V
PP ≤ VCC
VPP > VCC
PP ≤ VCC
VPP = VPPH, During Programming
±10
200
±10
50
µA
µA
µA
mA
Program Current (Read or
Standby)
V
(1)
IPP1
Program Current (Programming)
Program Current (Program
Verify)
(1)
IPP2
V
PP = VPPH, During Verify
5
mA
(1)
IPP3
Program Current (Erase)
VPP = VPPH, During Erase
50
5
mA
mA
(1)
IPP4
Program Current (Erase Verify)
VPP = VPPH, During Erase Verify
Program Current
(Electronic Signature)
(1)
IPP5
A9 = VID
500
µA
VIL
VIH
Input Low Voltage
–0.5
2
0.8
VCC + 0.5
VCC + 0.5
0.45
V
V
V
V
V
V
V
V
Input High VoltageTTL
Input High Voltage CMOS
0.7 VCC
I
OL = 5.8mA (grade 1)
IOL = 2.1mA (grade 3&6)
OH = –100µA
VOL
Output Low Voltage
0.45
I
VCC –0.4
0.85 VCC
2.4
Output High Voltage CMOS
Output High Voltage TTL
VOH
IOH = –2.5mA
IOH = –2.5mA
Program Voltage(Read
Operations)
VPPL
0
6.5
V
V
Program Voltage(Read/Write
Operations)
VPPH
VID
11.4
11.5
12.6
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
13
V
(1)
IID
A9 = VID
200
µA
Supply Voltage, Erase/Program
Lock-out
VLKO
2.5
V
Note: 1. Not 100% tested. Characterisation Data available.
6/20
M28F102
Table 8A. Read Only Mode AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; 0V ≤ VPP ≤ 6.5V)
M28F102
Symbol
Alt
Parameter
Test Condition
Unit
-90
-100
-120
Min Max Min Max Min Max
Write Enable High to
Output Enable Low
tWHGL
tAVAV
-
6
6
6
µs
ns
ns
tRC
tACC
tLZ
tCE
tOLZ
tOE
Read Cycle Time
E = VIL, G = VIL
E = VIL, G = VIL
90
100
120
Address Valid to
Output Valid
tAVQV
90
90
100
100
120
120
Chip Enable Low to
Output Transition
(1)
tELQX
G = VIL
G = VIL
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
Chip Enable Low to
Output Valid
tELQV
(1)
Output Enable Low to
Output Transition
tGLQX
E = VIL
Output Enable Low to
Output Valid
tGLQV
E = VIL
50
40
30
50
40
30
60
40
30
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
0
0
0
0
0
0
Output Enable High to
Output Hi-Z
(1)
tGHQZ
tDF
tOH
E = VIL
Address Transition to
Output Transition
tAXQX
E = VIL, G = VIL
Note: 1. Sampled only, not 100% tested
Table 8B. Read Only Mode AC Characteristics
((TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; 0V ≤ VPP ≤ 6.5V)
M28F102
Symbol
Alt
Parameter
Test Condition
Unit
-150
-200
Min
Max
Min
Max
Write Enable High to Output
Enable Low
tWHGL
-
6
6
µs
tAVAV
tRC
Read Cycle Time
E = VIL, G = VIL
E = VIL, G = VIL
150
200
ns
ns
tAVQV
tACC
Address Valid to Output Valid
150
150
200
200
Chip Enable Low to Output
Transition
(1)
tELQX
tLZ
tCE
tOLZ
tOE
G = VIL
G = VIL
E = VIL
0
0
0
0
ns
ns
ns
tELQV
Chip Enable Low to Output Valid
Output Enable Low to Output
Transition
(1)
tGLQX
tGLQV
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
E = VIL
G = VIL
E = VIL
70
55
35
70
60
45
ns
ns
ns
(1)
tEHQZ
0
0
0
0
(1)
tGHQZ
tDF
tOH
Address Transition to Output
Transition
tAXQX
E = VIL, G = VIL
0
0
ns
Note: 1. Sampled only, not 100% tested
7/20
M28F102
Figure 5. Read Mode AC Waveforms
tAVAV
A0-A15
E
tAVQV
tELQV
tAXQX
tEHQZ
tELQX
G
tGLQV
tGLQX
tGHQZ
DQ0-DQ15
DATA OUT
AI00630
Figure 6. Read Command Waveforms
V
PP
tVPHEL
VALID
A0-A15
tAVQV
tAXQX
E
tELWL
tWHEH
tELQV
tEHQZ
tGHQZ
G
tGHWL
tWHGL
W
tWLWH
tGLQV
tDVWH
tWHDX
DQ0-DQ15
COMMAND
DATA OUT
READ SET-UP
READ
AI00631
8/20
M28F102
Figure 7. Electronic Signature Command Waveforms
V
PP
tVPHEL
0000h-0001h
A0-A15
tAVQV
tELQV
tAXQX
tEHQZ
tGHQZ
E
tELWL
tWHEH
G
tGHWL
tWHGL
W
tWLWH
tDVWH
tGLQV
tWHDX
DQ0-DQ15
COMMAND
DATA OUT
READ ELECTRONIC
SIGNATURE SET-UP
READ
MANUFACTURER
OR DEVICE
AI00632
9/20
M28F102
Table 9A. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10% or 5V ± 5%)
M28F102
-100
Symbol
Alt
Parameter
Unit
-90
-120
Min Max Min Max Min Max
tVPHEL
tVPHWL
tWHWH3
tEHEH3
tAVWL
tAVEL
VPP High to Chip Enable Low
1
1
1
1
1
1
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
VPP High to Write Enable Low
tWC
tWC
tAS
Write Cycle Time (W controlled)
Write Cycle Time (E controlled)
90
90
0
100
100
0
120
120
0
Address Validto Write Enable Low
Address Validto Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Input Valid to Write Enable High
Input Valid to Chip Enable High
0
0
0
tWLAX
tELAX
tAH
40
60
15
0
60
80
20
0
60
80
20
0
tELWL
tCS
tWLEL
tGHWL
tGHEL
tDVWH
tDVEH
0
0
0
0
0
0
tDS
40
35
50
50
50
50
Write Enable Low to Write Enable High
(Write Pulse)
tWLWH
tELEH
tWP
40
45
60
70
60
70
ns
ns
Chip Enable Low to Chip Enable High
(Write Pulse)
tWHDX
tEHDX
tDH
Write Enable High to Input Transition
Chip Enable High to Input Transition
10
10
10
10
10
10
ns
ns
Duration of Program Operation
(W contr.)
tWHWH1
9.5
9.5
9.5
µs
tEHEH1
tWHWH2
tEHEH2
tWHEH
tEHWH
tWHWL
tEHEL
Duration of Program Operation (E contr.)
Duration of Erase Operation (W contr.)
Duration of Erase Operation (E contr.)
Write Enable High to Chip Enable High
Chip Enable High to Write Enable High
Write Enable High to Write Enable Low
Chip Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
Addess Valid to data Output
9.5
9.5
9.5
0
9.5
9.5
9.5
0
9.5
9.5
9.5
0
µs
ms
ms
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
tCH
0
0
0
tWPH
20
20
6
20
20
6
20
20
6
tWHGL
tEHGL
6
6
6
tAVQV
tACC
tLZ
90
90
100
100
120
120
(1)
tELQX
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
0
0
0
0
0
0
tELQV
tCE
(1)
tGLQX
tOLZ
tOE
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tGLQV
50
40
30
50
40
30
60
40
30
(1)
tEHQZ
(1)
tGHQZ
tDF
tOH
Output Enable High to Output Hi-Z
Address Transition to Output Transition
tAXQX
0
0
0
Note: 1. Sampled only, not 100% tested
10/20
M28F102
Table 9B. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10% or 5V ± 5%)
M28F102
Symbol
Alt
Parameter
Unit
-150
-200
Min Max Min Max
tVPHEL
tVPHWL
tWHWH3
tEHEH3
tAVWL
tAVEL
VPP High to Chip Enable Low
1
1
1
1
µs
µs
ns
120
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
VPP High to Write Enable Low
tWC
tWC
tAS
Write Cycle Time (W controlled)
150
150
0
200
200
0
Write Cycle Time (E controlled)
Address Validto Write Enable Low
Address Validto Chip Enable Low
0
0
tWLAX
tELAX
tAH
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Input Valid to Write Enable High
60
80
20
0
75
80
20
0
tELWL
tCS
tWLEL
tGHWL
tGHEL
tDVWH
tDVEH
0
0
0
0
tDS
tWP
tDH
50
50
60
70
10
10
9.5
9.5
9.5
9.5
0
50
50
60
80
10
10
9.5
9.5
9.5
9.5
0
Input Valid to Chip Enable High
tWLWH
tELEH
Write Enable Low to Write Enable High (Write Pulse)
Chip Enable Low to Chip Enable High (Write Pulse)
Write Enable High to Input Transition
Chip Enable High to Input Transition
Duration of Program Operation (W controlled)
Duration of Program Operation (E controlled)
Duration of Erase Operation (W controlled)
Duration of Erase Operation (E controlled)
Write Enable High to Chip Enable High
Chip Enable High to Write Enable High
Write Enable High to Write Enable Low
Chip Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
Addess Valid to data Output
tWHDX
tEHDX
tWHWH1
tEHEH1
tWHWH2
tEHEH2
tWHEH
tEHWH
tWHWL
tEHEL
tCH
0
0
tWPH
20
20
6
20
20
6
tWHGL
tEHGL
tAVQV
6
6
tACC
tLZ
150
150
200
200
(1)
tELQX
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
0
0
0
0
tELQV
tCE
(1)
tGLQX
tOLZ
tOE
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tGLQV
70
55
35
70
60
45
(1)
tEHQZ
(1)
tGHQZ
tDF
tOH
Output Enable High to Output Hi-Z
Address Transition to Output Transition
tAXQX
0
0
Note: 1. Sampled only, not 100% tested
11/20
M28F102
Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled
12/20
M28F102
Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled
13/20
M28F102
Figure 10. Program Set-up and Program Verify Commands Waveforms, W Controlled
14/20
M28F102
Figure 11. Program Set-up and Program Verify Commands Waveforms, E Controlled
15/20
M28F102
Figure 12. Erasing Flowchart
Figure 13. ProgrammingFlowchart
V
= 12V
PP
V
= 12V
PP
PROGRAM ALL
BYTES TO 0000h
n = 0
n=0, Addr=0000h
PROGRAM SET-UP
Latch Addr, Data
ERASE SET-UP
Wait 10ms
Wait 10µs
NO
++n
PROGRAM VERIFY
ERASE VERIFY
Latch Addr.
NO
++n
LIMIT
YES
Wait 6µs
= 25
YES
Wait 6µs
READ DATA OUTPUT
V
< 6.5V
PP
READ DATA OUTPUT
FAIL
V
< 6.5V
PP
FAIL
NO
Data
OK
Addr++
NO
Data
OK
Addr++
YES
YES
Last
NO
Addr
Last
NO
Addr
YES
READ COMMAND
YES
READ COMMAND
V
< 6.5V, PASS
PP
AI00677
V
< 6.5V, PASS
PP
AI00636
Limit: 1000 at grade 1; 6000 at grades 3 & 6.
PRESTO F ERASE ALGORITHM
PRESTO F PROGRAM ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithm first programs allwords to 0000hin order
to ensure uniform erasure. The programming fol-
lows the Presto F Programming Algorithm (see
below). Erase is set-up by writing ’xx20h’ to the
commandregister,theerasureis started byrepeat-
ing thiswrite cycle. Erase Verify is set-upby writing
’xxA0h’ to the command register together with the
addressof the wordto be verified. The subsequent
read cycle reads the data which is compared to
0FFFFh. Erase Verify beginsat address0000hand
continues to the last address or until the compari-
son of the data to 0FFFFh fails. If this occurs, the
address of the last word checked is stored and a
new Erase operationperformed. Erase Verify then
continues from the address of the storedlocation.
The PRESTO F Programming Algorithm applies a
series of 10µs programmingpulses to aword until
a correct verify occurs. Up to 25 programming
operations are allowed for one word. Program is
set-up by writing ’xx40h’ to the command register,
the programming is started after the next write
cycle which also latches the address and data to
be programmed.ProgramVerifyis set-upbywriting
’xxC0h’tothe commandregister, followedbyaread
cycle and a compare of the data read to the data
expected. During Program and Program Verify op-
erations a MARGIN MODE circuit is activated to
guaranteethat the cell isprogrammedwith a safety
margin.
16/20
M28F102
ORDERING INFORMATION SCHEME
Example:
M28F102 -100 X
K
1 TR
Speed
90 ns
V
CC Tolerance
Package
Temp. Range
0 to 70 °C
Option
-90
blank
X
± 10%
± 5%
K
N
PLCC44
1
3
6
TR Tape & Reel
Packing
-100
-120
-150
-200
100 ns
120 ns
150 ns
200 ns
TSOP40
10 x 14mm
–40 to 125 °C
–40 to 85 °C
For alist ofavailableoptions(Speed,VCC Tolerance,Package,etc...)refer to thecurrent Memory Shortform
catalogue.
For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest
to you.
17/20
M28F102
PLCC44 - 44 lead Plastic Leaded Chip Carrier, square
mm
Min
inches
Min
Symb
Typ
Max
4.70
3.04
0.53
0.81
17.65
16.66
16.00
17.65
16.66
16.00
–
Typ
Max
0.185
0.120
0.021
0.032
0.695
0.656
0.630
0.695
0.656
0.630
–
A
A1
B
4.20
2.29
0.33
0.66
17.40
16.51
14.99
17.40
16.51
14.99
–
0.165
0.090
0.013
0.026
0.685
0.650
0.590
0.685
0.650
0.590
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.050
N
44
44
CP
0.10
0.004
PLCC44
D
D1
A1
1 N
B1
e
Ne
E1 E
D2/E2
B
Nd
A
CP
PLCC
Drawing is not to scale
18/20
M28F102
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
14.20
12.50
10.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.559
0.492
0.398
–
A
A1
A2
B
0.05
0.95
0.17
0.10
13.80
12.30
9.90
–
0.002
0.037
0.007
0.004
0.543
0.484
0.390
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
40
40
CP
0.10
0.004
TSOP40
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale
19/20
M28F102
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - China - Brazil - France - Germany -Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.
20/20
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