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M28F201-70XN1R

更新时间：2024-10-29 02:11:08

品牌：STMICROELECTRONICS

描述：2 Mb 256K x 8, Chip Erase FLASH MEMORY

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规格参数
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M28F201-70XN1R 概述

2 Mb 256K x 8, Chip Erase FLASH MEMORY 2 Mb的256K ×8 ，芯片擦除闪存闪存

M28F201-70XN1R 规格参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP	包装说明：	8 X 20 MM, REVERSE, TSOP-32
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.89	最长访问时间：	70 ns
命令用户界面：	YES	数据轮询：	NO
JESD-30 代码：	R-PDSO-G32	JESD-609代码：	e0
长度：	18.4 mm	内存密度：	2097152 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	端子数量：	32
字数：	262144 words	字数代码：	256000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP1-R
封装等效代码：	TSSOP32,.8,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
编程电压：	12 V	认证状态：	Not Qualified
反向引出线：	YES	座面最大高度：	1.2 mm
最大待机电流：	0.0001 A	子类别：	Flash Memories
最大压摆率：	0.03 mA	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
切换位：	NO	类型：	NOR TYPE
宽度：	8 mm	Base Number Matches：	1

M28F201-70XN1R 数据手册

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M28F201

2 Mb (256K x 8, Chip Erase) FLASH MEMORY

5V ± 10% SUPPLY VOLTAGE

12V PROGRAMMING VOLTAGE

FAST ACCESS TIME: 70ns

BYTE PROGRAMMING TIME: 10µs typical

ELECTRICALCHIP ERASE in 1s RANGE

LOW POWER CONSUMPTION

– Active Current: 15mAtypical

PLCC32 (K)

TSOP32 (N)

8 x 20 mm

– Stand-by Current: 10µA typical

10,000 PROGRAM/ERASE CYCLES

INTEGRATED ERASE/PROGRAM-STOP

TIMER

OTP COMPATIBLE PACKAGES and PINOUTS

ELECTRONIC SIGNATURE

– ManufacturerCode: 20h

Figure 1. Logic Diagram

– Device Code: F4h

DESCRIPTION

The M28F201 FLASH Memory product is a non-

volatile memories which may be erased electrically

at the chip level and programmed byte-by-byte. It

is organised as 256K bytes. It uses a command

and thus provide a simple microprocessor inter-

face. The M28F201 FLASH Memory product is

suitable for applicationswhere the memory has to

be reprogrammed in the equipment. The access

time of 70ns makes the device suitable for use in

high speed microprocessor systems.

A0-A17

DQ0-DQ7

M28F201

Table 1. Signal Names

A0-A17

Address Inputs

Data Inputs / Outputs

Chip Enable

DQ0-DQ7

AI00637C

Output Enable

Write Enable

V_PP

V_CC

V_SS

Program Supply

Supply Voltage

Ground

April 1997

1/21

M28F201

Figure 2A. LCC Pin Connections

Figure 2B. TSOP Pin Connections

A11

A10

1 32

A13

A14

A17

DQ7

DQ6

DQ5

DQ4

DQ3

A14

A13

M28F201

(Normal)

M28F201

25 A11

A16

DQ2

DQ1

DQ0

A10

A15

A12

DQ0

DQ7

AI00638C

AI00639C

Figure 2C. TSOP Reverse Pin Connections

DEVICE OPERATION

The M28F201 FLASH Memory product employs a

technologysimilar to a 2 Megabit EPROM but add

to the device functionality by providing electrical

erasure and programming. These functions are

managed by a command register. The functions

that are addressed via the command register de-

pend on the voltage applied to the V_PP, program

voltage, input. When V_PPis less than or equal to

6.5V, the command register is disabled and the

M28F201 functions as a read only memory provid-

ing operating modes similar to an EPROM (Read,

Output Disable, Electronic Signature Read and

Standby).WhenV_PPisraised to 12Vthe command

Erase and Program operations.

A10

A11

DQ7

DQ6

DQ5

DQ4

DQ3

A13

A14

A17

M28F201

(Reverse)

DQ2

DQ1

DQ0

A16

A15

A12

READ ONLY MODES, V_PP≤ 6.5V

For all Read Only Modes, except Standby Mode,

the Write Enable input W should be High. In the

Standby Mode this input is ’don’t care’.

Read Mode. The M28F201 has two enable inputs,

E and G, both of which must be Low in order to

output data from the memory. The Chip Enable (E)

is the power control and should be used for device

selection. Output Enable (G) is the output control

and should be used to gate data on to the output,

independantof the device selection.

AI00640D

2/21

M28F201

Table 2. Absolute Maximum Ratings

Symbol

T_A

Parameter

Value

–40 to 125

–65 to 150

–0.6 to 7

Unit

°C

Ambient Operating Temperature

Storage Temperature

Input or Output Voltages

Supply Voltage

T_STG

V_IO

V_CC

–0.6 to 7

V_A9

A9 Voltage

–0.6 to 13.5

Program Supply Voltage, during Erase

or Programming

V_PP

–0.6 to 14

Note: Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above

those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended

periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

(1)

Table 3. Operations

V_PP

Operation

Read

V_IL

V_IH

DQ0 - DQ7

Data Output

Hi-Z

V_IL

V_IH

V_IL

V_IH

Output Disable

Standby

V_IH

Read Only

V_PPL

Hi-Z

Electronic Signature

Read

V_IL

V_IH

V_ID

Codes

V_IH

Data Output

Data Input

Hi-Z

Read/Write ⁽²⁾

V_PPH

Write

V_ILPulse

V_IH

Output Disable

Standby

Hi-Z

Notes: 1. X = V_ILor V_IH.

2. Refer also to the Command table.

Table 4. Electronic Signature

Identifier

Manufacturer’s Code

Device Code

V_IL

V_IH

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Hex Data

20h

F4h

3/21

M28F201

Table 5. Commands ⁽¹⁾

1st Cycle

A0-A17

2nd Cycle

A0-A17

Command

Cycles

Operation

DQ0-DQ7

Operation

DQ0-DQ7

Read

Write

00h

Read

00000h

00001h

20h

F4h

Electronic

Write

80h or 90h

20h

Signature ⁽²⁾

Setup Erase/

Erase

Write

Read

20h

Erase Verify

Setup Program/

Program

Write

A0-A17

A0h

40h

Data Output

Write

Read

Write

A0-A17

Data Input

Data Output

FFh

Program Verify

Write

C0h

FFh

Reset

Notes: 1. X = V_ILor V_IH.

2. Refer also to the Electronic Signature table.

Standby Mode. In the Standby Mode the maxi-

mum supply current is reduced. The device is

placed in the Standby Mode by applying a High

level to the Chip Enable (E) input. When in the

StandbyMode the outputsare ina highimpedance

state, independant of the Output Enable (G) input.

data at any location in the memory. Read mode is

set-up with one cycle only and may be followed by

any number of read operations to output data.

Electronic SignatureRead mode is set-up with one

cycle and followed by a read cycle to output the

manufactureror device codes.

Awrite tothe commandregisteris madebybringing

WLow whileE is Low. Thefalling edgeofWlatches

Addresses, while the rising edge latches Data,

which are used for those commands that require

address inputs, command input or provide data

output. The supply voltage V_CCand the program

voltage V_PPcan be applied in any order. When the

device is powered up or when V_PPis ≤ 6.5V the

contentsof the command register defaults to 00h,

thus automatically setting-up Read operations. In

addition a specific command may be used to set

the command register to 00h for reading the mem-

ory. The system designer may chose to provide a

constant high V_PPand use the register commands

for all operations,or to switch the V_PPfrom low to

high only when needing to erase or program the

memory. All command register access is inhibited

whenV_CCfallsbelowthe Erase/Write LockoutVolt-

age (V_LKO) of 2.5V.

Output Disable Mode. When the Output Enable

(G) is High the outputs are in a high impedance

state.

Electronic Signature Mode. This mode allowsthe

read out of two binary codes from the device which

identify the manufacturer and device type. This

mode is intended for use by programming equip-

ment to automatically select the correct erase and

programmingalgorithms.The ElectronicSignature

Mode is active when a high voltage (11.5V to 13V)

is appliedtoaddresslineA9 with EandG Low.With

A0 Low the output data is the manufacturer code,

when A0 is High the output is the device code. All

other address lines should be maintained Low

while reading the codes. The electronic signature

can also be accessed in Read/Write modes.

READ/WRITE MODES, 11.4V ≤ V_PP≤ 12.6V

If the device is deselected during Erasure, Pro-

gramming or verifying it will draw active supply

currents until the operationsare terminated.

The device is protected against stress caused by

long erase or program times. If the end ofErase or

Programming operations are not terminated by a

Verify cycle within a maximum time permitted, an

internal stop timer automatically stops the opera-

tion. The device remains in an inactivestate, ready

to start a Verify or ResetMode operation.

When V_PPis High both read and write operations

may be performed. These are defined by the con-

tents of an internalcommand register. Commands

may be written to this register to set-up and exe-

cute, Erase,Erase Verify, Program, Program Verify

and Reset modes. Each of these modes needs 2

cycles. Each mode starts with a write operationto

set-up the command, this is followedbyeither read

or write operations. The device expects the first

cycle to be a write operation and doesnot corrupt

4/21

M28F201

Table 6. AC Measurement Conditions

SRAM Interface Levels

EPROM Interface Levels

Input Rise and Fall Times

≤ 10ns

0 to 3V

1.5V

≤ 10ns

Input Pulse Voltages

0.45V to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

SRAM Interface

1N914

1.5V

3.3kΩ

DEVICE

UNDER

TEST

OUT

= 30pF or 100pF

EPROM Interface

2.4V

2.0V

0.8V

0.45V

= 30pF for SRAM Interface

AI01275

= 100pF for EPROM Interface

includes JIG capacitance

AI01276

Table 7. Capacitance ⁽¹⁾(T_A= 25 °C, f = 1 MHz )

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

V_IN= 0V

Min

Max

Unit

C_OUT

V_OUT= 0V

Note: 1. Sampled only, not 100% tested.

Read Mode. The Read Mode is the default at

power up or may be set-up by writing 00h to the

command register. Subsequent read operations

outputdata from thememory. Thememory remains

in the Read Mode until a new command is written

to the command register.

Electronic Signature Mode. Inorder to select the

correct erase and programmingalgorithms for on-

board programming, the manufacturerand device

codes may be read directly. It is not neccessaryto

apply a high voltage to A9 when using the com-

mand register. The Electronic Signature Mode is

set-up by writing 80h or 90h to the command

inputs 00000h or 00001h,output the manufacturer

or device codes. The command is terminated by

writing another valid command to the command

5/21

M28F201

Table 8. DC Characteristics

(T_A= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; V_CC= 5V ± 10%)

Symbol

I_LI

Parameter

Test Condition

0V ≤ V_IN≤ V_CC

0V ≤ V_OUT≤ V_CC

E = V_IL, f = 10MHz

E = V_IH

Min

Max

±1

Unit

µA

Input Leakage Current

I_LO

Output Leakage Current

±10

µA

I_CC

Supply Current (Read)

µA

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Supply Current (Programming)

Supply Current (Program Verify)

Supply Current (Erase)

I_CC1

E = V_CC± 0.2V

During Programming

During Verify

100

(1)

I_CC2

µA

(1)

I_CC3

(1)

I_CC4

During Erasure

During Erase Verify)

(1)

I_CC5

Supply Current (Erase Verify)

Program Leakage Current

I_LPP

I_PP

_PP≤ V_CC

V_PP> V_CC

_PP≤ V_CC

V_PP= V_PPH, During Programming

±10

200

±10

µA

Program Current (Read or

Standby)

µA

(1)

I_PP1

Program Current (Programming)

Program Current (Program

Verify)

(1)

I_PP2

_PP= V_PPH, During Verify

(1)

I_PP3

Program Current (Erase)

Program Current (Erase Verify)

Input Low Voltage

V_PP= V_PPH, During Erase

(1)

I_PP4

V_PP= V_PPH, During Erase Verify

V_IL

V_IH

–0.5

0.8

Input High VoltageTTL

Input High Voltage CMOS

Output Low Voltage

V_CC+ 0.5

0.45

0.7 V_CC

V_OL

I_OL= 5.8mA

_OH= –100µA

_OH= –2.5mA

V_CC– 0.4

0.85 V_CC

2.4

Output High Voltage CMOS

V_OH

Output High Voltage TTL

Program Voltage(Read

Operations)

V_PPL

6.5

Program Voltage(Read/Write

Operations)

V_PPH

V_ID

11.4

11.5

12.6

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

(1)

I_ID

A9 = V_ID

200

µA

Supply Voltage, Erase/Program

Lock-out

V_LKO

2.5

Note: 1. Not 100% tested. Characterisation Data available.

6/21

M28F201

Table 9. Read Only Mode AC Characteristics

((T_A= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

M28F201

-120

V_CC

-70

-90

-150

V_CC

Symbol

Alt

Parameter

Test Condition

Unit

5V±10%

EPROM

Interface

EPROM

Interface

EPROM

Interface

EPROM

Interface

Min Max Min Max Min Max Min Max

Write Enable High to

Output Enable Low

t_WHGL

t_AVAV

t_AVQV

µs

t_RC

Read Cycle Time

E = V_IL, G = V_IL

120

150

Address Valid to

Output Valid

t_ACC

120

150

Chip Enable Low to

Output Transition

(1)

t_ELQX

t_LZ

t_CE

t_OLZ

t_OE

G = V_IL

Chip Enable Low to

Output Valid

t_ELQV

Output Enable Low

to Output Transition

(1)

t_GLQX

E = V_IL

Output Enable Low

to Output Valid

t_GLQV

E = V_IL

Chip Enable High to

Output Hi-Z

(1)

t_EHQZ

G = V_IL

Output Enable High

to Output Hi-Z

(1)

t_GHQZ

t_DF

t_OH

E = V_IL

Address Transition

to Output Transition

t_AXQX

E = V_IL, G = V_IL

Note: 1. Sampled only, not 100% tested

Erase and Erase Verify Modes. The memory is

erased by first Programming all bytes to 00h, the

Erase command then erases them to FFh. The

Erase Verify command is then used to read the

memory byte-by-byte for a content of FFh. The

Erase Mode is set-up by writing 20h to the com-

mand register. The write cycle is then repeated to

start the erase operation. Erasure starts on the

rising edge of W during this second cycle. Erase is

followed by an Erase Verify which reads an ad-

dressed byte. Erase Verify Mode is set-up by writ-

ing A0h to the command register and at the same

time supplying the address of the byte to be veri-

fied. The rising edge of W during the set-up of the

first Erase Verify Mode stops the Erase operation.

The following read cycle is made with an internally

generated margin voltage applied; reading FFh

indicatesthat all bitsof the addressedbyte arefully

erased. The whole contents of the memory are

verified by repeating the Erase Verify Operation,

first writing the set-up code A0h with the address

of the byte to be verified and then reading the byte

contentsin a secondread cycle.

As the Erasealgorithm flow chart shows, when the

data read during Erase Verify is not FFh, another

Erase operation is performed and verification con-

tinuesfromtheaddressofthelast verifiedbyte.The

command is terminated by writing another valid

command to the command register (for example

Program or Reset).

7/21

M28F201

Figure 5. Read Mode AC Waveforms

tAVAV

A0-A17

tAVQV

tELQV

tAXQX

tEHQZ

tELQX

tGLQV

tGLQX

tGHQZ

DQ0-DQ7

DATA OUT

AI00642

Figure 6. Read Command Waveforms

tVPHEL

VALID

A0-A17

tAVQV

tAXQX

tELWL

tWHEH

tELQV

tEHQZ

tGHQZ

tGHWL

tWHGL

tWLWH

tGLQV

tDVWH

tWHDX

DQ0-DQ7

COMMAND

DATA OUT

READ SET-UP

READ

AI00643

8/21

M28F201

Figure 7. Electronic Signature Command Waveforms

tVPHEL

00000h-00001h

A0-A17

tAVQV

tELQV

tAXQX

tEHQZ

tGHQZ

tELWL

tWHEH

tGHWL

tWHGL

tWLWH

tDVWH

tGLQV

tWHDX

DQ0-DQ7

COMMAND

DATA OUT

READ ELECTRONIC

SIGNATURE SET-UP

READ

MANUFACTURER

OR DEVICE

AI00644

Program and Program Verify Modes. The Pro-

gramMode isset-upbywriting40htothe command

which latches the address and data of the byte to

be programmed. The rising edge of W during this

second cycle starts the programming operation.

Programmingis followedby aProgramVerifyofthe

data written.

gramming operation. The following read cycle, of

the address already latched during programming,

is made with an internally generated margin volt-

ageapplied,readingvaliddataindicatesthatallbits

have been programmed.

Reset Mode. This commandis usedtosafely abort

Erase or Program Modes. The Reset Mode is

set-up and performed by writing FFh two times to

the command register. The command should be

followed by writing a valid command to the the

command register (for example Read).

ProgramVerifyModeis set-upby writing C0h to the

commandregister. The rising edgeof Wduring the

set-up of the Program Verify Mode stops the Pro-

9/21

M28F201

Table 10A. Read/Write Mode AC Characteristics, W and E Controlled

(T_A= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

M28F201

-70

-90

Symbol

Alt

Parameter

Unit

V_CC= 5V ± 10% V_CC= 5V ± 10%

EPROM

Interface

EPROM

Interface

Min

Max

Min

Max

t_VPHEL

t_VPHWL

t_WHWH3

t_EHEH3

t_AVWL

t_AVEL

V_PPHigh to Chip Enable Low

µs

V_PPHigh to Write Enable Low

t_WC

t_AS

Write Cycle Time(W controlled)

Write Cycle Time(E controlled)

Address Valid to Write Enable Low

Address Valid to Chip Enable Low

t_WLAX

t_ELAX

t_AH

Write Enable Low to Address Transition

Chip Enable Low to Address Transition

Chip Enable Low to Write Enable Low

Write Enable Low to Chip Enable Low

Output Enable High to Write Enable Low

Output Enable High to ChipEnable Low

Input Valid to Write Enable High

t_ELWL

t_CS

t_WLEL

t_GHWL

t_GHEL

t_DVWH

t_DVEH

t_WLWH

t_ELEH

t_DS

t_WP

t_DH

9.5

Input Valid to Chip Enable High

Write Enable Low to Write Enable High (Write Pulse)

Chip Enable Low to Chip Enable High (Write Pulse)

Write Enable High to Input Transition

Chip Enable High to Input Transition

Duration of Program Operation (W contr.)

Duration of Program Operation (E contr.)

Duration of Erase Operation (W contr.)

Duration of Erase Operation (E contr.)

Write Enable High to Chip Enable High

Chip Enable High to Write Enable High

t_WHDX

t_EHDX

t_WHWH1

t_EHEH1

t_WHWH2

t_EHEH2

t_WHEH

t_EHWH

t_WHWL

t_EHEL

t_CH

t_WPHWrite Enable High to Write Enable Low

Chip Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Chip Enable High to Output Enable Low

t_ACCAddess Valid to data Output

t_WHGL

t_EHGL

t_AVQV

(1)

t_ELQX

t_LZ

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

t_ELQV

t_CE

(1)

t_GLQX

t_OLZOutput Enable Low to Output Transition

t_GLQV

t_OE

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

(1)

t_EHQZ

(1)

t_GHQZ

t_DF

t_OH

t_AXQX

Note: 1. Sampled only, not 100% tested

10/21

M28F201

Table 10B. Read/Write Mode AC Characteristics, W and E Controlled

(T_A= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

M28F201

-120

-150

Symbol

Alt

Parameter

Unit

V_CC= 5V ± 10% V_CC= 5V ± 10%

EPROM

Interface

EPROM

Interface

Min

Max

Min

Max

t_VPHEL

t_VPHWL

t_WHWH3

t_EHEH3

t_AVWL

t_AVEL

V_PPHigh to Chip Enable Low

µs

V_PPHigh to Write Enable Low

t_WC

t_AS

Write Cycle Time(W controlled)

120

150

Write Cycle Time(E controlled)

Address Valid to Write Enable Low

Address Valid to Chip Enable Low

t_WLAX

t_ELAX

t_AH

Write Enable Low to Address Transition

Chip Enable Low to Address Transition

Chip Enable Low to Write Enable Low

Write Enable Low to Chip Enable Low

Output Enable High to Write Enable Low

Output Enable High to ChipEnable Low

Input Valid to Write Enable High

t_ELWL

t_CS

t_WLEL

t_GHWL

t_GHEL

t_DVWH

t_DVEH

t_WLWH

t_ELEH

t_DS

t_WP

t_DH

9.5

Input Valid to Chip Enable High

Write Enable Low to Write Enable High (Write Pulse)

Chip Enable Low to Chip Enable High (Write Pulse)

Write Enable High to Input Transition

Chip Enable High to Input Transition

Duration of Program Operation (W contr.)

Duration of Program Operation (E contr.)

Duration of Erase Operation (W contr.)

Duration of Erase Operation (E contr.)

Write Enable High to Chip Enable High

Chip Enable High to Write Enable High

t_WHDX

t_EHDX

t_WHWH1

t_EHEH1

t_WHWH2

t_EHEH2

t_WHEH

t_EHWH

t_WHWL

t_EHEL

t_CH

t_WPHWrite Enable High to Write Enable Low

Chip Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Chip Enable High to Output Enable Low

t_ACCAddess Valid to data Output

t_WHGL

t_EHGL

t_AVQV

120

150

(1)

t_ELQX

t_LZ

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

t_ELQV

t_CE

(1)

t_GLQX

t_OLZOutput Enable Low to Output Transition

t_GLQV

t_OE

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

(1)

t_EHQZ

(1)

t_GHQZ

t_DF

t_OH

t_AXQX

Note: 1. Sampled only, not 100% tested

11/21

M28F201

Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled

12/21

M28F201

Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled

13/21

M28F201

Figure 10. Program Set-up and Program Verify Commands Waveforms - W Controlled

14/21

M28F201

Figure 11. Program Set-up and Program Verify Commands Waveforms - E Controlled

15/21

M28F201

Figure 12. Erasing Flowchart

Figure 13. ProgrammingFlowchart

= 12V

PROGRAM ALL

BYTES TO 00h

n = 0

n=0, Addr=00000h

PROGRAM SET-UP

Latch Addr, Data

ERASE SET-UP

Wait 10ms

Wait 10µs

PROGRAM VERIFY

ERASE VERIFY

Latch Addr.

YES

++n

= 25

Wait 6µs

++n

YES

Wait 6µs

1000

READ DATA OUTPUT

FAIL

6.5V

READ DATA OUTPUT

FAIL

6.5V

Data

Addr++

Data

Addr++

YES

Last

Addr

Last

Addr

YES

READ COMMAND

YES

READ COMMAND

< 6.5V, PASS

AI00677

< 6.5V, PASS

AI00649

PRESTO F ERASE ALGORITHM

PRESTO F PROGRAM ALGORITHM

The PRESTO F Erase Algorithm guarantees that

the device will be erased in a reliable way. The

algorithm first programs all bytes to 00h in order to

ensure uniform erasure. The programming follows

the PRESTO F Programming Algorithm. Erase is

set-up by writing 20h to the command register, the

erasure is started by repeating this write cycle.

Erase Verify is set-up by writing A0h to the com-

mand register together with the address of the byte

to beverified. Thesubsequentread cycle readsthe

datawhichis comparedto FFh. Erase Verifybegins

at address0000h andcontinuesto the lastaddress

or until the comparison of the data to FFh fails. If

this occurs, the address of the last byte checked is

stored and a new Erase operation performed.

EraseVerify thencontinuesfrom the addressof the

stored location.

The PRESTO F Programming Algorithm applies a

series of 10µs programming pulses to a byte until

a correct verify occurs. Up to 25 programming

operations are allowed for one byte. Program is

set-up by writing 40h to the command register, the

programming is started after the next write cycle

which also latches the address and data to be

programmed. Program Verify is set-up by writing

C0h to the command register, followed by a read

cycle and a compare of the data read to the data

expected. During Program and Program Verify op-

erations a MARGIN MODE circuit is activated to

guaranteethat thecell is programmed with asafety

margin.

16/21

M28F201

ORDERING INFORMATION SCHEME

Example:

M28F201

-70 X

1 TR

Operating Voltage

Option

Reverse

Pinout

TR Tape & Reel

Packing

Speed

Power Supplies

blank V_CC± 10%

_CC± 5%

Package

Temperature Range

-70

-90

70 ns

90 ns

PLCC32

0 to 70 °C

TSOP32

8 x 20 mm

–40 to 125 °C

–40 to 85 °C

-120

-150

120 ns

150 ns

Devices are shipped from the factory with the memory content erased (to FFh).

For alist of availableoptions(Speed, Package, etc...) orfor further information on any aspectof thisdevice,

please contact the SGS-THOMSON Sales Office nearest to you.

17/21

M28F201

PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

Min

2.54

1.52

0.33

0.66

12.32

11.35

9.91

14.86

13.89

12.45

–

inches

Min

Symb

Typ

Max

3.56

2.41

0.53

0.81

12.57

11.56

10.92

15.11

14.10

13.46

–

Typ

Max

0.140

0.095

0.021

0.032

0.495

0.455

0.430

0.595

0.555

0.530

–

0.100

0.060

0.013

0.026

0.485

0.447

0.390

0.585

0.547

0.490

–

1.27

0.050

0.10

0.004

PLCC32

1 N

E1 E

D2/E2

PLCC

Drawing is not to scale.

18/21

M28F201

TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm

Min

inches

Min

Symb

Typ

Max

1.20

0.17

1.50

0.27

0.21

20.20

18.50

8.10

–

Typ

Max

0.047

0.006

0.059

0.011

0.008

0.795

0.728

0.319

–

0.05

0.95

0.15

0.10

19.80

18.30

7.90

–

0.002

0.037

0.006

0.004

0.780

0.720

0.311

–

0.50

0.020

0.50

0°

0.70

5°

0.020

0°

0.028

5°

0.10

0.004

TSOP32

N/2

DIE

TSOP-a

Drawing is not to scale.

19/21

M28F201

TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm

Min

inches

Min

Symb

Typ

Max

1.20

0.17

1.50

0.27

0.21

20.20

18.50

8.10

–

Typ

Max

0.047

0.006

0.059

0.011

0.008

0.795

0.728

0.319

–

0.05

0.95

0.15

0.10

19.80

18.30

7.90

–

0.002

0.037

0.006

0.004

0.780

0.720

0.311

–

0.50

0.020

0.50

0°

0.70

5°

0.020

0°

0.028

5°

0.10

0.004

TSOP32

N/2

DIE

TSOP-b

Drawing is not to scale.

20/21

M28F201

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express

written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea- Malaysia - Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.

21/21

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