M28F411-100N3TR [STMICROELECTRONICS]
512KX8 FLASH 12V PROM, 100ns, PDSO40, 10 X 20 MM, PLASTIC, TSOP-40;
| 型号： | M28F411-100N3TR |
| 厂家： | 
ST |
| 描述： | 512KX8 FLASH 12V PROM, 100ns, PDSO40, 10 X 20 MM, PLASTIC, TSOP-40 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总34页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28F411
M28F421
4 Megabit (x 8, Block Erase) FLASH MEMORY
PRELIMINARY DATA
SMALL SIZE PLASTIC PACKAGETSOP40
MEMORY ERASE in BLOCKS
– One 16K Byte Boot Block (top or bottomlo-
cation) with hardware write and erase pro-
tection
– Two 8K Byte Key Parameter Blocks
– One 96K Byte Main Block
– Three 128K Byte Main Blocks
5V ± 10% SUPPLYVOLTAGE
TSOP40 (N)
10 x 20mm
12V ± 5% PROGRAMMING VOLTAGE
100,000 PROGRAM/ERASE CYCLES
PROGRAM/ERASE CONTROLLER
AUTOMATIC STATIC MODE
LOW POWER CONSUMPTION
– 60µA Typical in Standby
Figure 1. Logic Diagram
– 0.2µA Typical in Deep Power Down
– 20/25mATypical Operating Consumption
HIGH SPEED ACCESS TIME: 70ns
EXTENDED TEMPERATURE RANGES
V
V
PP
CC
DESCRIPTION
The M28F411 and M28F421 FLASH MEMORIES
are non-volatile memories that may be erased
electrically at the block level and programmed by
byte.
19
8
A0-A18
DQ0-DQ7
RP
W
E
Table 1. Signal Names
M28F411
M28F421
A0-A18
DQ0-DQ7
E
Address Inputs
Data Input / Outputs
Chip Enable
G
G
Output Enable
W
Write Enable
V
SS
RP
Reset/Power Down/Boot Block Unlock
Program Supply
Supply Voltage
AI01131C
VPP
VCC
VSS
Ground
October 1995
1/34
This is preliminary informationon a new product now in developmentor undergoingevaluation. Detailsare subject to change without notice.
M28F411, M28F421
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
grade 1
grade 3
grade 5
grade 6
0 to 70
–40 to 125
–20 to 85
–40 to 85
°C
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
–50 to 125
–65 to 150
–0.6 to 7
°C
°C
V
(2, 3)
VIO
VCC
–0.6 to 7
V
(2)
VA9
A9 Voltage
–0.6 to 13.5
V
Program Supply Voltage, during Erase
or Programming
(2)
VPP
–0.6 to 14
V
(2)
VRP
RP Voltage
–0.6 to 13.5
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Maximum DC voltage on I/O is VCC + 0.5V, overshoot to 7V allowed for less than 20ns.
Figure 2. TSOP Pin Connections
DEVICE OPERATION (cont’d)
The interface is directly compatible with most mi-
croprocessors. TSOP40 (10 x 20mm) package is
used.
A16
A15
A14
A13
A12
A11
A9
1
40
A17
Organization
V
SS
The M28F411 and M28F421 are organized as
512K x 8. Memory control is provided by Chip
Enable, Output Enable and Write Enable inputs. A
Reset/Power Down/Boot block unlock, tri-level in-
put, places the memory in deep power down, nor-
mal operation or enables programming and
erasure of the Boot block.
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
A8
Blocks
W
M28F411
M28F421
(Normal)
Erasure of the memories is in blocks. There are 7
blocks in the memory address space, one Boot
Block of 16K Bytes, two ’Key Parameter Blocks’ of
8K Bytes, one ’Main Block’ of 96K Bytes, and three
’Main Blocks’ of 128K Bytes. The M28F411 mem-
ory has the Boot Block at the top of the memory
addressspace(7FFFFh) andthe M28F421locates
the Boot Block starting at the bottom (00000h).
Erasure of each block takes typically 1 second and
each block can be programmed and erased over
100,000 cycles.
RP
10
11
31
30
V
V
CC
V
PP
DU
CC
NC
A18
A7
A6
A5
A4
A3
A2
A1
DQ3
DQ2
DQ1
DQ0
G
V
SS
E
The Boot Block is hardware protected from acci-
dental programming or erasure depending on the
RP signal. Program/Erase commands in the Boot
Block are executedonly when RP is at 12V.
20
21
A0
AI01134C
Blockerasuremaybesuspendedwhiledatais read
from other blocks of the memory, then resumed.
Warning: NC = Not Connected, DU = Don’t Use
2/34
M28F411, M28F421
Table 3. Operations
Operation
Read Byte
E
G
VIL
VIH
VIH
X
W
VIH
VIL
VIH
X
RP
VIH
VIH
VIH
VIH
VIL
DQ0 - DQ7
Data Output
Data Input
Hi-Z
VIL
VIL
VIL
VIH
X
Write Byte
Output Disable
Standby
Hi-Z
Power Down
X
X
Hi-Z
Note: X = VIL or VIH, VPP = VPPL or VPPH
Table 4. Electronic Signature
Code
Device
E
G
W
A0
A9
VID
VID
VID
A1-A8 & A10-A18
Don’t Care
DQ0 - DQ7
20h
Manufact. Code
Device Code
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIH
VIH
M28F411
M28F421
Don’t Care
0F6h
Don’t Care
0FEh
Note: RP = VIH
Bus Operations
takes typically 9µs, block erase typically 1 second.
Erasure of a memory block may be suspended in
order to read data from another block and then
resumed. A Status Register may be read at any
time, including during the programming or erase
cycles, to monitor the progressof the operation.
Sixoperationscan beperformedbytheappropriate
bus cycles, Read Byte from the Array, Read Elec-
tronic Signature, Output Disable, Standby, Power
Down and Write the Command of an Instruction.
Command Interface
Power Saving
Commands can bewritten to aCommand Interface
(C.I.)latch to perform read, programming, erasure
and to monitor the memory’s status. When power
is first applied, on exit from power down or if VCC
falls below VLKO, the command interface is reset to
Read Memory Array.
The M28F411 and M28F421 have a number of
power saving features. A CMOS standby mode is
entered when the Chip Enable E and the Re-
set/PowerDown(RP) signalsare at VCC, when the
supply current drops to typically 60µA. A deep
power down mode is enabled when the Re-
set/Power Down (RP) signal is at VSS, when the
supply current drops to typically 0.2µA. The time
requiredto awakefromthedeeppowerdownmode
is 300ns maximum, with instructions to the C.I.
recognised after only 210ns.
Instructions and Commands
Eight Instructions are defined to perform Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, Erase, Program, Clear Status
Register, Erase Suspend and Erase Resume. An
internalProgram/EraseController(P/E.C.) handles
all timing and verificationof the Programand Erase
instructions and provides status bits to indicate its
operation and exit status. Instructions are com-
posed of a first command write operation followed
by either second command write, to confirm the
commands for programming or erase, or a read
operationtoread datafromthe array,theElectronic
Signatureor the Status Register.
DEVICE OPERATION
Signal Descriptions
A0-A18 Address Inputs. The address signals,
inputs for the memory array, are latched during a
write operation.
A9 Address Input is also used for the Electronic
SignatureOperation. When A9 is raised to 12V the
Electronic Signature may be read. The A0 signal is
used to read two bytes, when A0 is Low the Manu-
facturer code is read and when A0 is High the
Device code.
For added data protection, the instructions for byte
programand blockerase consist of two commands
that are written to the memory and which start the
automatic P/E.C. operation. Byte programming
3/34
M28F411, M28F421
Table 5. Instructions
1st Cycle
2nd Cycle
Mnemo
Instruction
nic
Cycles
Operation Address (1)
Data
Operation Address (1)
Data
Read
Memory
Array
Read
Read (2)
RD
1+
1+
3
Write
Write
Write
X
X
X
0FFh
Data
Address
Read
Status
Register
Status
Register
RSR
RSIG
70h
Read (2)
Read (2)
X
Read
Electronic
Signature
Signature
Adress (3)
90h
20h
Signature
Block
Address
EE
PG
Erase
2
2
Write
Write
X
X
Write
Write
0D0h
40h or
10h
Program
Address
Data Input
Clear
Status
Register
CLRS
1
Write
X
50h
Erase
Suspend
ES
ER
1
1
Write
Write
X
X
0B0h
0D0h
Erase
Resume
Notes: 1. X = Don’t Care.
2. The first cycle of the RD, RSR or RSIG instruction is followed by read operations toread memory array, Status Register
or Electronic Signature codes. Any number of Read cycle can occur after one command cycle.
3. Signature address bit A0=VIL will output Manufacturer code. Address bit A0=VIH will output Device code. Other address bits are
ignored.
memory Array, the Electronic Signature or Status
Register is valid when Chip Enable E and Output
EnableG are active. Theoutput is high impedance
when the chip is deselected or the outputs are
disabled.
Table 6. Commands
Hex Code
Command
00h
10h
Invalid/Reserved
Alternative Program Set-up
Erase Set-up
E Chip Enable. The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High de-selects the memory
and reducesthe powerconsumptionto thestandby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at alow level. Both addressesand data
inputs are then latched on the rising edge of E.
20h
40h
Program Set-up
50h
Clear Status Register
Read Status Register
Read Electronic Signature
Erase Suspend
70h
90h
RP Reset/Power Down. This is a tri-level input
which locks the Boot Block from programming and
erasure, and allows the memory to be put in deep
powerdown.
0B0h
0D0h
0FFh
Erase Resume/Erase Confirm
Read Array
When RP is High (up to 6.5V maximum) the Boot
Block is locked and cannot be programmed or
erased. When RP is above 11.4V the Boot Block is
unlocked for programming or erasure.
DQ0-DQ7 Data Input/Outputs. The data inputs, a
byte to be programmed or a command to the C.I.,
are latched when both Chip Enable E and Write
Enable W are active. The data output from the
With RP Low the memory is in deep power down,
and if RP is within VSS+0.2V the lowest supply
current is absorbed.
4/34
M28F411, M28F421
Table 7. Status Register
Mnemon
Logic
Level
Bit
Name
Definition
Ready
Note
ic
’1’
’0’
’1’
Indicates the P/E.C. status, check during Program
or Erase, and on completion before checking bits
b4 or b5 for Program or Erase Success
P/ECS
7
P/E.C. Status
Busy
Suspended
Erase
Suspend
Status
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until an
Erase Resume instruction is given.
ESS
ES
6
5
4
3
In progress or
Completed
’0’
’1’
’0’
’1’
Erase Error
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
Erase Status
Erase Success
Program Error
Program
Status
PS bit set to ’1’ if the P/E.C. has failed to program
a byte.
PS
Program
Success
’0’
’1’
’0’
V
PP Low, Abort
VPPS bit is set if the VPP voltage is below
PPH(min) when a Program or Erase instruction
VPPS
VPP Status
V
has been executed.
VPP OK
2
1
0
Reserved
Reserved
Reserved
Notes: Logic level ’1’ is High, ’0’ is Low.
G Output Enable. The Output Enable gates the
outputs through the data buffers during a read
operation.
two productsissimply aninversionoftheblockmap
to position the Boot Block at the top or bottom of
the memory. The selectionof the Boot Block at the
top or bottom of the memory depends on the
microprocessor needs.
W Write Enable. It controls writing to the Com-
mand Register and Input Address and Data
latches. Both Addresses and Data Inputs are
latched on the rising edge of W.
Each block of the memory can be erased sepa-
rately, but only by one block at a time. The erase
operation is managed by the P/E.C. but can be
suspended in orderto read from another block and
then resumed.
VPP ProgramSupply Voltage. Thissupplyvoltage
is used for memory Programming and Erase.
VPP ±10% toleranceoption is provided for applica-
tion requiringmaximum 100write anderase cycles.
Programming and erasure of the memory is dis-
abled when the program supply is at VPPL. For
successful programming and erasure the program
VCC Supply Voltage. It is the main circuit supply.
VSS Ground. It is the reference for all voltage
measurements.
supply must be at VPPH
.
The BootBlockprovides additionalhardwaresecu-
rity by use of the RP signal which must be at VHH
before any program or erase operation will be
executed by the P/E.C. on the Boot Block.
Memory Blocks
The memory blocks of the M28F411and M28F421
are shown in Figure 8. The difference betweenthe
5/34
M28F411, M28F421
Table 8. AC Measurement Conditions
SRAM Interface Levels
EPROM Interface Levels
≤ 10ns
Input Rise and Fall Times
≤ 10ns
0 to 3V
1.5V
Input Pulse Voltages
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
EPROM Interface
C
2.4V
L
2.0V
0.8V
0.45V
C
C
C
= 30pF for SRAM Interface
L
L
L
AI01275
= 100pF for EPROM Interface
includes JIG capacitance
AI01276
Table 9. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
Unit
pF
6
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Operations
device selection. Output Enable should be used to
gatedataontotheoutputindependentofthedevice
selection. The data read depends on the previous
command written to the memory (see instructions
RD, RSR and RSIG).
Operations are defined as specific bus cycles and
signals which allow memory Read, Command
Write, Output Disable, Standby,Power Down, and
Electronic Signature Read. They are shown in Ta-
ble 3.
Write. Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. Awrite operation is initiated when
Chip Enable E is Low and Write Enable W is Low
withOutput EnableG High. Commands, InputData
and Addressesare latchedon the rising edge of W
or E.
Read. Read operations are used to output the
contents of the Memory Array, the Status Register
or the Electronic Signature. Both Chip Enable E
and Output Enable G must be low in order to read
the output of the memory. The Chip Enable input
alsoprovides powercontrol andshouldbe usedfor
6/34
M28F411, M28F421
Table 10. DC Characteristics
(TA = 0 to70°C; VCC = 5V±5% or 5V±10%; VPP = 12V±5%)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±1
Unit
µA
ILO
Output Leakage Current
Supply Current (Read) TTL
Supply Current (Read) CMOS
Supply Current (Standby) TTL
0V ≤ VOUT ≤ VCC
±10
50
µA
E = VIL, f = 10MHz, IOUT = 0mA
E = VSS, f = 10MHz, IOUT = 0mA
E = VIH, RP = VIH
mA
mA
mA
(1, 3)
ICC
45
3
(3)
ICC1
E = VCC ± 0.2V,
RP = VCC ± 0.2V
Supply Current (Standby) CMOS
100
5
µA
µA
Supply Current (Power Down)
CMOS
(3)
ICC2
RP = VSS ± 0.2V
ICC3
ICC4
Supply Current (Program)
Supply Current (Erase)
Program in progress
Erase in progress
50
30
10
mA
mA
mA
(2)
ICC5
Supply Current (Erase Suspend)
E = VIH, Erase suspended
Program Leakage Current (Read or
Standby)
IPP
VPP > VCC
200
µA
IPP1
IPP2
IPP3
IPP4
IPP5
VIL
Program Current (Read or Standby)
Program Current (Power Down)
Program Current (Program)
Program Current (Erase)
Program Current (Erase Suspend)
Input Low Voltage
V
PP ≤ VCC
±10
5
µA
µA
mA
mA
µA
V
RP = VSS ± 0.2V
Program in progress
Erase in progress
Erase suspended
30
30
200
–0.5
2
0.8
VIH
Input High Voltage
VCC + 0.5
0.45
V
VOL
VOH
VPPL
Output Low Voltage
IOL = 5.8mA
V
Output High Voltage
IOH = –2.5mA
2.4
0
V
Program Voltage (Normal operation)
6.5
V
Program Voltage (Program or Erase
operations)
VPPH
11.4
11.4
12.6
V
VID
IID
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
13
V
A9 = VID
500
µA
Supply Voltage (Erase and Program
lock-out)
VLKO
VHH
2
V
V
Input Voltage (RP, Boot unlock)
Boot Block Program or Erase
11.4
13
Notes: 1. Automatic Power Saving reduces ICC to ≤ 8mA typical in static operation.
2. Current increases to ICC + ICC5 during a read operation.
3. CMOS levels VCC ± 0.2V and VSS ± 0.2V. TTL levels VIH and VIL.
7/34
M28F411, M28F421
Table 11. DC Characteristics
(TA = –20 to 85°C or –40 to 85°C ; VCC = 5V±5% or 5V±10%; VPP = 12V±5%)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±1
Unit
µA
ILO
Output Leakage Current
Supply Current (Read) TTL
Supply Current (Read) CMOS
Supply Current (Standby) TTL
0V ≤ VOUT ≤ VCC
±10
65
µA
E = VIL, f = 10MHz, IOUT = 0mA
E = VSS, f = 10MHz, IOUT = 0mA
E = VIH, RP = VIH
mA
mA
mA
(1, 3)
ICC
60
3
(3)
ICC1
E = VCC ± 0.2V,
RP = VCC ± 0.2V
Supply Current (Standby) CMOS
100
8
µA
µA
Supply Current (Power Down)
CMOS
(3)
ICC2
RP = VSS ± 0.2V
ICC3
ICC4
Supply Current (Program)
Supply Current (Erase)
Program in progress
Erase in progress
50
30
10
mA
mA
mA
(2)
ICC5
Supply Current (Erase Suspend)
E = VIH, Erase suspended
Program Leakage Current (Read or
Standby)
IPP
VPP > VCC
200
µA
IPP1
IPP2
IPP3
IPP4
IPP5
VIL
Program Current (Read or Standby)
Program Current (Power Down)
Program Current (Program)
Program Current (Erase)
Program Current (Erase Suspend)
Input Low Voltage
V
PP ≤ VCC
±15
5
µA
µA
mA
mA
µA
V
RP = VSS ± 0.2V
Program in progress
Erase in progress
Erase suspended
30
30
200
–0.5
2
0.8
VIH
Input High Voltage
VCC + 0.5
0.45
V
VOL
VOH
VPPL
Output Low Voltage
IOL = 5.8mA
V
Output High Voltage
IOH = –2.5mA
2.4
0
V
Program Voltage (Normal operation)
6.5
V
Program Voltage (Program or Erase
operations)
VPPH
11.4
11.4
12.6
V
VID
IID
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
13
V
A9 = VID
500
µA
Supply Voltage (Erase and Program
lock-out)
VLKO
VHH
2
V
V
Input Voltage (RP, Boot unlock)
Boot Block Program or Erase
11.4
13
Notes: 1. Automatic Power Saving reduces ICC to ≤ 8mA typical in static operation.
2. Current increases to ICC + ICC5 during a read operation.
3. CMOS levels VCC ± 0.2V and VSS ± 0.2V. TTL levels VIH and VIL.
8/34
M28F411, M28F421
Table 12. DC Characteristics
(TA = –40 to 125°C; VCC = 5V±5% or 5V±10%; VPP = 12V±5%)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±1
Unit
µA
ILO
Output Leakage Current
Supply Current (Read) TTL
Supply Current (Read) CMOS
Supply Current (Standby) TTL
0V ≤ VOUT ≤ VCC
±10
65
µA
E = VIL, f = 10MHz, IOUT = 0mA
E = VSS, f = 10MHz, IOUT = 0mA
E = VIH, RP = VIH
mA
mA
mA
(1, 3)
ICC
60
3
(3)
ICC1
E = VCC ± 0.2V,
RP = VCC ± 0.2V
Supply Current (Standby) CMOS
130
80
µA
µA
Supply Current (Power Down)
CMOS
(3)
ICC2
RP = VSS ± 0.2V
ICC3
ICC4
Supply Current (Program)
Supply Current (Erase)
Program in progress
Erase in progress
50
30
10
mA
mA
mA
(2)
ICC5
Supply Current (Erase Suspend)
E = VIH, Erase suspended
Program Leakage Current (Read or
Standby)
IPP
VPP > VCC
200
µA
IPP1
IPP2
IPP3
IPP4
IPP5
VIL
Program Current (Read or Standby)
Program Current (Power Down)
Program Current (Program)
Program Current (Erase)
Program Current (Erase Suspend)
Input Low Voltage
V
PP ≤ VCC
±15
5
µA
µA
mA
mA
µA
V
RP = VSS ± 0.2V
Program in progress
Erase in progress
Erase suspended
30
30
200
–0.5
2
0.8
VIH
Input High Voltage
VCC + 0.5
0.45
V
VOL
VOH
VPPL
Output Low Voltage
IOL = 5.8mA
V
Output High Voltage
IOH = –2.5mA
2.4
0
V
Program Voltage (Normal operation)
6.5
V
Program Voltage (Program or Erase
operations)
VPPH
11.4
11.4
12.6
V
VID
IID
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
13
V
A9 = VID
500
µA
Supply Voltage (Erase and Program
lock-out)
VLKO
VHH
2
V
V
Input Voltage (RP, Boot unlock)
Boot Block Program or Erase
11.4
13
Notes: 1. Automatic Power Saving reduces ICC to ≤ 8mA typical in static operation.
2. Current increases to ICC + ICC5 during a read operation.
3. CMOS levels VCC ± 0.2V and VSS ± 0.2V. TTL levels VIH and VIL.
9/34
M28F411, M28F421
Table 13. Read AC Characteristics (1)
(TA = 0 to70°C, –20 to 85°C or –40 to 85°C; VPP = 12V ± 5%)
M28F411 / 421
-80 -100
CC = 5V ± 5% VCC = 5V ± 10% VCC = 5V ± 10% VCC = 5V ± 10%
-70
-120
Symbol
Alt
Parameter
Unit
V
SRAM
Interface
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
Min
Max
Address Valid to Next
Address Valid
tAVAV
tAVQV
tPHQV
tRC
tACC
tPWH
tLZ
70
80
100
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to
Output Valid
70
80
100
300
120
300
Power Down High to
Output Valid
300
300
Chip Enable Low to
Output Transition
(2)
tELQX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chip Enable Low to
Output Valid
(3)
tELQV
tCE
70
35
25
25
80
40
30
30
100
45
120
50
Output Enable Low
to Output Transition
(2)
tGLQX
tOLZ
tOE
tOH
tHZ
Output Enable Low
to Output Valid
(3)
tGLQV
Chip Enable High to
Output Transition
(2)
tEHQX
Chip Enable High to
Output Hi-Z
(2)
tEHQZ
35
35
Output Enable High
to Output Transition
(2)
tGHQX
tOH
tDF
Output Enable High
to Output Hi-Z
(2)
tGHQZ
35
35
Address Transition to
Output Transition
(2)
tAXQX
tOH
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Sampled only, not 100% tested.
3. G may bedelayed by up to tELQV - tGLQV after the fallingedge of E without increasing tELQV
.
10/34
M28F411, M28F421
Table 14. Read AC Characteristics (1)
(TA = –40 to 125°C; VPP = 12V ± 5%)
M28F411 / 421
-90 -100
-80
-120
Unit
Symbol
Alt
Parameter
V
CC = 5V ± 5% VCC = 5V ± 10% VCC = 5V ± 10% VCC = 5V ± 10%
SRAM
Interface
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
Min
Max
Address Valid to Next
Address Valid
tAVAV
tAVQV
tPHQV
tRC
tACC
tPWH
tLZ
80
90
100
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to
Output Valid
80
90
100
300
120
300
Power Down High to
Output Valid
300
300
Chip Enable Low to
Output Transition
(2)
tELQX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chip Enable Low to
Output Valid
(3)
tELQV
tCE
80
40
30
30
90
45
35
35
100
50
120
55
Output Enable Low
to Output Transition
(2)
tGLQX
tOLZ
tOE
tOH
tHZ
Output Enable Low
to Output Valid
(3)
tGLQV
Chip Enable High to
Output Transition
(2)
tEHQX
Chip Enable High to
Output Hi-Z
(2)
tEHQZ
40
45
Output Enable High
to Output Transition
(2)
tGHQX
tOH
tDF
Output Enable High
to Output Hi-Z
(2)
tGHQZ
40
45
Address Transition to
Output Transition
(2)
tAXQX
tOH
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Sampled only, not 100% tested.
3. G may bedelayed by up to tELQV - tGLQV after the fallingedge of E without increasing tELQV
.
11/34
M28F411, M28F421
Figure 5. Read Mode AC Waveforms
12/34
M28F411, M28F421
Table 15A. Write AC Characteristics,Write Enable Controlled (1)
(TA = 0 to70°C, –20 to 85°C or –40 to 85°C; VPP = 12V ± 5%)
M28F411 / 421
-70
-80
Symbol
Alt
Parameter
Unit
V
CC = 5V ± 5%
VCC = 5V ± 10%
SRAM
Interface
EPROM
Interface
Min
Max
Min
80
210
0
Max
tAVAV
tPHWL
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWH
tWC
tPS
tCS
tWP
tDS
tDH
tCH
Write Cycle Time
70
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power Down High to Write Enable Low
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Data Valid to Write Enable High
50
50
0
50
50
0
Write Enable High to Data Transition
Write Enable High to Chip Enable High
10
20
50
10
30
50
tWPH Write Enable High to Write Enable Low
tAS
Address Validto Write Enable High
Power Down VHH (Boot Block Unlock) to Write
Enable High
(5)
tPHHWH
tPHS
100
100
ns
(5)
tVPHWH
tVPS VPP High to Write Enable High
100
10
6
100
10
6
ns
ns
µs
tWHAX
tAH
Write Enable High to Address Transition
Write Enable High to Output Valid
(2, 3)
(2, 3)
tWHQV1
tWHQV2
Write Enable High to Output Valid (Boot Block
Erase)
0.3
0.3
0.6
0.3
0.3
0.6
sec
sec
sec
Write Enable High to Output Valid (Parameter
Block Erase)
(2)
tWHQV3
Write Enable High to Output Valid (Main Block
Erase)
(2)
tWHQV4
(5)
tQVPH
tPHH Output Validto Reset/Power Down High
Output Validto VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
13/34
M28F411, M28F421
Table 15B. Write AC Characteristics,Write Enable Controlled (1)
(TA = 0 to70°C, –20 to 85°C or –40 to 85°C; VPP = 12V ± 5%)
M28F411 / 421
-100 -120
CC = 5V ± 10% VCC = 5V ± 10%
Symbol
Alt
Parameter
Unit
V
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
tAVAV
tPHWL
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWH
tWC Write Cycle Time
100
210
0
120
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPS
tCS
Power Down High to Write Enable Low
Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
60
60
0
70
60
0
tDS
tDH
tCH
Data Valid to Write Enable High
Write Enable High to Data Transition
Write Enable High to Chip Enable High
10
40
60
10
50
60
tWPH Write Enable High to Write Enable Low
tAS
Address Valid to Write Enable High
Power Down VHH (Boot Block Unlock) to Write
Enable High
(5)
tPHHWH
tPHS
100
100
ns
(5)
tVPHWH
tVPS VPP High to Write Enable High
100
10
7
100
10
7
ns
ns
µs
tWHAX
tAH
Write Enable High to Address Transition
Write Enable High to Output Valid
(2, 3)
(2, 3)
tWHQV1
tWHQV2
Write Enable High to Output Valid (Boot Block
Erase)
0.4
0.4
0.7
0.4
0.4
0.7
sec
sec
sec
Write Enable High to Output Valid (Parameter
Block Erase)
(2)
tWHQV3
Write Enable High to Output Valid (Main Block
Erase)
(2)
tWHQV4
(5)
tQVPH
tPHH Output Valid to Reset/Power Down High
Output Valid to VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
14/34
M28F411, M28F421
Table 16A. Write AC Characteristics,Write Enable Controlled (1)
(TA = –40 to 125°C; VPP = 12V ± 5%)
M28F411 / 421
-80
-90
Symbol
Alt
Parameter
Unit
V
CC = 5V ± 5%
VCC = 5V ± 10%
SRAM
Interface
EPROM
Interface
Min
Max
Min
90
210
0
Max
tAVAV
tPHWL
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWH
tWC
tPS
tCS
tWP
tDS
tDH
tCH
Write Cycle Time
80
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power Down High to Write Enable Low
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Data Valid to Write Enable High
50
50
0
60
60
0
Write Enable High to Data Transition
Write Enable High to Chip Enable High
10
30
50
10
40
60
tWPH Write Enable High to Write Enable Low
tAS
Address Validto Write Enable High
Power Down VHH (Boot Block Unlock) to Write
Enable High
(5)
tPHHWH
tPHS
100
100
ns
(5)
tVPHWH
tVPS VPP High to Write Enable High
100
10
6
100
10
7
ns
ns
µs
tWHAX
tAH
Write Enable High to Address Transition
Write Enable High to Output Valid
(2, 3)
(2, 3)
tWHQV1
tWHQV2
Write Enable High to Output Valid (Boot Block
Erase)
0.3
0.3
0.6
0.4
0.4
0.7
sec
sec
sec
Write Enable High to Output Valid (Parameter
Block Erase)
(2)
tWHQV3
Write Enable High to Output Valid (Main Block
Erase)
(2)
tWHQV4
(5)
tQVPH
tPHH Output Validto Reset/Power Down High
Output Validto VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
15/34
M28F411, M28F421
Table 16B. Write AC Characteristics,Write Enable Controlled (1)
(TA = –40 to 125°C; VPP = 12V ± 5%)
M28F411 / 421
-100 -120
CC = 5V ± 10% VCC = 5V ± 10%
Symbol
Alt
Parameter
Unit
V
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
tAVAV
tPHWL
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWH
tWC Write Cycle Time
100
210
0
120
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPS
tCS
Power Down High to Write Enable Low
Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
60
60
0
70
60
0
tDS
tDH
tCH
Data Valid to Write Enable High
Write Enable High to Data Transition
Write Enable High to Chip Enable High
10
40
60
10
50
60
tWPH Write Enable High to Write Enable Low
tAS
Address Valid to Write Enable High
Power Down VHH (Boot Block Unlock) to Write
Enable High
(5)
tPHHWH
tPHS
100
100
ns
(5)
tVPHWH
tVPS VPP High to Write Enable High
100
10
7
100
10
7
ns
ns
µs
tWHAX
tAH
Write Enable High to Address Transition
Write Enable High to Output Valid
(2, 3)
(2, 3)
tWHQV1
tWHQV2
Write Enable High to Output Valid (Boot Block
Erase)
0.4
0.4
0.7
0.4
0.4
0.7
sec
sec
sec
Write Enable High to Output Valid (Parameter
Block Erase)
(2)
tWHQV3
Write Enable High to Output Valid (Main Block
Erase)
(2)
tWHQV4
(5)
tQVPH
tPHH Output Valid to Reset/Power Down High
Output Valid to VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
16/34
M28F411, M28F421
Figure 6. Program & Erase AC Waveforms, W Controlled
17/34
M28F411, M28F421
Table 17A. Write AC Characteristics, Chip Enable Controlled (1)
(TA = 0 to70°C, –20 to 85°C or –40 to 85°C; VPP = 12V ± 5%)
M28F411 / 421
-70
-80
Symbol
Alt
Parameter
Unit
V
CC = 5V ± 5% VCC = 5V ± 10%
SRAM
Interface
EPROM
Interface
Min
Max
Min
Max
tAVAV
tPHEL
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEH
tWC
tPS
Write Cycle Time
70
210
0
80
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power Down High to Chip Enable Low
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Data Valid to Chip Enable High
tCS
tWP
tDS
50
50
0
50
50
0
tDH
tCH
tWPH
tAS
Chip Enable High to Data Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable High
10
20
50
10
30
50
Power Down VHH (Boot Block Unlock) to Chip
Enable High
(5)
tPHHEH
tPHS
100
100
ns
(5)
tVPHEH
tVPS
tAH
VPP High to Chip Enable High
100
10
6
100
10
6
ns
ns
µs
tEHAX
Chip Enable High to Address Transition
Chip Enable High to Output Valid
(2, 3)
tEHQV1
Chip Enable High to Output Valid (Boot Block
Erase)
(2, 3)
tEHQV2
0.3
0.3
0.6
0.3
0.3
0.6
sec
sec
sec
Chip Enable High to Output Valid (Parameter
Block Erase)
(2)
tEHQV3
Chip Enable High to Output Valid (Main Block
Erase)
(2)
tEHQV4
(5)
tQVPH
tPHH
Output Valid to Reset/Power Down High
Output Valid to VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
18/34
M28F411, M28F421
Table 17B. Write AC Characteristics, Chip Enable Controlled (1)
(TA = 0 to70°C, –20 to 85°C or –40 to 85°C; VPP = 12V ± 5%)
M28F411 / 421
-100 -120
CC = 5V ± 10% VCC = 5V ± 10%
Symbol
Alt
Parameter
Unit
V
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
tAVAV
tPHEL
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEH
tWC
tPS
Write Cycle Time
100
210
0
120
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power Down High to Chip Enable Low
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Data Valid to Chip Enable High
tCS
tWP
tDS
60
60
0
70
60
0
tDH
tCH
tWPH
tAS
Chip Enable High to Data Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable High
10
40
60
10
50
60
Power Down VHH (Boot Block Unlock) to Chip
Enable High
(5)
tPHHEH
tPHS
100
100
ns
(5)
tVPHEH
tVPS
tAH
VPP High to Chip Enable High
100
10
7
100
10
7
ns
ns
µs
tEHAX
Chip Enable High to Address Transition
Chip Enable High to Output Valid
(2, 3)
tEHQV1
Chip Enable High to Output Valid (Boot Block
Erase)
(2, 3)
tEHQV2
0.4
0.4
0.7
0.4
0.4
0.7
sec
sec
sec
Chip Enable High to Output Valid (Parameter
Block Erase)
(2)
tEHQV3
Chip Enable High to Output Valid (Main Block
Erase)
(2)
tEHQV4
(5)
tQVPH
tPHH
Output Valid to Reset/Power Down High
Output Valid to VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
19/34
M28F411, M28F421
Table 18A. Write AC Characteristics, Chip Enable Controlled (1)
(TA = –40 to 125°C; VPP = 12V ± 5%)
M28F411 / 421
-80
-90
Symbol
Alt
Parameter
Unit
V
CC = 5V ± 5% VCC = 5V ± 10%
SRAM
Interface
EPROM
Interface
Min
Max
Min
Max
tAVAV
tPHEL
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEH
tWC
tPS
Write Cycle Time
80
210
0
90
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power Down High to Chip Enable Low
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Data Valid to Chip Enable High
tCS
tWP
tDS
50
50
0
60
60
0
tDH
tCH
tWPH
tAS
Chip Enable High to Data Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable High
10
30
50
10
40
60
Power Down VHH (Boot Block Unlock) to Chip
Enable High
(5)
tPHHEH
tPHS
100
100
ns
(5)
tVPHEH
tVPS
tAH
VPP High to Chip Enable High
100
10
6
100
10
7
ns
ns
µs
tEHAX
Chip Enable High to Address Transition
Chip Enable High to Output Valid
(2, 3)
tEHQV1
Chip Enable High to Output Valid (Boot Block
Erase)
(2, 3)
tEHQV2
0.3
0.3
0.6
0.4
0.4
0.7
sec
sec
sec
Chip Enable High to Output Valid (Parameter
Block Erase)
(2)
tEHQV3
Chip Enable High to Output Valid (Main Block
Erase)
(2)
tEHQV4
(5)
tQVPH
tPHH
Output Valid to Reset/Power Down High
Output Valid to VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
20/34
M28F411, M28F421
Table 18B. Write AC Characteristics, Chip Enable Controlled (1)
(TA = -40 to 125°C; VPP = 12V ± 5%)
M28F411 / 421
-100 -120
CC = 5V ± 10% VCC = 5V ± 10%
Symbol
Alt
Parameter
Unit
V
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
tAVAV
tPHEL
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEH
tWC
tPS
Write Cycle Time
100
210
0
120
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power Down High to Chip Enable Low
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Data Valid to Chip Enable High
tCS
tWP
tDS
60
60
0
70
60
0
tDH
tCH
tWPH
tAS
Chip Enable High to Data Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable High
10
40
60
10
50
60
Power Down VHH (Boot Block Unlock) to Chip
Enable High
(5)
tPHHEH
tPHS
100
100
ns
(5)
tVPHEH
tVPS
tAH
VPP High to Chip Enable High
100
10
7
100
10
7
ns
ns
µs
tEHAX
Chip Enable High to Address Transition
Chip Enable High to Output Valid
(2, 3)
tEHQV1
Chip Enable High to Output Valid (Boot Block
Erase)
(2, 3)
tEHQV2
0.4
0.4
0.7
0.4
0.4
0.7
sec
sec
sec
Chip Enable High to Output Valid (Parameter
Block Erase)
(2)
tEHQV3
Chip Enable High to Output Valid (Main Block
Erase)
(2)
tEHQV4
(5)
tQVPH
tPHH
Output Valid to Reset/Power Down High
Output Valid to VPP Low
0
0
0
0
ns
ns
ns
(5)
tQVVPL
(4, 5)
tPHBR
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 =’1’.
3. For Program or Erase of the Boot Block RP must be at VHH
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
.
21/34
M28F411, M28F421
Figure 7. Program & Erase AC Waveforms, E Controlled
22/34
M28F411, M28F421
Table 19. Byte Program, Erase Times
(TA = 0 to70°C; VCC = 5V ± 10% or 5V ± 5%)
M28F411 / 421
Parameter
Test Conditions
Unit
Min
Typ
1.2
1
Max
4.2
7
Main Block Program
V
PP = 12V ±5%
VPP = 12V ±5%
PP = 12V ±5%
sec
sec
sec
Boot or Parameter Block Erase
Main Block Erase
V
2.4
14
Table 20. Byte Program, Erase Times
(TA = –20 to 85°C, –-40 to 85°C or –40 to 125°C; VCC = 5V ± 10% or 5V ± 5%)
M28F411 / 421
Parameter
Test Conditions
Unit
Min
Typ
1.4
1.5
3
Max
5
Main Block Program
V
V
V
PP = 12V ±5%
PP = 12V ±5%
PP = 12V ±5%
sec
sec
sec
Boot or Parameter Block Erase
Main Block Erase
10.5
18
DEVICE OPERATION (cont’d)
input A0 isLow and thedevicecodewhen this input
is High. Other Address inputs are ignored.
Output Disable. The data outputsare high imped-
ance when the Output Enable G is High with Write
Enable W High.
Instructions and Commands
The memories include a Command Interface (C.I.)
which latches commands written to the memory.
Instructions are made up from one or more com-
mands to perform memory Read, Read Status
Register, Read Electronic Signature, Erase, Pro-
gram, Clear Status Register, Erase Suspend and
Erase Resume. These instructions require from 1
to 3 operations, the first of which is always a write
operation and is followed by either a further write
operation to confirm the first command or a read
operation(s)to output data.
Standby. The memory is in standbywhen the Chip
Enable E is High. The power consumption is re-
duced tothe standby leveland the outputsare high
impedance, independent of the Output Enable G
or Write Enable Winputs.
Power Down. Thememory is in PowerDownwhen
RP is low. The power consumption is reduced to
the Power Down level, and Outputs are in high
impedance, independant of the Chip Enable E,
Output Enable G or Write Enable W inputs.
A Status Register indicates the P/E.C. status
Ready or Busy, the suspend/in-progressstatus of
erase operations, the failure/success of erase and
program operations and the low/correct value of
the Program Supply voltage VPP.
Electronic Signature. Two codes identifying the
manufacturerand the device can be read from
the memories, the manufacturer code for SGS-
THOMSON is 20h, and the device codes are 0F6h
for the M28F411(Top Boot Block) and 0FEh for the
M28F421 (Bottom Boot Block). These codes allow
programming equipment or applications to auto-
maticallymatchtheirinterfacetothe characteristics
of the particular manufacturer’sproduct.
The P/E.C. automatically sets bits b3 to b7 and
clears bit b6 & b7. It cannot clear bits b3 to b5. The
register can be read by the Read Status Register
(RSR) instruction and cleared by the Clear Status
Register (CLRS) instruction. The meaning of the
bits b3 to b7 is shown in Table 7. Bits b0 to b2 are
reserved for future use (and should be masked out
during status checks).
The Electronic Signatureis output by a Read Array
operation when the voltage applied to A9 is at VID,
the manufacturercode is output when the Address
23/34
M28F411, M28F421
Figure 8. Memory Map, Byte-wide Addresses
M28F411 TOP BOOT BLOCK
M28F421 BOTTOM BOOT BLOCK
A0-A18
7FFFFh
Byte Wide
A0-A18
Byte Wide
7FFFFh
16K BOOT BLOCK
128K MAIN BLOCK
7C000h
7BFFFh
60000h
5FFFFh
8K PARAMETER BLOCK
8K PARAMETER BLOCK
96K MAIN BLOCK
128K MAIN BLOCK
128K MAIN BLOCK
7A000h
79FFFh
40000h
3FFFFh
78000h
77FFFh
20000h
1FFFFh
96K MAIN BLOCK
60000h
5FFFFh
08000h
07FFFh
128K MAIN BLOCK
128K MAIN BLOCK
128K MAIN BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
16K BOOT BLOCK
40000h
3FFFFh
06000h
05FFFh
20000h
1FFFFh
04000h
03FFFh
00000h
00000h
AI01291
Read (RD) instruction. TheRead instruction con-
sists of one write operation giving the command
0FFh. Subsequent read operations will read the
addressed memory array content.
Erase Set-up command 20h. The second com-
mand isthe EraseConfirm command 0D0h.During
theinputof the secondcommand anaddressofthe
block to be erased is given and this is latchedinto
the memory. If the second command given is not
the Erase Confirm command then the status regis-
ter bitsb4 and b5 areset andthe instructionaborts.
Read operations output the status register after
erasure has started.
Read Status Register (RSR) instruction. The
Read Status Register instruction may be given at
any time, including while the Program/Erase Con-
troller is active. It consists of one write operation
givingthecommand70h. SubsequentRead opera-
tions output the contents of the Status Register.
The contents of the status register are latched on
the falling edge of E or G signals, and can be read
until E or G returns to its initial high level. Either E
or G must be toggled to VIH to update the latch.
Additionally, any read attempt during program or
erase operation will automatically output the con-
tents of the Status Register.
During theexecutionofthe erase bythe P/E.C.,the
memory accepts only the RSR (Read Status Reg-
ister) and ES (Erase Suspend)instructions. Status
Register bit b7 returns ’0’ while the erasure is in
progress and ’1’ when it has completed. After com-
pletion the Status Register bit b5 returns’1’ if there
has been an Erase Failure because erasure has
not been verified even after the maximum number
of erase cycles have been executed. Status Reg-
isterbit b3returns’1’ if VPP doesnot remain at VPPH
level when theerasure is attemptedand/orproced-
ing.
Read Electronic Signature (RSIG) instruction.
Thisinstructionuses3operations.Itconsists ofone
write operation giving the command 90h followed
by two read operationsto outputthe manufacturer
and device codes. The manufacturercode, 20h, is
output when the address line A0 is Low, and the
device code, 0F6h for the M28F411 or0FEh forthe
M28F421, when A0 is High.
VPP must be at VPPH when erasing, erase should
not be attempted when VPP < VPPH as the results
willbe uncertain. If VPP fallsbelow VPPH orRP goes
Low the erase aborts and must be repeated, after
having cleared the Status Register (CLRS). The
Boot Block can only be erased when RP is also at
Erase (EE) instruction. This instruction uses two
write operations. The first command written is the
VHH.
24/34
M28F411, M28F421
Program (PG) instruction. This instruction uses
two write operations.The first command written is
the Program Set-up command 40h (or 10h). A
secondwrite operationlatchesthe Addressandthe
Data to be written and starts the P/E.C. Read
operations output the status register after the pro-
gramming has started.
Erase Resume (ER) instruction. If an Erase Sus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 0D0h. The status register bit b6 is
cleared when erasure resumes. Read operations
output the status register after the erase is re-
sumed. The suggested flow charts for programs
that use the programming,erasure and erase sus-
pend/resumefeatures of the memories are shown
in Figure 9 to Figure 11.
Memory programming is only made bywriting ’0’ in
place of ’1’ in a byte.
During the execution of the programming by the
P/E.C., the memory accepts only the RSR (Read
StatusRegister)instruction.The StatusRegisterbit
b7 returns’0’ while the programming is in progress
and ’1’ when it hascompleted. After completionthe
Status register bit b4 returns ’1’ if there has been a
Program Failure. Status Register bit b3 returns a
’1’ if VPP does not remain at VPPH when program-
ming is attempted and/or during programming.
VPP mustbe at VPPH whenprogramming, program-
ming should not be attempted when VPP < VPPH
as the results will be uncertain. Programming
aborts if VPP drops below VPPH or RP goes Low. If
aborted the data may be incorrect. Then after
having cleared the Status Register (CLRS), the
memory must be erased and re-programmed.
Programming. The memory can be programmed
byte-by-byte. The Program Supply voltage VPP
must be applied before program instructions are
given, and if the programming is in the Boot Block,
RP must also be raised to VHH to unlock the Boot
Block. TheProgram Supplyvoltagemay be applied
continuously during programming. The program
sequence is started by writing a Program Set-up
command (40h) to the Command Interface, thisis
followed by writing the address and data byte or
word tothememory. TheProgram/EraseController
automaticallystarts andperformstheprogramming
after the second write operation, providing that the
VPP voltage (and RP voltage if programming the
Boot Block) are correct. During the programming
the memorystatus is checkedby readingthe status
registerbit b7 which shows the status of the P/E.C.
Bit b7 = ’1’ indicates that programming is com-
pleted.
The Boot Block can onlybe programmed when RP
is at VHH
.
Clear Status Register (CLRS) instruction. The
Clear Status Register uses a single write operation
which clears bits b3, b4 and b5, if latched to ’1’ by
the P/E.C., to ’0’. Its use is necessary before any
new operation when an error has been detected.
A full status check can be made after each
byte/word or after a sequence of data has been
programmed. The status check is made on bit b3
for any possible VPP error and on bit b4 for any
possible programming error.
Erase Suspend (ES) instruction. The Erase op-
erationmay be suspended bythis instructionwhich
consists of writing the command 0B0h. The Status
Register bit b6 indicates whether the erase has
actually been suspended,b6 = ’1’, or whether the
P/E.C. cycle was the last and the erase is com-
pleted, b6 = ’0’. During the suspension the memory
will respond only to Read (RD), Read Status Reg-
ister (RSR) or Erase Resume (ER) instructions.
Read operations initially output the status register
while erase is suspended but, following a Read
instruction, data from other blocks of the memory
can be read. VPP must be maintained at VPPH while
eraseis suspended.If VPP doesnot remain atVPPH
or the RP signal goes Low while erase is sus-
pended then erase is aborted while bits b5 and b3
of the status register are set. Erase operationmust
be repeated after having cleared the status regis-
ter, to be certain to erase the block.
Erase. Thememory can be erased by blocks. The
Program Supply voltage VPP must be applied be-
fore the Erase instruction is given, and if the Erase
is of the Boot Block RP must also be raised to VHH
to unlock the Boot Block. The Erase sequence is
started by writing an Erase Set-up command (20h)
to the Command Interface, this is followed by an
address in the block to be erased and the Erase
Confirm command (0D0h). The Program/Erase
Controller automatically starts and performs the
block erase, providing the VPP voltage (and the RP
voltage if the erase is of the Boot Block) is correct.
During the erase the memory status is checked by
reading the status register bit b7 which shows the
status ofthe P/E.C. Bit b7 =’1’ indicates that erase
is completed.
A full status check can be made after the block
erase by checkingbit b3 for any possible VPP error,
bits b5 and b6 for any command sequence errors
(erase suspended) and bit b5 alone for an erase
error.
25/34
M28F411, M28F421
Recovery from deep power down requires 300ns
to a memory read operation, or 210ns to a com-
mand write. On return from power down the status
register is cleared to 00h.
Reset. Note that after any program or erase in-
struction has completed with an error indication or
after any VPP transitions down to VPPL the Com-
mand Interface must be reset by a Clear Status
Register Instruction before data can be accessed.
Power Up
Automatic Power Saving
The Supply voltage VCC and the Program Supply
voltage VPP canbe applied in any order. The mem-
ory Command Interface is reset on power up to
Read Memory Array, but a negative transition of
Chip Enable E or a change of the addresses is
required to ensure valid data outputs. Care must
be taken to avoid writes to the memory when VCC
is above VLKO and VPP powers up first. Writes can
be inhibited by driving either E or W to VIH. The
memory is disabled until RP is up to VIH.
The M28F411 and M28F421 memories place
themselvesin a lower power state when not being
accessed. Following a Read operation, after a
delayequaltothe memory access time, the Supply
Current is reduced from a typical read current of
25mA (CMOS inputs) to less than 2mA.
Power Down
The memories provide a power down control input
RP. When this signal is taken to below VSS + 0.2V
all internal circuits are switched off and the supply
current drops to typically 0.2µA and the program
current to typically 0.1µA. If RP is taken low during
a memory read operation then the memory is
de-selected and the outputs become high imped-
ance. If RP is taken low during a program or erase
sequencethen it is aborted and the memory con-
tent is no longer valid.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling, each device in a system should
have the VCC andVPP railsdecoupled with a0.1µF
capacitor close to the VCC and VSS pins. The PCB
trace widths should be sufficient to carry the VPP
programand erase currents required.
26/34
M28F411, M28F421
Figure 9. Program Flow-chart and Pseudo Code
Start
Write 40h
Command
PG instruction:
– write 40h command
– write Address & Data
(memory enters read status
state after the PG instruction)
Write Address
& Data
Read Status
Register
do:
– read status register
(E or G must be toggled)
NO
b7 = 1
while b7 = 1
YES
NO
NO
V
Low
If b3 = 0, V
low error:
– error handler
PP
PP
b3 = 0
YES
Error (1, 2)
Program
Error (1, 2)
If b4 = 0, Program error:
– error handler
b4 = 0
YES
End
AI01278
Notes: 1. Status check of b3 (VPP Low) and b4 (Program Error) can be made after each byte/word programming or after a sequence.
2. If a VPP Low or Program Erase is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
27/34
M28F411, M28F421
Figure 10. Erase Flow-chart and Pseudo Code
Start
Write 20h
Command
EE instruction:
– write 20h command
– write Block Address
(A12-A17) & command 0D0h
(memory enters read status
state after the EE instruction)
Write Block Address
& 0D0h Command
Suspend
Loop
NO
do:
Read Status
– read status register
(E or G must be toggled)
if EE instruction given execute
suspend erase loop
Register
Suspend
YES
NO
NO
NO
NO
b7 = 1
YES
while b7 = 1
V
Low
If b3 = 0, V
low error:
PP
PP
– error handler
b3 = 0
YES
Error (1)
Command
Sequence Error
If b4, b5 = 0, Command Sequence error:
– error handler
b4, b5 = 1
YES
Erase
If b5 = 0, Erase error:
– error handler
b5 = 0
Error (1)
YES
End
AI01279
Note: 1. If VPP Low or Erase Error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
28/34
M28F411, M28F421
Figure 11. Erase Suspend & Resume Flow-chart and Pseudo Code
Start
Write 0B0h
Command
ES instruction:
– write 0B0h command
(memory enters read register
state after the ES instruction)
do:
Read Status
Register
– read status register
(E or G must be toggled)
NO
NO
b7 = 1
YES
while b7 = 1
If b6 = 0, Erase completed
(at this point the memory wich
accept only the RD or ER instruction)
Erase
Complete
b6 = 1
YES
Write 0FFh
Command
RD instruction:
– write 0FFh command
– one o more data reads
from another block
Read data from
another block
Write 0D0h
Command
ER instruction:
– write 0D0h command
to resume erasure
Erase Continues
AI01280
29/34
M28F411, M28F421
Figure 12. Command Interface and Program Erase Controller Flow-diagram (a)
WAIT FOR
COMMAND
WRITE (1)
NO
90h
YES
BYTE
IDENTIFIER
NO
70h
YES
READ
ARRAY
READ
STATUS
NO
50h
YES
CLEAR
STATUS
NO
40h or
10h
YES
PROGRAM
SET-UP
NO
20h
YES
READ
STATUS
PROGRAM
ERASE
SET-UP
NO
0FFh
YES
YES
READY
(2)
NO
OD0h
NO
YES
ERASE
COMMAND
ERROR
READ
STATUS
A
B
AI01286C
Notes: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or
if VCC falls below VLKO, the Command Interface defaults to Read Array mode.
2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
30/34
M28F411, M28F421
Figure 13. Command Interface and Program Erase Controller Flow-diagram (b)
A
B
ERASE
(READ STATUS)
YES
READY
(2)
NO
NO
0B0h
YES
READ
STATUS
ERASE
SUSPEND
YES
READY
(2)
NO
ERASE
SUSPENDED
?
NO
READ
STATUS
YES
YES
NO
70h
NO
READ
STATUS
YES
0D0h
READ
ARRAY
READ
STATUS
(ERASE RESUME)
AI01287B
Note: 2. P/E.C. status(Ready or Busy) is read on Status Register bit 7.
31/34
M28F411, M28F421
ORDERING INFORMATION SCHEME
Example:
M28F411 -80 X
N
1
TR
VCC Range
Array Org.
Top Boot
Temp. Range
Option
F
5V
1
2
1
3
5
6
0 to 70 °C
TR Tape & Reel
Packing
Bottom Boot
–40 to 125 °C
–20 to 85 °C
–40 to 85 °C
Speed
Power Supplies
Package
-70 70ns
-80 80ns
-90 90ns
-100 100ns
-120 120ns
blank VCC ± 10%,
N
TSOP40
10 x 20mm
V
PP ± 5%
X
V
V
CC ± 5%,
PP ± 5%
For a list of available options(VCC Range, Array Organisation, Speed, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest
to you.
32/34
M28F411, M28F421
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm
mm
Min
inches
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
10.10
-
Typ
Min
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.398
-
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
9.90
-
0.002
0.037
0.007
0.004
0.780
0.720
0.390
-
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
40
40
CP
0.10
0.004
TSOP40
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale
33/34
M28F411, M28F421
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany -Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.
34/34
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